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Irith Pomeranz
Person information
- affiliation: Purdue University, School of Electrical and Computer Engineering, West Lafayette, IN, USA
- affiliation: University of Iowa, Department of Electrical and Computer Engineering, Iowa City, IA, USA
- affiliation (PhD 1989): Technion, Department of Electrical Engineering, Israel
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2020 – today
- 2025
- [j330]Irith Pomeranz
:
Arranging a Pool of Functional Test Sequences for Variable In-Field Test Periods. IEEE Access 13: 10009-10021 (2025) - [j329]Irith Pomeranz
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SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard Scan. ACM Trans. Design Autom. Electr. Syst. 30(1): 1-13 (2025) - 2024
- [j328]Irith Pomeranz
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Longest Path Selection Based on Path Identifiers. IEEE Access 12: 14512-14520 (2024) - [j327]Irith Pomeranz
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Sharing of Topped-Off Compressed Test Sets Among Logic Blocks. IEEE Access 12: 49895-49903 (2024) - [j326]Irith Pomeranz
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Functional Compaction for Functional Test Sequences. IEEE Access 12: 98130-98140 (2024) - [j325]Irith Pomeranz
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Weak and Strong Non-Robust Tests for Functionally Possible Path Delay Faults. IEEE Access 12: 156651-156661 (2024) - [j324]Irith Pomeranz
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Conventional Tests for Approximate Scan Logic. IEEE Des. Test 41(3): 5-13 (2024) - [j323]Irith Pomeranz
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Dynamic Test Compaction of a Compressed Test Set Shared Among Logic Blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 394-402 (2024) - [j322]Jerin Joe
, Nilanjan Mukherjee
, Irith Pomeranz
, Janusz Rajski
:
Generation of Two-Cycle Tests for Structurally Similar Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 694-703 (2024) - [j321]Irith Pomeranz
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Test Insertion for Dynamic Test Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1302-1306 (2024) - [j320]Irith Pomeranz
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Test Generation for Functionally Possible Subpaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(12): 4841-4851 (2024) - [j319]Irith Pomeranz
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Functional Design-for-Testability for Functional Test Sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(12): 4852-4859 (2024) - [j318]Irith Pomeranz
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Unconstrained-Activation Functional-Detection Scan-Based Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(12): 4860-4864 (2024) - [j317]Irith Pomeranz
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Reduced On-chip Storage of Seeds for Built-in Test Generation. ACM Trans. Design Autom. Electr. Syst. 29(3): 45:1-45:16 (2024) - [j316]Irith Pomeranz
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Two-dimensional Search Space for Extracting Broadside Tests from Functional Test Sequences. ACM Trans. Design Autom. Electr. Syst. 29(3): 48:1-48:13 (2024) - [j315]Irith Pomeranz
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Testability Evaluation for Local Design Modifications. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 195-199 (2024) - [j314]Irith Pomeranz
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Bit-Complemented Test Data to Replace the Tail of a Fault Coverage Curve. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 609-618 (2024) - [j313]Irith Pomeranz
, Yervant Zorian:
Functionally Possible Path Delay Faults With High Functional Switching Activity. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 2159-2163 (2024) - [c416]Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman:
Generating Storage-Aware Test Sets Targeting Several Fault Models. ISVLSI 2024: 15-20 - [c415]Irith Pomeranz:
Functionally-Possible Gate-Exhaustive Bridging Faults. ITC 2024: 31-35 - [c414]Hari Addepalli, Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski:
Delay Monitoring Under Different PVT Corners for Test and Functional Operation. ITC 2024: 157-166 - [c413]Subashini Gopalsamy, Irith Pomeranz:
A Storage Based LBIST Scheme for Logic Diagnosis. VTS 2024: 1-7 - [c412]Irith Pomeranz:
Test Compaction Using (k, 1)-Cycle Tests. VTS 2024: 1-7 - 2023
- [j312]Irith Pomeranz
:
Storage and Counter Based Logic Built-In Self-Test. IEEE Access 11: 139335-139344 (2023) - [j311]Irith Pomeranz
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Topping Off Test Sets Under Bounded Transparent Scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 341-345 (2023) - [j310]Irith Pomeranz
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Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test Set. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1336-1345 (2023) - [j309]Irith Pomeranz
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Estimating the Number of Extra Tests During Iterative Test Generation for Single-Cycle Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2752-2760 (2023) - [j308]Irith Pomeranz
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Storage-Based Logic Built-In Self-Test With Cyclic Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 3118-3122 (2023) - [j307]Irith Pomeranz
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Partially Specified Output Response for Reduced Fail Data Volume. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 3123-3127 (2023) - [j306]Irith Pomeranz
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Path Unselection for Path Delay Fault Test Generation. IEEE Trans. Very Large Scale Integr. Syst. 31(2): 267-275 (2023) - [j305]Irith Pomeranz
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Diagnostic Test Point Insertion and Test Compaction. IEEE Trans. Very Large Scale Integr. Syst. 31(2): 276-285 (2023) - [j304]Irith Pomeranz
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Sharing of Compressed Tests Among Logic Blocks. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 421-430 (2023) - [j303]Irith Pomeranz
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Test Data Compression for Transparent-Scan Sequences. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 601-605 (2023) - [j302]Irith Pomeranz
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Storage-Based Logic Built-In Self-Test With Partitioned Deterministic Compressed Tests. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1259-1268 (2023) - [j301]Irith Pomeranz
:
Dummy Faulty Units for Reduced Fail Data Volume From Logic Faults. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1754-1762 (2023) - [c411]Irith Pomeranz:
Compaction of Functional Broadside Tests for Path Delay Faults Using Clusters of Propagation Lines. ITC 2023: 105-110 - [c410]Subashini Gopalsamy, Irith Pomeranz:
Fully Deterministic Storage Based Logic Built-In Self-Test. VTS 2023: 1-7 - [c409]Irith Pomeranz:
Expanding a Pool of Functional Test Sequences to Support Test Compaction. VTS 2023: 1-7 - [c408]Irith Pomeranz:
Compact Set of Functional Broadside Tests with Fault Detection on Primary Outputs. VTS 2023: 1-7 - 2022
- [j300]Irith Pomeranz
:
Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 776-783 (2022) - [j299]Irith Pomeranz
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Static Test Compaction Using Independent Suffixes of a Transparent-Scan Sequence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 1130-1141 (2022) - [j298]Irith Pomeranz
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Multicycle Tests With Fault Detection Test Data for Improved Logic Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1587-1591 (2022) - [j297]Irith Pomeranz
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GEPDFs: Path Delay Faults Based on Two-Cycle Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2315-2322 (2022) - [j296]Irith Pomeranz
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Storage-Based Logic Built-in Self-Test With Multicycle Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3553-3557 (2022) - [j295]Irith Pomeranz
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Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4862-4872 (2022) - [j294]Irith Pomeranz
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Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5635-5643 (2022) - [j293]Irith Pomeranz
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Increasing the Fault Coverage of a Truncated Test Set. ACM Trans. Design Autom. Electr. Syst. 27(6): 54:1-54:16 (2022) - [j292]Irith Pomeranz
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Preponing Fault Detections for Test Compaction Under Transparent Scan. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1543-1547 (2022) - [j291]Irith Pomeranz
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Test Sequences for Faults in the Scan Logic. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1568-1572 (2022) - [j290]Irith Pomeranz
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Functional Test Sequences as a Source for Partially Functional Launch-on-Shift Tests. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1803-1807 (2022) - [c407]Irith Pomeranz:
Two-Dimensional Test Generation Objective. ATS 2022: 108-113 - [c406]Irith Pomeranz:
Selecting Path Delay Faults Through the Largest Subcircuits of Uncovered Lines. ATS 2022: 114-119 - [c405]Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman:
Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults. ATS 2022: 120-125 - [c404]Irith Pomeranz:
Usable Circuits with Imperfect Scan Logic. ATS 2022: 156-161 - [c403]Irith Pomeranz:
Storage-Based Logic Built-In Self-Test with Variable-Length Test Data. DFT 2022: 1-6 - [c402]Irith Pomeranz:
Compaction of Compressed Bounded Transparent-Scan Test Sets. ACM Great Lakes Symposium on VLSI 2022: 339-343 - [c401]Hari Addepalli, Irith Pomeranz:
Algorithms for the Selection of Applied Tests when a Stored Test Produces Many Applied Tests. ACM Great Lakes Symposium on VLSI 2022: 345-349 - [c400]Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski:
Test Generation for an Iterative Design Flow with RTL Changes. ITC 2022: 305-313 - [c399]Irith Pomeranz:
Transforming an $n$-Detection Test Set into a Test Set for a Variety of Fault Models. ITC 2022: 474-478 - [c398]Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski:
Fast Test Generation for Structurally Similar Circuits. VTS 2022: 1-7 - 2021
- [j289]Irith Pomeranz
:
Maximal Independent Fault Set for Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(3): 598-602 (2021) - [j288]Irith Pomeranz
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PRESERVE: Static Test Compaction that Preserves Individual Numbers of Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 803-807 (2021) - [j287]Irith Pomeranz
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Padding of LFSR Seeds for Reduced Input Test Data Volume. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 1004-1008 (2021) - [j286]Irith Pomeranz
, M. Enamul Amyeen:
Hybrid Pass/Fail and Full Fail Data for Reduced Fail Data Volume. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1711-1720 (2021) - [j285]Irith Pomeranz
:
Storage-Based Built-In Self-Test for Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2189-2193 (2021) - [j284]Irith Pomeranz, M. Enamul Amyeen:
Logic Diagnosis with Hybrid Fail Data. ACM Trans. Design Autom. Electr. Syst. 26(3): 19:1-19:13 (2021) - [j283]Irith Pomeranz:
Covering Test Holes of Functional Broadside Tests. ACM Trans. Design Autom. Electr. Syst. 26(3): 23:1-23:15 (2021) - [j282]Irith Pomeranz:
Equivalent Faults under Launch-on-Shift (LOS) Tests with Equal Primary Input Vectors. ACM Trans. Design Autom. Electr. Syst. 26(4): 25:1-25:15 (2021) - [j281]Irith Pomeranz
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Partitioning Functional Test Sequences Into Multicycle Functional Broadside Tests. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 89-99 (2021) - [j280]Irith Pomeranz
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Test Compaction by Backward and Forward Extension of Multicycle Tests. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 242-246 (2021) - [j279]Irith Pomeranz
, Xijiang Lin
:
Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. 29(2): 423-433 (2021) - [j278]Irith Pomeranz
:
Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1500-1504 (2021) - [c397]Irith Pomeranz:
Positive and Negative Extra Clocking of LFSR Seeds for Reduced Numbers of Stored Tests. ATS 2021: 109-114 - [c396]Irith Pomeranz:
Zoom-In Feature for Storage-Based Logic Built-In Self-Test. DFT 2021: 1-6 - [c395]Irith Pomeranz:
Compact Set of LFSR Seeds for Diagnostic Tests. VTS 2021: 1-7 - 2020
- [j277]Irith Pomeranz:
LFSR-based generation of boundary-functional broadside tests. IET Comput. Digit. Tech. 14(2): 61-68 (2020) - [j276]Irith Pomeranz
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Multicycle Broadside and Skewed-Load Tests for Test Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 262-266 (2020) - [j275]Irith Pomeranz
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Reverse Low-Power Broadside Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 742-746 (2020) - [j274]Irith Pomeranz
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Switching Activity of Faulty Circuits in Presence of Multiple Transition Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 936-945 (2020) - [j273]Irith Pomeranz
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Broadside Tests for Transition and Stuck-At Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(8): 1739-1743 (2020) - [j272]Irith Pomeranz
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Globally Functional Transparent-Scan Sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3012-3022 (2020) - [j271]Irith Pomeranz
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New Targets for Diagnostic Test Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3035-3043 (2020) - [j270]Irith Pomeranz
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Functional Broadside Tests Under Broadcast Scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3139-3143 (2020) - [j269]Irith Pomeranz
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Direct Computation of LFSR-Based Stored Tests for Broadside and Skewed-Load Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5238-5246 (2020) - [j268]Irith Pomeranz
, Srikanth Venkataraman:
LFSR-Based Test Generation for Reduced Fail Data Volume. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5261-5266 (2020) - [j267]Irith Pomeranz:
Target Faults for Test Compaction Based on Multicycle Tests. ACM Trans. Design Autom. Electr. Syst. 25(2): 18:1-18:14 (2020) - [j266]Irith Pomeranz
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Selection of Primary Output Vectors to Observe Under Multicycle Tests. IEEE Trans. Very Large Scale Integr. Syst. 28(1): 156-162 (2020) - [j265]Irith Pomeranz
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Extra Clocking of LFSR Seeds for Improved Path Delay Fault Coverage. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 544-552 (2020) - [j264]Irith Pomeranz
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RETRO: Reintroducing Tests for Improved Reverse Order Fault Simulation. IEEE Trans. Very Large Scale Integr. Syst. 28(8): 1930-1934 (2020) - [j263]Irith Pomeranz
:
Broad-Brush Compaction for Sequential Test Generation. IEEE Trans. Very Large Scale Integr. Syst. 28(8): 1940-1944 (2020) - [c394]Irith Pomeranz:
Improving a Test Set to Cover Test Holes by Detecting Gate-Exhaustive Faults. DFT 2020: 1-4 - [c393]Irith Pomeranz:
Storage Based Built-In Test Pattern Generation Method for Close-to-Functional Broadside Tests. IOLTS 2020: 1-4 - [c392]Irith Pomeranz, Sandip Kundu:
Reduced Fault Coverage as a Target for Design Scaffolding Security. IOLTS 2020: 1-6 - [c391]Irith Pomeranz:
Selecting Close-to-Functional Path Delay Faults for Test Generation. ITC 2020: 1-5 - [c390]Irith Pomeranz:
Input Test Data Volume Reduction Using Seed Complementation and Multiple LFSRs. VTS 2020: 1-6 - [c389]Irith Pomeranz:
Non-Masking Non-Robust Tests for Path Delay Faults. VTS 2020: 1-6
2010 – 2019
- 2019
- [j262]Irith Pomeranz:
Updating the sets of target faults during test generation for multiple fault models. IET Comput. Digit. Tech. 13(5): 369-375 (2019) - [j261]Irith Pomeranz
:
Diagnostic Test Generation That Addresses Diagnostic Holes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 335-344 (2019) - [j260]Irith Pomeranz
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LFSR-Based Test Generation for Path Delay Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 345-353 (2019) - [j259]Irith Pomeranz
:
Skewed-Load Tests for Transition and Stuck-at Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10): 1969-1973 (2019) - [j258]Irith Pomeranz
:
Invisible-Scan: A Design-for-Testability Approach for Functional Test Sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12): 2357-2365 (2019) - [j257]Irith Pomeranz:
Boundary-Functional Broadside and Skewed-Load Tests. ACM Trans. Design Autom. Electr. Syst. 24(1): 7:1-7:20 (2019) - [j256]Irith Pomeranz:
Incomplete Tests for Undetectable Faults to Improve Test Set Quality. ACM Trans. Design Autom. Electr. Syst. 24(2): 23:1-23:13 (2019) - [j255]Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman:
Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design. ACM Trans. Design Autom. Electr. Syst. 24(4): 42:1-42:19 (2019) - [j254]Irith Pomeranz
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Test Compaction by Test Removal Under Transparent Scan. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 496-500 (2019) - [j253]Irith Pomeranz
:
Extracting a Close-to-Minimum Multicycle Functional Broadside Test Set From a Functional Test Sequence. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1428-1437 (2019) - [j252]Irith Pomeranz
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Test Scores for Improving the Accuracy of Logic Diagnosis for Multiple Defects. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1720-1724 (2019) - [j251]Irith Pomeranz
:
Extended Transparent-Scan. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2096-2104 (2019) - [j250]Irith Pomeranz
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Padding of Multicycle Broadside and Skewed-Load Tests. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2587-2595 (2019) - [c388]Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz:
TEA: A Test Generation Algorithm for Designs with Timing Exceptions. ATS 2019: 19-24 - [c387]Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman:
Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines. DATE 2019: 1022-1027 - [c386]Irith Pomeranz:
Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults. ITC 2019: 1-7 - [c385]Irith Pomeranz:
Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation. ITC 2019: 1-7 - [c384]Irith Pomeranz:
Test Compaction Under Bounded Transparent-Scan. VTS 2019: 1-6 - [c383]Irith Pomeranz, Vivek Chickermane, Srikanth Venkataraman:
Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults. VTS 2019: 1-6 - 2018
- [j249]Irith Pomeranz:
On-chip generation of primary input sequences for multicycle functional broadside tests. IET Comput. Digit. Tech. 12(3): 80-86 (2018) - [j248]Irith Pomeranz:
Static test compaction procedure for large pools of multicycle functional broadside tests. IET Comput. Digit. Tech. 12(5): 233-240 (2018) - [j247]Irith Pomeranz
:
Improving the Diagnosability of Scan Chain Faults Under Transparent-Scan by Observation Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1278-1287 (2018) - [j246]Irith Pomeranz
:
An Initialization Process to Support Online Testing Based on Output Comparison for Identical Finite-State Machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1494-1504 (2018) - [j245]Irith Pomeranz
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Autonomous Multicycle Tests With Low Storage and Test Application Time Overheads. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1881-1892 (2018) - [j244]Irith Pomeranz:
Partially Invariant Patterns for LFSR-Based Generation of Close-to-Functional Broadside Tests. ACM Trans. Design Autom. Electr. Syst. 23(4): 53:1-53:18 (2018) - [j243]Irith Pomeranz:
Dynamically Determined Preferred Values and a Design-for-Testability Approach for Multiplexer Select Inputs under Functional Test Sequences. ACM Trans. Design Autom. Electr. Syst. 23(5): 59:1-59:16 (2018) - [j242]Irith Pomeranz
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Selecting Functional Test Sequences for Defect Diagnosis. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 2160-2164 (2018) - [j241]