"Transparent DFT: a design for testability and test generation approach for ..."

Irith Pomeranz, Sudhakar M. Reddy (2006)

> Home

Details and statistics

DOI: 10.1109/TCAD.2005.855947

access: closed

type: Journal Article

metadata version: 2020-09-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcad/PomeranzR06a
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcad/PomeranzR06a
Irith Pomeranz, Sudhakar M. Reddy:
Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1170-1175 (2006)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.