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2000 – 2009
- 2005
[c143]Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng:
Hardware Ef.cient LBISTWith Complementary Weights. ICCD 2005: 479-484- 2004
- [j40]Dong Xiang, Janak H. Patel:
Partial Scan Design Based on Circuit State Information and Functional Analysis. IEEE Trans. Computers 53(3): 276-287 (2004) - [c142]Ravishankar K. Iyer, William H. Sanders, Janak H. Patel, Zbigniew Kalbarczyk:
The evolution of dependable computing at the University of Illinois. IFIP Congress Topical Sessions 2004: 135-164 - [c141]Mihir A. Shah, Janak H. Patel:
Enhancement of the Illinois Scan Architecture for Use with Multiple Scan Inputs. ISVLSI 2004: 167-172 - [c140]Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng:
Logic BIST with Scan Chain Segmentation. ITC 2004: 57-66 - [c139]Manish Sharma, Janak H. Patel:
What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit? VTS 2004: 31-36 - [c138]Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel:
Logic BIST Using Constrained Scan Cells. VTS 2004: 199-205 - 2003
- [c137]Manish Sharma, Janak H. Patel, Jeff Rearick:
Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture. VTS 2003: 15-21 - [c136]Janak H. Patel, Steven S. Lumetta, Sudhakar M. Reddy:
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns. VTS 2003: 107-112 - 2002
- [c135]Amit R. Pandey, Janak H. Patel:
An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs. DATE 2002: 368-375 - [c134]Manish Sharma, Janak H. Patel:
Finding a Small Set of Longest Testable Paths that Cover Every Gate. ITC 2002: 974-982 - [c133]Amit R. Pandey, Janak H. Patel:
Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs . VTS 2002: 9-15 - 2001
- [j39]Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty:
Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. ACM Trans. Design Autom. Electr. Syst. 6(4): 471-489 (2001) - [c132]Frank F. Hsu, Kenneth M. Butler, Janak H. Patel:
A case study on the implementation of the Illinois Scan Architecture. ITC 2001: 538-547 - [c131]Manish Sharma, Janak H. Patel:
Testing of critical paths for delay faults. ITC 2001: 634-641 - [c130]Jian-Kun Zhao, Jeffrey A. Newquist, Janak H. Patel:
A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy Identification. VLSI Design 2001: 163- - 2000
- [j38]Ilker Hamzaoglu, Janak H. Patel:
Test set compaction algorithms for combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8): 957-963 (2000) - [j37]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Dynamic state traversal for sequential circuit test generation. ACM Trans. Design Autom. Electr. Syst. 5(3): 548-565 (2000) - [j36]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Peak power estimation of VLSI circuits: new peak power measures. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 435-439 (2000) - [c129]Ilker Hamzaoglu, Janak H. Patel:
Deterministic Test Pattern Generation Techniques for Sequential Circuits. ICCAD 2000: 538-543 - [c128]Manish Sharma, Janak H. Patel:
Enhanced delay defect coverage with path-segments. ITC 2000: 385-392 - [c127]Manish Sharma, Janak H. Patel:
Bounding Circuit Delay by Testing a Very Small Subset of Paths. VTS 2000: 333-342 - [c126]Ilker Hamzaoglu, Janak H. Patel:
Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators. VTS 2000: 369-376
1990 – 1999
- 1999
- [j35]Ilker Hamzaoglu, Janak H. Patel:
New Techniques for Deterministic Test Pattern Generation. J. Electron. Test. 15(1-2): 63-73 (1999) - [j34]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Fast Static Compaction Algorithms for Sequential Circuit Test Vectors. IEEE Trans. Computers 48(3): 311-322 (1999) - [j33]Elizabeth M. Rudnick, Janak H. Patel:
Efficient Techniques for Dynamic Test Sequence Compaction. IEEE Trans. Computers 48(3): 323-330 (1999) - [c125]Ilker Hamzaoglu, Janak H. Patel:
Reducing Test Application Time for Full Scan Embedded Cores. FTCS 1999: 260-267 - [c124]Zbigniew Kalbarczyk, Janak H. Patel, Myeong S. Lee, Ravishankar K. Iyer:
An Approach to Evaluating the Effects of Realistic Faults in Digital Circuits. VLSI Design 1999: 260-265 - [c123]Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal:
A Test Generator for Segment Delay Faults. VLSI Design 1999: 484-491 - 1998
- [j32]Frank F. Hsu, Janak H. Patel:
High-Level Controllability and Observability Analysis for Test Synthesis. J. Electron. Test. 13(2): 93-103 (1998) - [j31]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(3): 239-254 (1998) - [c122]Frank F. Hsu, Janak H. Patel:
High-level variable selection for partial-scan implementation. ICCAD 1998: 79-84 - [c121]Ilker Hamzaoglu, Janak H. Patel:
Test set compaction algorithms for combinational circuits. ICCAD 1998: 283-289 - [c120]Fulvio Corno, Janak H. Patel, Elizabeth M. Rudnick, Matteo Sonza Reorda
, Roberto Vietti:
Enhancing topological ATPG with high-level information and symbolic techniques. ICCD 1998: 504-509 - [c119]Janak H. Patel:
Retrospective: Improving the Throughput of a Pipeline by Insertion of Delays. 25 Years ISCA: Retrospectives and Reprints 1998: 5 - [c118]Janak H. Patel:
Retrospective: A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories. 25 Years ISCA: Retrospectives and Reprints 1998: 39-41 - [c117]Janak H. Patel, Edward S. Davidson:
Improving the Throughput of a Pipeline by Insertion of Delays. 25 Years ISCA: Retrospectives and Reprints 1998: 132-137 - [c116]Mark S. Papamarcos, Janak H. Patel:
A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories. 25 Years ISCA: Retrospectives and Reprints 1998: 284-290 - [c115]Ilker Hamzaoglu, Janak H. Patel:
Compact two-pattern test set generation for combinational and full scan circuits. ITC 1998: 944-953 - [c114]Janak H. Patel:
Stuck-at fault: a fault model for the next millennium. ITC 1998: 1166 - [c113]Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, Janak H. Patel:
Partial Scan Selection Based on Dynamic Reachability and Observability Information. VLSI Design 1998: 174-180 - [c112]Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel:
Diagnostic Simulation of Sequential Circuits Using Fault Sampling. VLSI Design 1998: 476-481 - [c111]Ilker Hamzaoglu, Janak H. Patel:
New Techniques for Deterministic Test Pattern Generation. VTS 1998: 446-452 - 1997
- [j30]Frank F. Hsu, Janak H. Patel:
Design for Testability Using State Distances. J. Electron. Test. 11(1): 93-100 (1997) - [j29]Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel:
Improving a nonenumerative method to estimate path delay fault coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7): 759-762 (1997) - [j28]Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann:
A genetic algorithm framework for test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(9): 1034-1044 (1997) - [j27]Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel:
Algorithms to compute bridging fault coverage of IDDQ test sets. ACM Trans. Design Autom. Electr. Syst. 2(3): 281-305 (1997) - [c110]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Sequential circuit test generation using dynamic state traversal. ED&TC 1997: 22-28 - [c109]Gurjeet S. Saund, Michael S. Hsiao, Janak H. Patel:
Partial Scan beyond Cycle Cutting. FTCS 1997: 320-328 - [c108]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Effects of delay models on peak power estimation of VLSI sequential circuits. ICCAD 1997: 45-51 - [c107]Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal:
Fast identification of untestable delay faults using implications. ICCAD 1997: 642-647 - [c106]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
K2: an estimator for peak sustainable power of VLSI circuits. ISLPED 1997: 178-183 - [c105]Elizabeth M. Rudnick, Janak H. Patel:
Putting the Squeeze on Test Sequences. ITC 1997: 723-732 - [c104]James P. Cusey, Janak H. Patel:
BART: A Bridging Fault Test Generation for Sequential Circuits. ITC 1997: 838-847 - [c103]Dilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, Janak H. Patel:
Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation. Workshop on Parallel and Distributed Simulation 1997: 30-37 - [c102]Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee:
Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. VLSI Design 1997: 475-481 - [c101]Elizabeth M. Rudnick, Janak H. Patel:
Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation. VLSI Design 1997: 495-503 - [c100]Charles R. Graham, Elizabeth M. Rudnick, Janak H. Patel:
Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits. VLSI Design 1997: 542-544 - [c99]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors. VTS 1997: 188-195 - [c98]Ismed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs:
Diagnostic Test Pattern Generation for Sequential Circuits. VTS 1997: 196-202 - [c97]Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee:
SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation. VTS 1997: 274-281 - [c96]Jian-Kun Zhao, Elizabeth M. Rudnick, Janak H. Patel:
Static logic implication with application to redundancy identification. VTS 1997: 288-295 - 1996
- [j26]Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi:
A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults. IEEE Trans. Computers 45(11): 1248-1256 (1996) - [j25]Jaushin Lee, Janak H. Patel:
Hierarchical test generation under architectural level functional constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9): 1144-1151 (1996) - [c95]Dong Xiang, Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel:
Partial Scan Design Based on Circuit State Information. DAC 1996: 807-812 - [c94]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Alternating Strategies for Sequential Circuit ATPG. ED&TC 1996: 368-374 - [c93]Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel:
On Double Transition Faults as a Delay Fault Model. Great Lakes Symposium on VLSI 1996: 282-287 - [c92]Elizabeth M. Rudnick, Janak H. Patel:
Simulation-based techniques for dynamic test sequence compaction. ICCAD 1996: 67-73 - [c91]Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel:
Enhancing high-level control-flow for improved testability. ICCAD 1996: 322-328 - [c90]Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal:
SIGMA: a simulator for segment delay faults. ICCAD 1996: 502-508 - [c89]Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel:
Testability Insertion in Behavioral Descriptions. ISSS 1996: 139-144 - [c88]Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz:
On Potential Fault Detection in Sequential Circuits. ITC 1996: 142-149 - [c87]Dong Xiang, Janak H. Patel:
A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information. ITC 1996: 548-557 - [c86]Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal:
Improving accuracy in path delay fault coverage estimation. VLSI Design 1996: 422-425 - [c85]Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal:
Segment delay faults: a new fault model. VTS 1996: 32-41 - [c84]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Automatic test generation using genetically-engineered distinguishing sequences. VTS 1996: 216-223 - [c83]Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel:
Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. VTS 1996: 456-462 - 1995
- [j24]Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel:
Sequential circuit testability enhancement using a nonscan approach. IEEE Trans. Very Large Scale Integr. Syst. 3(2): 333-338 (1995) - [c82]Eiji Harada, Janak H. Patel:
Overhead reduction techniques for hierarchical fault simulation. Asian Test Symposium 1995: 79-85 - [c81]Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel:
Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. DAC 1995: 133-138 - [c80]Elizabeth M. Rudnick, Janak H. Patel:
Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation. DAC 1995: 183-188 - [c79]Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel:
Fault Simulation ofIDDQ Tests for Bridging Faults in Sequential Circuits. FTCS 1995: 340-349 - [c78]Steven Parkes, Prithviraj Banerjee, Janak H. Patel:
A parallel algorithm for fault simulation based on PROOFS . ICCD 1995: 616-621 - [c77]Michael S. Hsiao, Janak H. Patel:
A new architectural-level fault simulation using propagation prediction of grouped fault-effects. ICCD 1995: 628-635 - [c76]Elizabeth M. Rudnick, Janak H. Patel:
A genetic approach to test application time reduction for full scan and partial scan circuits. VLSI Design 1995: 288-293 - [c75]Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel:
Cyclic stress tests for full scan circuits. VTS 1995: 89-94 - [c74]Frank F. Hsu, Janak H. Patel:
A distance reduction approach to design for testability. VTS 1995: 158-163 - 1994
- [j23]Vivek Chickermane, Jaushin Lee, Janak H. Patel:
Addressing design for testability at the architectural level. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(7): 920-934 (1994) - [j22]Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel:
An observability enhancement approach for improved testability and at-speed test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(8): 1051-1056 (1994) - [j21]Jaushin Lee, Janak H. Patel:
Architectural level test generation for microprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(10): 1288-1300 (1994) - [c73]Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther:
Microprocessor Testing: Which Technique is Best? (Panel). DAC 1994: 294 - [c72]Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann:
Sequential Circuit Test Generation in a Genetic Algorithm Framework. DAC 1994: 698-704 - [c71]Steven Parkes, Prithviraj Banerjee, Janak H. Patel:
ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation. DAC 1994: 717-721 - [c70]Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel:
Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. EDAC-ETC-EUROASIC 1994: 40-45 - [c69]John W. C. Fu, Janak H. Patel:
Trace Driven Simulation using Sampled Traces. HICSS (1) 1994: 211-220 - [c68]Abhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel:
Fast timing simulation of transient faults in digital circuits. ICCAD 1994: 719-722 - [c67]Hungse Cha, Janak H. Patel:
Latch Design for Transient Pulse Tolerance. ICCD 1994: 385-388 - [c66]Jeff Baxter, John W. C. Fu, Balkrishna Ramkumar, Janak H. Patel:
Hybrid Resource Management Algorithms for Multicomputer Systems. IPPS 1994: 482-489 - 1993
- [j20]Jaushin Lee, Janak H. Patel:
An architectural level test generator based on nonlinear equation solving. J. Electron. Test. 4(2): 137-150 (1993) - [j19]Alok N. Choudhary, Janak H. Patel, Narendra Ahuja:
NETRA: A Hierarchical and Partitionable Architecture for Computer Vision Systems. IEEE Trans. Parallel Distributed Syst. 4(10): 1092-1104 (1993) - [c65]Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel:
Non-Scan Design-for-Testability Techniques for Sequential Circuits. DAC 1993: 236-241 - [c64]Hungse Cha, Elizabeth M. Rudnick, Gwan S. Choi, Janak H. Patel, Ravishankar K. Iyer:
A Fast and Accurate Gate-Level Transient Fault Simulation Environment. FTCS 1993: 310-319 - [c63]Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel:
Theory and Practice of Sequential Machine Testing and Testability. FTCS 1993: 330-337 - [c62]Hungse Cha, Janak H. Patel:
A Logic-Level Model for alpha-Paricle Hits in CMOS Circuits. ICCD 1993: 538-542 - [c61]John W. C. Fu, Janak H. Patel:
Memory Reference Behavior of Compiler Optimized Programs on High Speed. ICPP (2) 1993: 87-94 - [c60]Pi-Yu Chung, Ibrahim N. Hajj, Janak H. Patel:
Efficient Variable Ordering Heuristics for Shared ROBDD. ISCAS 1993: 1690-1693 - [c59]Jeff Rearick, Janak H. Patel:
Fast and Accurate CMOS Bridging Fault Simulation. ITC 1993: 54-62 - [c58]Jaushin Lee, Janak H. Patel:
Testability analysis based on structural and behavioral information. VTS 1993: 139-146 - [c57]Jaushin Lee, Vivek Chickermane, Janak H. Patel:
Impact of high level functional constraints on testability. VTS 1993: 309-312 - 1992
- [j18]Pinaki Mazumder, Janak H. Patel:
An efficient design of embedded memories and their testability analysis using Markov chains. J. Electron. Test. 3(3): 235-250 (1992) - [j17]Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel:
PROOFS: a fast, memory-efficient sequential circuit fault simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(2): 198-207 (1992) - [j16]Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham:
Test compaction for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(2): 260-267 (1992) - [c56]Sungho Kim, Prithviraj Banerjee, Vivek Chickermane, Janak H. Patel:
APT: An Area-Performance-Testability Driven Placement Algorithm. DAC 1992: 141-146 - [c55]Jaushin Lee, Janak H. Patel:
Hierarchical Test Generation under Intensive Global Functional Constraints. DAC 1992: 261-266 - [c54]Rabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu:
Automatic test generation for linear digital systems with bi-level search using matrix transform methods. ICCAD 1992: 224-228 - [c53]Gary S. Greenstein, Janak H. Patel:
E-PROOFS: a CMOS bridging fault simulator. ICCAD 1992: 268-271 - [c52]Vivek Chickermane, Jaushin Lee, Janak H. Patel:
A comparative study of design for testability methods using high-level and gate-level descriptions. ICCAD 1992: 620-624 - [c51]