29th DAC 1992: Anaheim, California, USA

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Electrical Analysis

Test Generation

Two Level Logic Synthesis

Tutorial

Partitioning and Floorplanning

Interconnect Simulation

Scheduling and Allocation

Panel

Concurrent Engineering

New Approaches to Placement

Deley-Fault Testing

Synthesis Systems and Representations

Panel

Asymptotic Waveform Evaluation

System-Level Synthesis

Performance Issues in Logic Synthesis

Panel

High-Level Test Generation

Allocation and Binding

Panel

Tutorial

Design Verification and Compaction

Fault Simulation and Fault Diagnosis

FPGA Synthesis

Tutorial

Timing Optimization and Verification

Discrete Simulation

Multi-Level Logic Synthesis

Panel

DA for High-Speed Packaging

Technology Mapping in Logic Synthesis

Panel

Frameworks

Global Issues in Routing

Path Delay Analysis

Sequential Logic Synthesis

Panel

Multi-Layer Channel and Over-the-Cell Routing

Automated Approaches to Formal Verification of Hardware

Advances in High-Level Synthesis

Tutorial - EDIF/CFI - A User's Perspective

Routing for Special Applications

Issues in Analog CAD