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ORCIDDATE 2011: Grenoble, France
- Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011. IEEE 2011, ISBN 978-1-61284-208-0
Keynote
- Stephen B. Furber:
Biologically-inspired massively-parallel architectures - Computing beyond a million processors. 1
System-Level Techniques to Handle Performance, Reliability and Thermal Issues
- Vivek Joy Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey:
VESPA: Variability emulation for System-on-Chip performance analysis. 2-7 - Chiao-Ling Lung, Yi-Lun Ho, Ding-Ming Kwai, Shih-Chieh Chang:
Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization. 8-13 - Yi Wang, Duo Liu, Zhiwei Qin, Zili Shao:
An endurance-enhanced Flash Translation Layer via reuse for NAND flash memory storage systems. 14-19 - Tiantian Liu, Alex Orailoglu, Chun Jason Xue, Minming Li:
Register allocation for simultaneous reduction of energy and peak temperature on registers. 20-25
Modeling and Simulation of Interconnects
- Luca Gobbato, Alessandro Chinea, Stefano Grivet-Talocia:
A parallel Hamiltonian eigensolver for passivity characterization and enforcement of large interconnect macromodels. 26-31 - Yu Bi, Kees-Jan van der Kolk, Jorge Fernandez Villena, Luís Miguel Silveira
, Nick van der Meijs:
Fast statistical analysis of RC nets subject to manufacturing variabilities. 31-37 - Baktash Boghrati, Sachin S. Sapatnekar:
A scaled random walk solver for fast power grid analysis. 38-43 - Zheng Zhang, Xiang Hu, Chung-Kuan Cheng, Ngai Wong:
A block-diagonal structured model reduction scheme for power grid networks. 44-49
Logic Synthesis and Place and Route: After 20 Years of Engagement, Wedding in View? (Panel/Tutorial)
- Giovanni De Micheli:
Logic synthesis and physical design: Quo vadis? 50 - Marco Casale-Rossi, Antun Domic:
Panel and embedded tutorial - Logic synthesis and place and route: After 20 years of engagement, wedding in view? 51
Transient Faults and Soft Errors
- David J. Palframan, Nam Sung Kim, Mikko H. Lipasti:
Time redundant parity for low-cost transient error detection. 52-57 - Keheng Huang, Yu Hu, Xiaowei Li:
Cross-layer optimized placement and routing for FPGA soft error mitigation. 58-63 - Chien-Chih Yu, John P. Hayes:
Trigonometric method to handle realistic error probabilities in logic circuits. 64-69 - Mahdi Fazeli, Seyed Nematollah Ahmadian, Seyed Ghassem Miremadi, Hossein Asadi, Mehdi Baradaran Tahoori:
Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs). 70-75
Networked Embedded Systems
- Martin Lukasiewycz, Samarjit Chakraborty, Paul Milbredt:
FlexRay switch scheduling - A networking concept for electric vehicles. 76-81 - Kay Klobedanz, Andreas König, Wolfgang Müller:
A reconfiguration approach for fault-tolerant FlexRay networks. 82-87 - Lan S. Bai, Robert P. Dick, Peter A. Dinda, Pai H. Chou:
Simplified programming of faulty sensor networks via code transformation and run-time interval computation. 88-93
Design of Energy-Efficient and Automotive Systems
- Nafsika Chrysanthou, Grigorios Chrysos, Euripides Sotiriades, Ioannis Papaefstathiou:
Parallel accelerators for GlimmerHMM bioinformatics algorithm. 94-99 - Francesco Paterna, Andrea Acquaviva, Alberto Caprara, Francesco Papariello, Giuseppe Desoli, Luca Benini:
An efficient on-line task allocation algorithm for QoS and energy efficiency in multicore multimedia platforms. 100-105 - Jatin N. Mistry, Bashir M. Al-Hashimi, David Flynn, Stephen Hill:
Sub-clock power-gating technique for minimising leakage power during active mode. 106-111 - Andreas Kern, Thilo Streichert, Jürgen Teich:
An automated data structure migration concept - From CAN to Ethernet/IP in automotive embedded systems (CANoverIP). 112-117 - Sebastian Siegl, Kai-Steffen Hielscher, Reinhard German, Christian Berger:
Formal specification and systematic model-driven testing of embedded automotive systems. 118-123
Embedded Tutorial
- Bhanu Kapoor, Knut M. Just:
Embedded tutorial: Addressing critical power management verification issues in low power designs. 124
Power Optimization of Multi-Core Architectures
- Koushik Chakraborty, Sanghamitra Roy:
Topologically homogeneous power-performance heterogeneous multicore systems. 125-130 - Lucas Francisco Wanner, Rahul Balani, Sadaf Zahedi, Charwak Apte, Puneet Gupta, Mani B. Srivastava:
Variability-aware duty cycle scheduling in long running embedded sensing systems. 131-136 - Vinay Hanumaiah, Sarma B. K. Vrudhula:
Reliability-aware thermal management for hard real-time applications on multi-core processors. 137-142
Core Algorithms for Formal Verification Engines
- HyoJung Han, HoonSang Jin, Fabio Somenzi:
Clause simplification through dominator analysis. 143-148 - Sven Reimer, Florian Pigorsch, Christoph Scholl, Bernd Becker:
Integration of orthogonal QBF solving techniques. 149-154 - Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Alexander Dreyer, Frank Seelisch, Gert-Martin Greuel:
STABLE: A new QF-BV SMT solver for hard verification problems combining Boolean reasoning with computer algebra. 155-160
Predicting Bugs and Generating Tests for Validation
- Qi Guo, Tianshi Chen, Haihua Shen, Yunji Chen, Yue Wu, Weiwu Hu:
Empirical design bugs prediction for verification. 161-166 - Mingsong Chen, Prabhat Mishra:
Decision ordering based property decomposition for functional test generation. 167-172 - Lingyi Liu, David Sheridan, William Tuohy, Shobha Vasudevan:
Towards coverage closure: Using GoldMine assertions for generating design validation stimulus. 173-178 - Jörg Behrend, Djones Lettnin, Patrick Heckeler, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel:
Scalable hybrid verification for embedded software. 179-184
Timing Related Issues in Test
- Mingjing Chen, Alex Orailoglu:
Diagnosing scan chain timing faults through statistical feature analysis of scan images. 185-190 - Mainak Banga, Nikhil P. Rahagude, Michael S. Hsiao:
Design-for-test methodology for non-scan at-speed testing. 191-196 - Bo Yang, Amit Sanghani, Shantanu Sarangi, Chunsheng Liu:
A clock-gating based capture power droop reduction methodology for at-speed scan testing. 197-203
Performance and Timing Analysis
- Sidharta Andalam, Partha S. Roop, Alain Girault:
Pruning infeasible paths for tight WCRT analysis of synchronous programs. 204-209 - Stefan Stattelmann, Oliver Bringmann, Wolfgang Rosenstiel:
Fast and accurate resource conflict simulation for performance analysis of multi-core systems. 210-215 - Zhonglei Wang, Kun Lu, Andreas Herkersdorf:
An approach to improve accuracy of source-level TLMs of embedded software. 216-221 - Parisa Razaghi, Andreas Gerstlauer:
Host-compiled multicore RTOS simulator for embedded real-time software development. 222-227
Implementations for Digital Baseband Processing
- Purushotham Murugappa, Rachid Al-Khayat, Amer Baghdadi, Michel Jézéquel:
A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding. 228-233 - Christian Bernard, Fabien Clermidy:
A low-power VLIW processor for 3GPP-LTE complex numbers processing. 234-239 - Nils Heidmann, Till Wiegand, Steffen Paul:
Architecture and FPGA-implementation of a high throughput K+-Best detector. 240-245 - Nariman Moezzi Madani, Thorlindur Thorolfsson, Joseph Crop, Patrick Chiang, W. Rhett Davis:
An energy-efficient 64-QAM MIMO detector for emerging wireless standards. 246-251
Panel
- Barry M. Pangrle, John Biggs, Cristophe Clavel, Olivier Domerego, Knut M. Just:
Beyond UPF & CPF: Low-power design and verification. 252
Interactive Presentations
- Mohammed G. Khatib, Leon Abelmann:
Buffering implications for the design space of streaming MEMS storage. 253-256 - Ankit Goyal, Farid N. Najm:
Efficient RC power grid verification using node elimination. 257-260 - Michael B. Healy, Sung Kyu Lim:
A novel TSV topology for many-tier 3D power-delivery networks. 261-264 - Nor Zaidi Haron, Said Hamdioui:
Cost-efficient fault-tolerant decoder for hybrid nanoelectronic memories. 265-268 - Tobias Ziermann, Jürgen Teich, Zoran Salcic:
DynOAA - Dynamic offset adaptation algorithm for improving response times of CAN systems. 269-272 - Simone Sabatelli, Francesco Sechi, Luca Fanucci, Alessandro Rocchi:
A sensor fusion algorithm for an integrated angular position estimation with inertial measurement units. 273-276 - Luc Michel, Nicolas Fournel, Frédéric Pétrot:
Speeding-up SIMD instructions dynamic binary translation in embedded processor simulation. 277-280 - Linwei Niu:
System-level energy-efficient scheduling for hard real-time embedded systems. 281-284 - Rami A. Abdallah, Yu-Hung Lee, Naresh R. Shanbhag:
Timing error statistics for energy-efficient robust DSP systems. 285-288 - Mojtaba Ebrahimi, Seyed Ghassem Miremadi, Hossein Asadi:
ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications. 298-292
Robust and Low Power Systems
- T. Kolpe, Antonia Zhai, Sachin S. Sapatnekar:
Enabling improved power management in multicore processors through clustered DVFS. 293-298 - Fazal Hameed, Mohammad Abdullah Al Faruque, Jörg Henkel:
Dynamic thermal management in 3D multi-core architecture through run-time adaptation. 299-304 - Ilya Wagner, Shih-Lien Lu:
Distributed hardware matcher framework for SoC survivability. 305-310 - Songjun Pan, Yu Hu, Xing Hu, Xiaowei Li:
A cost-effective substantial-impact-filter based method to tolerate voltage emergencies. 311-315
Formal Verification Techniques and Applications
- Gianpiero Cabodi, Sergio Nocco, Stefano Quer:
Interpolation sequences revisited. 316-322 - Brian Keng, Sean Safarpour, Andreas G. Veneris:
Automated debugging of SystemVerilog assertions. 323-328 - Bryan A. Brady, Daniel E. Holcomb, Sanjit A. Seshia:
Counterexample-guided SMT-driven optimal buffer sizing. 329-334
System Level Simulation and Validation
- Peng-Chih Wang, Meng-Huan Wu, Ren-Song Tsay:
DOM: A Data-dependency-Oriented Modeling approach for efficient simulation of OS preemptive scheduling. 335-340 - Chen Kang Lo, Li-Chun Chen, Meng-Huan Wu, Ren-Song Tsay:
Cycle-count-accurate processor modeling for fast and accurate system-level simulation. 341-346 - Cheng-Yang Fu, Meng-Huan Wu, Ren-Song Tsay:
A shared-variable-based synchronization approach to efficient cache coherence simulation for multi-core systems. 347-352 - Yu-Fu Yeh, Chung-Yang Huang, Chi-An Wu, Hsin-Cheng Lin:
Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method. 353-358
Advances in Analogue, Mixed Signal and RF Testing
- Ping-Ying Wang, Hsiu-Ming Chang, Kwang-Ting Cheng:
An all-digital built-in self-test technique for transfer function characterization of RF PLLs. 359-364 - Pedro Fonseca da Mota, José Machado da Silva:
A true power detector for RF PA built-in calibration and testing. 365-370 - Hamidreza Hashempour, Jos Dohmen, Bratislav Tasic, Bram Kruseman, Camelia Hora, Maikel van Beurden, Yizi Xing:
Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example. 371-376 - Mohit Singh, Mahendra Sakare, Shalabh Gupta:
Testing of high-speed DACs using PRBS generation with "Alternate-Bit-Tapping". 377-382
Design Automation Methodologies and Architectures for Three-Dimensional ICs
- Da-Cheng Juan, Siddharth Garg, Diana Marculescu:
Statistical thermal evaluation and mitigation techniques for 3D Chip-Multiprocessors in the presence of process variations. 383-388 - Christian Weis, Norbert Wehn, Igor Loi, Luca Benini:
Design space exploration for 3D-stacked DRAMs. 389-394 - Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli:
Analytical heat transfer model for thermal through-silicon vias. 395-400 - Hsien-Te Chen, Hong-Long Lin, Zi-Cheng Wang, TingTing Hwang:
A new architecture for power network in 3D IC. 401-406
Resource Management for QoS Guaranteed NoCs
- Everton Carara, Gabriel Marchesan Almeida, Gilles Sassatelli, Fernando Gehm Moraes:
Achieving composability in NoC-based MPSoCs through QoS management at software level. 407-412 - Marjan Asadinia, Mehdi Modarressi, Arash Tavakkol, Hamid Sarbazi-Azad:
Supporting non-contiguous processor allocation in mesh-based CMPs using virtual point-to-point links. 413-418 - Markus Winter, Gerhard P. Fettweis:
Guaranteed service virtual channel allocation in NoCs for run-time task scheduling. 419-424 - Ashkan Beyranvand Nejad, Matias Escudero Martinez, Kees Goossens:
An FPGA bridge preserving traffic quality of service for on-chip network-based systems. 425-430
Smart Devices Embedded Tutorial - Smart Devices for the Cloud Era
- Gerhard P. Fettweis, Falko Guderian, Stefan Krone:
Entering the path towards terabit/s wireless links. 431-436 - Antoine Dupret, Michaël Tchagaspanian, Arnaud Verdant, Laurent Alacoque, Arnaud Peizerat:
Smart imagers of the future. 437-442
An Encyclopedia of Routing
- Tai-Hsuan Wu, Azadeh Davoodi, Jeff T. Linderoth:
Power-driven global routing for multi-supply voltage domains. 443-448 - Jin-Tai Yan, Zhi-Wei Chen:
Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance. 449-454 - Jianchao Lu, Vinayak Honkote, Xin Chen, Baris Taskin:
Steiner tree based rotary clock routing with bounded skew and capacitive load balancing. 455-460 - Tsung-Ying Tsai, Ren-Jie Lee, Ching-Yu Chin, Chung-Yi Kuan, Hung-Ming Chen, Yoji Kajitani:
On routing fixed escaped boundary pins for high speed boards. 461-466
Temperature and Variation Aware Design in Low Power Systems
- Satyanand Nalam, Vikas Chandra, Robert C. Aitken, Benton H. Calhoun:
Dynamic write limited minimum operating voltage for nanoscale SRAMs. 467-472 - Mohammad Ghasemazar, Massoud Pedram:
Variation aware dynamic power management for chip multiprocessor architectures. 473-478 - Huang Huang, Gang Quan:
Leakage aware energy minimization for real-time systems under the maximum temperature constraint. 479-484
Advanced NoC Tooling and Architectures
- Anita Tino, Gul N. Khan:
Multi-objective Tabu Search based topology generation technique for application-specific Network-on-Chip architectures. 485-490 - Abbas Rahimi, Igor Loi, Mohammad Reza Kakoee, Luca Benini:
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters. 491-496 - Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alexandre Yakovlev, Maurizio Palesi:
Run-time deadlock detection in networks-on-chip using coupled transitive closure networks. 497-502
Industrial 1
- Akitoshi Matsuda, Tohru Ishihara:
Developing an integrated verification and debug methodology. 503-504 - Geert Eneman, J. Cho, V. Moroz, Dragomir Milojevic, M. Choi, Kristin De Meyer, Abdelkarim Mercha, Eric Beyne, Thomas Hoffmann, Geert Van der Plas:
An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations. 505-506 - Bhanu Kapoor, Alan Hunter, Prapanna Tiwari:
Power management verification experiences in Wireless SoCs. 507-508 - Tsunwai Gary Yip, Philip Yeung, Ming Li, Deborah Dressler:
Challenges in designing high speed memory subsystem for mobile applications. 509-510 - Massimo Mazzillo, Pier Giorgio Fallica, Elisa Ficarra, A. Messina, Mario Francesco Romeo, Roberto Zafalon:
Solid state photodetectors for nuclear medical imaging applications. 511-512 - Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Oscar Ballan:
Fault grading of software-based self-test procedures for dependable automotive applications. 513-514
Analysis, Compilation and Runtime Techniques
- Janmartin Jahn, Mohammad Abdullah Al Faruque, Jörg Henkel:
CARAT: Context-aware runtime adaptive task migration for multi core architectures. 515-520 - Joachim Falk, Christian Zebelein, Christian Haubelt, Jürgen Teich:
A rule-based static dataflow clustering algorithm for efficient embedded software synthesis. 521-526 - José Baiocchi, Bruce R. Childers:
Demand code paging for NAND flash in MMU-less embedded systems. 517-532
Embedded Tutorial
- Dimitris Gizopoulos, Mihalis Psarakis, Sarita V. Adve, Pradeep Ramachandran, Siva Kumar Sastry Hari, Daniel J. Sorin, Albert Meixner, Arijit Biswas, Xavier Vera:
Architectures for online error detection and recovery in multicore processors. 533-538
Interactive Presentations
- Jishen Zhao, Xiangyu Dong, Yuan Xie:
An energy-efficient 3D CMP design with fine-grained voltage scaling. 539-542 - Gianpiero Cabodi, Sergio Nocco:
Optimized model checking of multiple properties. 543-546 - Dusung Kim, Maciej J. Ciesielski, Seiyang Yang:
A new distributed event-driven gate-level HDL simulation by accurate prediction. 547-550 - Lakshmanan Balasubramanian, Puneet Sabbarwal, Rajesh Kumar Mittal, Prakash Narayanan, Ranjit Kumar Dash, Anand Devendra Kudari, Srikanth Manian, Sudhir Polarouthu, Harikrishna Parthasarathy, Ravi C. Vijayaraghavan, Sachin Turkewadikar:
Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management system. 551-554 - Walid Lafi, Didier Lattard, Ahmed Amine Jerraya:
A 3D reconfigurable platform for 4G telecom applications. 555-558 - Susumu Kobayashi, Kenichi Horiuchi:
An LOCV-based static timing analysis considering spatial correlations of power supply variations. 559-562 - Claus Traulsen, T. Amende, Reinhard von Hanxleden:
Compiling SyncCharts to Synchronous C. 563-566 - Xiaotao Chang, Yike Ma, Hubertus Franke, Kun Wang, Rui Hou, Hao Yu, Terry Nelms:
Optimization of stateful hardware acceleration in hybrid architectures. 567-570 - Chih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, Sy-Yen Kuo:
Formal reset recovery slack calculation at the register transfer level. 571-574 - Alain Fourmigue, Giovanni Beltrame, Gabriela Nicolescu, El Mostapha Aboulhamid, Ian O'Connor:
Multi-granularity thermal evaluation of 3D MPSoC architectures. 575-578 - David C. Keezer, Carl Edward Gray:
Two methods for 24 Gbps test signal synthesis. 579-582 - Yi-Chung Chen, Hai Li, Yiran Chen, Robinson E. Pino:
3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers. 583-586 - Chia-I Chen, Bau-Cheng Lee, Juinn-Dar Huang:
Architectural exploration of 3D FPGAs towards a better balance between area and delay. 587-590 - Joël Porquet, Alain Greiner, Christian Schwarz:
NoC-MPU: A secure architecture for flexible co-hosting on shared memory MPSoCs. 591-594