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ORCIDDATE 2017: Lausanne, Switzerland
- David Atienza, Giorgio Di Natale:
Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017. IEEE 2017, ISBN 978-3-9815370-8-6
- Florian Neugebauer, Ilia Polian, John P. Hayes:
Framework for quantifying and managing accuracy in stochastic circuit design. 1-6 - Issa Qiqieh
, Rishad A. Shafik, Ghaith Tarawneh, Danil Sokolov, Alex Yakovlev:
Energy-efficient approximate multiplier design using bit significance-driven logic compression. 7-12 - Vincent T. Lee, Armin Alaghi, John P. Hayes, Visvesh Sathe, Luis Ceze:
Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing. 13-18 - Lerong Chen, Jiawen Li, Yiran Chen, Qiuping Deng, Jiyuan Shen, Xiaoyao Liang, Li Jiang:
Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar. 19-24 - Guan Wang, Xiaojun Cai, Lei Ju, Chuanqi Zang, Mengying Zhao, Zhiping Jia:
Shared last-level cache management for GPGPUs with hybrid main memory. 25-30 - Mohammad Sadrosadati, Amirhossein Mirhosseini, Shahin Roozkhosh, Hazhir Bakhishi, Hamid Sarbazi-Azad:
Effective cache bank placement for GPUs. 31-36 - Arun Subramaniyan, Semeen Rehman, Muhammad Shafique, Akash Kumar, Jörg Henkel:
Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-cores. 37-42 - Kishore Punniyamurthy, Behzad Boroujerdian, Andreas Gerstlauer:
GATSim: Abstract timing simulation of GPUs. 43-48 - Sandeep Poddar, Rik Jongerius, Leandro Fiorin, Giovanni Mariani, Gero Dittmann, Andreea Anghel, Henk Corporaal:
MeSAP: A fast analytic power model for DRAM memories. 49-54 - Kecheng Ji, Ming Ling, Qin Wang, Longxing Shi, Jianping Pan:
AFEC: An analytical framework for evaluating cache performance in out-of-order processors. 55-60 - Sadia Moriam, Gerhard P. Fettweis:
Reliability assessment of fault tolerant routing algorithms in networks-on-chip: An analytic approach. 61-66 - Zana Ghaderi, Ayed Alqahtani, Nader Bagherzadeh:
Online monitoring and adaptive routing for aging mitigation in NoCs. 67-72 - Siddhartha, Nachiket Kapre:
eBSP: Managing NoC traffic for BSP workloads on the 16-core Adapteva Epiphany-III processor. 73-78 - Manuel J. Barragan, Gildas Léger, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda:
On the limits of machine learning-based test: A calibrated mixed-signal system case study. 79-84 - Sebastien Cliquennois:
An extension of Cohn's sensitivity theorem to mismatch analysis of 1-port resistor networks. 85-90 - Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann:
Testing microfluidic Fully Programmable Valve Arrays (FPVAs). 91-96 - Nikolaos Zompakis, Michail Noltsis, Lorena Ndreu, Zacharias Hadjilambrou, Panayiotis Englezakis, Panagiota Nikolaou, Antoni Portero, Simone Libutti, Giuseppe Massari, Federico Sassi, Alessandro Bacchini, Chrysostomos Nicopoulos, Yiannakis Sazeides, Radim Vavrík, Martin Golasowski, Jiri Sevcík, Vít Vondrák, Francky Catthoor, William Fornaciari, Dimitrios Soudris:
HARPA: Tackling physically induced performance variability. 97-102 - Fabrice Cros, Leonidas Kosmidis, Franck Wartel, David Morales, Jaume Abella, Ian Broster, Francisco J. Cazorla:
Dynamic software randomisation: Lessons learnec from an aerospace case study. 103-108 - Per Gunnar Kjeldsberg, Andreas Gocht, Michael Gerndt, Lubomir Riha, Joseph Schuchart, Umbreen Sabir Mian:
READEX: Linking two ends of the computing continuum to improve energy-efficiency in dynamic applications. 109-114 - Artur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans G. Kerkhoff, Rene Krenz-Baath, Piet Engelke:
BASTION: Board and SoC test instrumentation for ageing and no failure found. 115-120 - Gina Alioto, Paul M. Carpenter, Adrián Cristal, Osman S. Unsal, Marcus Leich, Christophe Avare:
RETHINK big: European roadmap for hardware anc networking optimizations for big data. 121-126 - Massimo Alioto:
Energy-quality scalable adaptive VLSI circuits and systems beyond approximate computing. 127-132 - Chenyun Pan, Azad Naeemi:
Beyond-CMOS non-Boolean logic benchmarking: Insights and future directions. 133-138 - Hsin-Pai Cheng, Wei Wen, Chunpeng Wu, Sicheng Li, Hai Helen Li, Yiran Chen:
Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspective. 139-144 - András Horváth, Michael Hillmer, Qiuwen Lou, Xiaobo Sharon Hu, Michael T. Niemier:
Cellular neural network friendly convolutional neural networks - CNNs with CNNs. 145-150 - Pei Luo, Konstantinos Athanasiou, Yunsi Fei, Thomas Wahl:
Algebraic fault analysis of SHA-3. 151-156 - Minsu Kim, Sunhee Kong, Boeui Hong, Lei Xu, Weidong Shi, Taeweon Suh:
Evaluating coherence-exploiting hardware Trojan. 157-162 - Fatma Nur Esirci, Alp Arslan Bayrakci:
Hardware Trojan detection based on correlated path delays in defiance of variations with spatial correlations. 163-168 - Zhixing Xu, Sayak Ray, Pramod Subramanyan, Sharad Malik:
Malware detection using machine learning based analysis of virtual memory access patterns. 169-174 - Hussam Amrouch, Behnam Khaleghi, Jörg Henkel:
Optimizing temperature guardbands. 175-180 - Benjamin Barrois, Olivier Sentieys, Daniel Ménard:
The hidden cost of functional approximation against careful data sizing - A case study. 181-186 - Seogoo Lee, Lizy K. John, Andreas Gerstlauer:
High-level synthesis of approximate hardware under joint precision and voltage scaling. 187-192 - Sanchari Sen, Swagath Venkataramani, Anand Raghunathan:
Approximate computing for spiking neural networks. 193-198 - Jong Hwan Ko, Duckhwan Kim, Taesik Na, Jaeha Kung, Saibal Mukhopadhyay:
Adaptive weight compression for memory-efficient neural networks. 199-204 - Qiuwen Chen, Qinru Qiu:
Real-time anomaly detection for streaming data using burst code on a neurosynaptic processor. 205-207 - Parami Wijesinghe, Chamika M. Liyanagedera, Kaushik Roy:
Fast, low power evaluation of elementary functions using radial basis function networks. 208-213 - Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas:
Charka: A reliability-aware test scheme for diagnosis of channel shorts beyond mesh NoCs. 214-219 - Shengcheng Wang, Hengyang Zhao, Sheldon X.-D. Tan, Mehdi Baradaran Tahoori:
Recovery-aware proactive TSV repair for electromigration in 3D ICs. 220-225 - Johannes Bund, Christoph Lenzen, Moti Medina:
Near-optimal metastability-containing sorting networks. 226-231 - Yecheng Zhao, Haibo Zeng:
The concept of unschedulability core for optimizing priority assignment in real-time systems. 232-237 - Saravanan Ramanathan, Arvind Easwaran:
Utilization difference based partitioned scheduling of mixed-criticality systems. 238-243 - Leo Hatvani, Reinder J. Bril, Sebastian Altmeyer:
Schedulability using native non-preemptive groups on an AUTOSAR/OSEK platform with caches. 244-249 - Zhe Li, Ao Ren, Ji Li, Qinru Qiu, Bo Yuan, Jeffrey Draper, Yanzhi Wang:
Structural design optimization for deep convolutional neural networks using stochastic computing. 250-253 - Ting Wang, Qian Zhang, Qiang Xu:
ApproxQA: A unified quality assurance framework for approximate computing. 254-257 - Vojtech Mrazek, Radek Hrbacek, Zdenek Vasícek, Lukás Sekanina:
EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. 258-261 - Radha Krishna Aluru, Swaroop Ghosh:
Droop mitigating last level cache architecture for STTRAM. 262-265 - Omayma Matoussi, Frédéric Pétrot:
Modeling instruction cache and instruction buffer for performance estimation of VLIW architectures using native simulation. 266-269 - Enrico Fraccaroli, Franco Fummi:
Analog fault testing through abstraction. 270-273 - Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee:
BISCC: Efficient pre through post silicon validation of mixed-signal/RF systems using built in state consistency checking. 274-277 - Mustafa Altun, Valentina Ciriani, Mehdi Baradaran Tahoori:
Computing with nano-crossbar arrays: Logic synthesis and fault tolerance. 278-281 - Florian Kelbert, Franz Gregor, Rafael Pires, Stefan Köpsell, Marcelo Pasin, Aurelien Havet, Valerio Schiavoni, Pascal Felber, Christof Fetzer, Peter R. Pietzuch:
SecureCloud: Secure big data processing in untrusted clouds. 282-285 - Steven Derrien, Isabelle Puaut, Panayiotis Alefragis, Marcus Bednara, Harald Bucher, Clément David, Yann Debray, Umut Durak, Imen Fassi, Christian Ferdinand, Damien Hardy, Angeliki Kritikakou, Gerard K. Rauwerda, Simon Reder, Martin Sicks, Timo Stripf, Kim Sunesen, Timon D. ter Braak, Nikolaos S. Voros, Jürgen Becker:
WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach. 286-289 - Martin Andraud, Gönenç Berkol, Jaro De Roose, Santosh Gannavarapu, Haoming Xin, Eugenio Cantatore, Pieter J. A. Harpe, Marian Verhelst, Peter G. M. Baltus:
Exploring the unknown through successive generations of low power and low resource versatile agents. 290-293 - Faiq Khalid Lodhi, Syed Rafay Hasan, Osman Hasan, Falah R. Awwad:
Power profiling of microcontroller's instruction set for runtime hardware Trojans detection without golden circuit models. 294-297 - Martin Bruestel, Akash Kumar:
Accounting for systematic errors in approximate computing. 298-301 - Amin Ghasemazar, Mieszko Lis:
Gaussian mixture error estimation for approximate circuits. 302-305 - Kai Neubauer, Philipp Wanko, Torsten Schaub, Christian Haubelt:
Enhancing symbolic system synthesis through ASPmT with partial assignment evaluation. 306-309 - Javad Bagherzadeh, Valeria Bertacco:
3DFAR: A three-dimensional fabric for reliable multi-core processors. 310-313 - Mostafa Kishani, Reza Eftekhari, Hossein Asadi:
Evaluating impact of human errors on the availability of data storage systems. 314-317 - Björn Forsberg, Andrea Marongiu, Luca Benini:
GPUguard: Towards supporting a predictable execution model for heterogeneous SoC. 318-321 - Lin Li, Philipp Wagner, Albrecht Mayer, Thomas Wild, Andreas Herkersdorf:
A non-intrusive, operating system independent spinlock profiler for embedded multicore systems. 322-325 - Meisam Bahadori, Sébastien Rumley, Robert P. Polster, Alexander Gazman, Matt Traverso, Mark Webster, Kaushik Patel, Keren Bergman:
Energy-performance optimized design of silicon photonic interconnection networks for high-performance computing. 326-331 - Kaushik Patel:
Rapid growth of IP traffic is driving adoption of silicon photonics in data centers. 332-335 - Christian Reimer, Michael Kues, Piotr Roztocki, Benjamin Wetzel, Brent E. Little, Sai T. Chu, Lucia Caspani, David J. Moss, Roberto Morandotti:
Generation of complex quantum states via integrated frequency combs. 336-337 - Michael Raitza, Akash Kumar, Marcus Völp, Dennis Walter, Jens Trommer, Thomas Mikolajick, Walter M. Weber:
Exploiting transistor-level reconfiguration to optimize combinational circuits. 338-343 - Tushar Krishna, Arya Balachandran, Siau Ben Chiah, Li Zhang, Bing Wang, Cong Wang, Kenneth Eng-Kian Lee, Jürgen Michel, Li-Shiuan Peh:
Automatic place-and-route of emerging LED-driven wires within a monolithically-integrated CMOS-III-V process. 344-349 - Zhezhi He, Deliang Fan:
A tunable magnetic skyrmion neuron cluster for energy efficient artificial neural network. 350-355 - Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan:
STAxCache: An approximate, energy efficient STT-MRAM cache. 356-361 - Fazal Hameed, Jerónimo Castrillón:
Rethinking on-chip DRAM cache for simultaneous performance and energy optimization. 362-367 - Tiago T. Jost, Gabriel L. Nazar, Luigi Carro:
An energy-efficient memory hierarchy for multi-issue processors. 368-373 - Yazhi Feng, Dan Feng, Chenye Yu, Wei Tong, Jingning Liu:
Mapping granularity adaptive FTL based on flash page re-programming. 374-379 - Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler:
Data flow testing for virtual prototypes. 380-385 - Alper Sen, Etem Deniz, Brian Kahne:
MINIME-validator: Validating hardware with synthetic parallel testcases. 386-391 - Farimah Farahmandi, Ronny Morad, Avi Ziv, Ziv Nevo, Prabhat Mishra:
Cost-effective analysis of post-silicon functional coverage events. 392-397 - Kenneth O'Brien, Lorenzo Di Tucci, Gianluca Durelli, Michaela Blott:
Towards exascale computing with heterogeneous architectures. 398-403 - Tobias Becker, Pavel Burovskiy, Anna Maria Nestorov, Hristina Palikareva, Enrico Reggiani, Georgi Gaydadjiev:
From exaflop to exaflow. 404-409 - Marco Rabozzi, Giuseppe Natale, Emanuele Del Sozzo, Alberto Scolari, Luca Stornaiuolo, Marco D. Santambrogio:
Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project. 410-415 - Dirk Stroobandt, Catalin Bogdan Ciobanu, Marco D. Santambrogio, Gabriel Figueiredo, Andreas Brokalakis, Dionisios N. Pnevmatikatos, Michael Hübner, Tobias Becker, Alex J. W. Thom:
An open reconfigurable research platform as stepping stone to exascale high-performance computing. 416-421 - Jan Burchard, Dominik Erb, Adit D. Singh, Sudhakar M. Reddy, Bernd Becker:
Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG. 422-427 - Jing Ye, Qingli Quo, Yu Hu, Xiaowei Li:
Fault diagnosis of arbiter physical unclonable function. 428-433 - Meng Zhang, Fei Wu, He Huang, Qian Xia, Jian Zhou, Changsheng Xie:
FPGA-based failure mode testing and analysis for MLC NAND flash memory. 434-439 - Ali BanaGozar, Mohammad Ali Maleki, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
Robust neuromorphic computing in the presence of process variation. 440-445 - Yue Ma, Thidapat Chantem, Robert P. Dick, Shige Wang, Xiaobo Sharon Hu:
An on-line framework for improving reliability of real-time systems on "big-little" type MPSoCs. 446-451 - Konstantinos Maragos, George Lentaris, Dimitrios Soudris, Kostas Siozios, Vasilis F. Pavlidis:
Application performance improvement by exploiting process variability on FPGA devices. 452-457 - Alwin Zulehner, Robert Wille:
Make it reversible: Efficient embedding of non-reversible functions. 458-463 - Nader Khammassi, Imran Ashraf, Xiang Fu, Carmen G. Almudéver, Koen Bertels:
QX: A high-performance quantum computer simulation platform. 464-469 - Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli:
Design automation and design space exploration for quantum computers. 470-475 - Rengarajan Ragavan, Benjamin Barrois, Cédric Killian, Olivier Sentieys:
Pushing the limits of voltage over-scaling for error-resilient applications. 476-481 - Xun Jiao, Vincent Camus, Mattia Cacciotti, Yu Jiang, Christian C. Enz, Rajesh K. Gupta:
Combining structural and timing errors in overclocked inexact speculative adders. 482-487 - Bert Moons, Roel Uytterhoeven, Wim Dehaene, Marian Verhelst:
DVAFS: Trading computational accuracy for energy through dynamic-voltage-accuracy-frequency-scaling. 488-493 - Alexandre Mercat, Justine Bonnot, Maxime Pelcat, Wassim Hamidouche, Daniel Ménard:
Exploiting computation skip to reduce energy consumption by approximate computing, an HEVC encoder case study. 494-499 - E. J. Jose Gonzalez, Chen Luo, Anshumali Shrivastava, Krishna V. Palem, Yongshik Moon, Soonhyun Noh, Daedong Park, Seongsoo Hong:
Location detection for navigation using IMUs with a map through coarse-grained machine learning. 500-505 - Nicholas C. Doyle, Eric Matthews, Graham M. Holland, Alexandra Fedorova, Lesley Shannon:
Performance impacts and limitations of hardware memory access trace collection. 506-511 - Sebastian Ottlik, Christoph Gerum, Alexander Viehl, Wolfgang Rosenstiel, Oliver Bringmann:
Context-sensitive timing automata for fast source level simulation. 512-517 - Raphael Eidenbenz, Alexandra Moga, Thanikesavan Sivanthi, Carsten Franke:
MARS: A flexible real-time streaming platform for testing automation systems. 518-523 - Saurav Kumar Ghosh, Soumyajit Dey:
SERD: A simulation framework for estimation of system level reliability degradation. 524-529 - Gopalakrishnan Srinivasan, Abhronil Sengupta, Kaushik Roy:
Magnetic tunnel junction enabled all-spin stochastic spiking neural network. 530-535 - Sophiane Senni, Thibaud Delobelle, Odilia Coi, Pierre-Yves Peneau, Lionel Torres, Abdoulaye Gamatié, Pascal Benoit, Gilles Sassatelli:
Embedded systems to high performance computing using STT-MRAM. 536-541 - Wang Kang, Liang Chang, Youguang Zhang, Weisheng Zhao:
Voltage-controlled MRAM for working memory: Perspectives and challenges. 542-547 - Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui:
Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor. 548-553 - Nour Sayed, Mojtaba Ebrahimi, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Opportunistic write for fast and reliable STT-MRAM. 554-559 - Tianjian Li, Yan Han, Xiaoyao Liang, Hsien-Hsin S. Lee, Li Jiang:
Fault clustering technique for 3D memory BISR. 560-565 - Yen-Hao Chen, Chien-Pang Chiu, Russell Barnes, TingTing Hwang:
Architectural evaluations on TSV redundancy for reliability enhancement. 566-571 - Neetu Jindal, Preeti Ranjan Panda, Smruti R. Sarangi:
Reusing trace buffers to enhance cache performance. 572-577 - Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler:
Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression. 578-583 - Zain Alabedin Haj Hammadeh, Rolf Ernst, Sophie Quinton, Rafik Henia, Laurent Rioux:
Bounding deadline misses in weakly-hard real-time systems with task dependencies. 584-589 - Sebastian Tobuschat, Rolf Ernst:
Real-time communication analysis for Networks-on-Chip with backpressure. 590-595 - Yasmina Abdeddaïm, Dorin Maxim:
Probabilistic schedulability analysis for fixed priority mixed criticality real-time systems. 596-601 - Rui Wu, Yuyang Wang, Zeyu Zhang, Chong Zhang, Clint L. Schow, John E. Bowers, Kwang-Ting Cheng:
Compact modeling and circuit-level simulation of silicon nanophotonic interconnects. 602-605 - Yuanzhuo Qu, Jie Han, Bruce F. Cockburn, Witold Pedrycz, Yue Zhang, Weisheng Zhao:
A true random number generator based on parallel STT-MTJs. 606-609 - Panagiotis Chaourani, Per-Erik Hellström, Saul Rodriguez, Raul Onet, Ana Rusu:
Enabling area efficient RF ICs through monolithic 3D integration. 610-613 - Ragh Kuttappa, Lunal Khuon, Bahram Nabet, Baris Taskin:
Reconfigurable threshold logic gates using optoelectronic capacitors. 614-617