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ORCID37th DAC 2000: Los Angeles, CA, USA
- Giovanni De Micheli:
Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000. ACM 2000 - Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums:
A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC. 1-6 - Peter J. Vancorenland, Carl De Ranter, Michiel Steyaert
, Georges G. E. Gielen:
Optimal RF design using smart evolutionary algorithms. 7-10 - Carl De Ranter, Bram De Muer, Geert Van der Plas, Peter J. Vancorenland, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen:
CYCLONE: automated design and layout of RF LC-oscillators. 11-14 - Carlo Guardiani, Sharad Saxena, Patrick McNamara, Phillip Schumaker, Dale Coder:
An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects. 15-18 - Tao Pi, Chuanjin Richard Shi:
Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits. 19-22 - In-Ho Moon, James H. Kukula, Kavita Ravi, Fabio Somenzi:
To split or to conjoin: the question in image computation. 23-28 - Roderick Bloem, Kavita Ravi, Fabio Somenzi:
Symbolic guided search for CTL model checking. 29-34 - Jin Yang, Andreas Tiemeyer:
Lazy symbolic model checking. 35-38 - Andreas Hett, Christoph Scholl, Bernd Becker:
Distance driven finite state machine traversal. 39-42 - Indradeep Ghosh, Masahiro Fujita:
Automatic test pattern generation for functional RTL circuits using assignment decision diagrams. 43-48 - Ian G. Harris, Russell Tessier:
Interconnect testing in cluster-based FPGA architectures. 49-54 - Ismet Bayraktaroglu, Alex Orailoglu:
Improved fault diagnosis in scan-based BIST via superposition. 55-58 - Irith Pomeranz, Sudhakar M. Reddy:
On diagnosis of pattern-dependent delay faults. 59-62 - Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David T. Blaauw:
On-chip inductance modeling and analysis. 63-68 - Eileen You, Lakshminarasimh Varadadesikan, John MacDonald, Wieze Xie:
A practical approach to parasitic extraction for design of multimillion-transistor integrated circuits. 69-74 - H. Levy, W. Scott, Don MacMillen, Jacob White:
A rank-one update method for efficient processing of interconnect parasitics in timing analysis. 75-78 - Andrew B. Kahng, Sudhakar Muddu, Egino Sarto:
On switch factor based analysis of coupled RC interconnects. 79-84 - Rob A. Rutenbar, Cheming Hu, Mark Horowitz, Stephen Y. Chow:
Life at the end of CMOS scaling (and beyond) (panel session) (abstract only). 85 - Dirk-Jan Jongeneel, Yosinori Watanabe, Robert K. Brayton, Ralph H. J. M. Otten:
Area and search space control for technology mapping. 86-91 - Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal:
BDS: a BDD-based logic optimization system. 92-97 - Junhyung Um, Taewhan Kim, C. L. Liu:
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. 98-103 - Hai Zhou, D. F. Wong:
Optimal low power X OR gate decomposition. 104-107 - Seapahn Meguerdichian, Miodrag Potkonjak:
Watermarking while preserving the critical path. 108-111 - Miroslav N. Velev, Randal E. Bryant:
Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction. 112-117 - Chung-Yang Huang, Kwang-Ting Cheng:
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. 118-123 - Chris Wilson, David L. Dill:
Reliable verification using symbolic simulation with scalar values. 124-129 - David W. Currie, Alan J. Hu, Sreeranga P. Rajan:
Automatic formal verification of DSP software. 130-135 - Yervant Zorian, Erik Jan Marinissen:
System chip test: how will it impact your design? 136-141 - Kwang-Ting Cheng, Sujit Dey, Mike Rodgers, Kaushik Roy:
Test challenges for deep sub-micron technologies. 142-149 - Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David T. Blaauw:
Hierarchical analysis of power distribution networks. 150-155 - Sani R. Nassif, Joseph N. Kozhaya:
Fast power grid simulation. 156-161 - Rajat Chaudhry, David T. Blaauw, Rajendran Panda, Tim Edwards:
Current signature compression for IR-drop analysis. 162-167 - Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas:
Impact of interconnect variations on the clock skew of a gigahertz microprocessor. 168-171 - Vikas Mehrotra, Shiou Lin Sam, Duane S. Boning, Anantha P. Chandrakasan, Rakesh Vallishayee, Sani R. Nassif:
A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance. 172-175 - Raul Camposano, Jacob Greidinger, Patrick Groeneveld, Michael Jackson, Lawrence T. Pileggi, Louis Scheffer:
Design closure (panel session): hope or hype? 176-177 - Baolin Yang, Joel R. Phillips:
A multi-interval Chebyshev collocation method for efficient high-accuracy RF circuit simulation. 178-183 - Joel R. Phillips:
Projection frameworks for model reduction of weakly nonlinear systems. 184-189 - Chandramouli V. Kashyap, Byron Krauter:
A realizable driving point model for on-chip interconnect with inductance. 190-195 - Amit Goel, William R. Lee:
Formal verification of an IBM CoreConnect processor local bus arbiter core. 196-200 - Mark D. Aagaard, Robert B. Jones, Roope Kaivola, Katherine R. Kohatsu, Carl-Johan H. Seger:
Formal verification of iterative algorithms in microprocessors. 201-206 - John C. Lach, William H. Mangione-Smith, Miodrag Potkonjak:
Efficient error detection, localization, and correction for FPGA-based debugging. 207-212 - Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, Krishna Saraswat:
Multiple Si layer ICs: motivation, performance analysis, and design implications. 213-220 - Vince E. Boros, Aleksandar D. Rakic, Sri Parameswaran:
High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system. 221-226 - Michael T. Niemier, Michael J. Kontz, Peter M. Kogge:
A design of and design tools for a novel quantum dot based microprocessor. 227-232 - Rafi Levy, David T. Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov:
ClariNet: a noise analysis tool for deep submicron design. 233-238 - Kenneth L. Shepard, Dae-Jin Kim:
Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technology. 239-242 - Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De:
Dynamic noise analysis in precharge-evaluate circuits. 243 - Janet Meiling Wang, Tuyen V. Nguyen:
Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources. 247-252 - Jennifer Smith, Tom Quan, Andrew B. Kahng:
EDA meets.COM (panel session): how E-services will change the EDA business model. 253 - Clayton B. McDonald, Randal E. Bryant:
Symbolic timing simulation using cluster scheduling. 254-259 - Soha Hassoun:
Critical path analysis using a dynamically bounded delay model. 260-265 - Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi:
TACO: timing analysis with coupling. 266-269 - David T. Blaauw, Rajendran Panda, Abhijit Das:
Removing user specified false paths from timing graphs. 270-273 - Jason Cong, Sung Kyu Lim, Chang Wu:
Performance driven multi-level and multiway partitioning with retiming. 274-279 - Ki-Wook Kim, Unni Narayanan, Sung-Mo Kang:
Domino logic synthesis minimizing crosstalk. 280-285 - Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska:
Fast post-placement rewiring using easily detectable functional symmetries. 286-289 - Jason Cong, Hui Huang:
Depth optimal incremental mapping for field programmable gate arrays. 290-293 - Haris Lekatsas, Jörg Henkel, Wayne H. Wolf:
Code compression for low power embedded system design. 294-299 - Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Synthesis of application-specific memories for power optimization in embedded systems. 300-303 - Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye:
Influence of compiler optimizations on system power. 304-307 - Catherine H. Gebotys, Robert J. Gebotys, S. Wiratunga:
Power minimization derived from architectural-usage of VLIW processors. 308-311 - Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Power analysis of embedded operating systems. 312-315 - Peter Grun, Nikil D. Dutt, Alexandru Nicolau:
Memory aware compilation through accurate timing extraction. 316-321 - Stephen A. Edwards:
Compiling Esterel into sequential code. 322-327 - Thierry J.-F. Omnés, Thierry Franzetti, Francky Catthoor:
Interactive co-design of high throughput embedded multimedia. 328-331 - Naji Ghazal, A. Richard Newton, Jan M. Rabaey:
Predicting performance potential of modern DSPs. 332-335 - Brian Dipert, Danesh Tavana, Barry K. Britton, Bill Harris, Bob Boderson, Chris Rowen:
Future systems-on-chip: software of hardware design? (panel session). 336-337 - A. Richard Newton, Walden C. Rhines, Sünke Mehrgardt, Henry Samueli, Tudor Brown:
Embedded systems design in the new millennium (panel session). 338-339 - Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
The design and use of simplepower: a cycle-accurate energy estimation tool. 340-345 - Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto:
An instruction-level functionally-based energy estimation model for 32-bits microprocessors. 346-351 - Qinru Qiu, Qing Wu, Massoud Pedram:
Dynamic power management of complex systems using generalized stochastic Petri nets. 352-356 - Luca Macchiarulo, Malgorzata Marek-Sadowska:
Wave-steering one-hot encoded FSMs. 357-360 - Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli:
Performance analysis and optimization of latency insensitive systems. 361-367 - Ashok Jagannathan, Sung-Woo Hur, John Lillis:
A fast algorithm for context-aware buffer insertion. 368-373 - Minghorng Lai, D. F. Wong:
Maze routing with buffer insertion and wiresizing. 374-378 - Jason Cong, Xin Yuan:
Routing tree construction under fixed buffer locations. 379-384 - Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke:
A current driven routing and verification methodology for analog applications. 385-389 - JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas:
A codesign virtual machine for hierarchical, balanced hardware/software system modeling. 390-395 - Dirk Desmet, Diederik Verkest, Hugo De Man:
Operating system based software generation for systems-on-chip. 396-401 - Erwin A. de Kock, W. J. M. Smits, Pieter van der Wolf, Jean-Yves Brunel, W. M. Kruijtzer, Paul Lieverse, Kees A. Vissers, Gerben Essink:
YAPI: application modeling for signal processing systems. 402-405 - Jean-Yves Brunel, W. M. Kruijtzer, H. J. H. N. Kenter, Frédéric Pétrot, L. Pasquier, Erwin A. de Kock, W. J. M. Smits:
COSY communication IP's. 406-409 - Pai H. Chou, Gaetano Borriello:
Synthesis and optimization of coordination controllers for distributed embedded systems. 410-415 - Derek Chiou, Prabhat Jain, Larry Rudolph, Srinivas Devadas:
Application-specific memory management for embedded systems using software-controlled caches. 416-419 - Reinaldo A. Bergamaschi, William R. Lee:
Designing systems-on-chip using cores. 420-425 - Marinés Puig-Medina, Gülbin Ezer, Pavlos Konas:
Verification of configurable processor cores. 426-431 - Krishnendu Chakrabarty:
Design of system-on-a-chip test access architectures under place-and-route and power constraints. 432-437 - Richard Goering, Clifford E. Cummings, Steven E. Schulz, Simon Davidman, John Sanguinetti, Joachim Kunkel, Oz Levia:
The future of system design languages (panel session). 438-439 - Gerd Vandersteen, Piet Wambacq, Yves Rolain, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens:
A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers. 440-445 - Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels, Ivo Bolsens:
High-level simulation of substrate noise generation including power supply noise coupling. 446-451 - Geert Van der Plas, Jan Vandenbussche, Walter Daems, Antal van den Bosch, Georges G. E. Gielen, Willy M. C. Sansen:
Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter. 452-457 - Yun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, Shu-Wei Wu:
B*-Trees: a new representation for non-slicing floorplans. 458-463 - Yingxin Pang, Florin Balasa, Koen Lampaert, Chung-Kuan Cheng:
Block placement with symmetry constraints based on the O-tree non-slicing representation. 464-467 - Pinghong Chen, Ernest S. Kuh:
Floorplan sizing by linear programming approximation. 468-471 - Shih-Lian T. Ou, Massoud Pedram:
Timing-driven placement based on partitioning with dynamic cut-net control. 472-476 - Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Can recursive bisection alone produce routable placements? 477-482 - Marco Di Natale, Alberto L. Sangiovanni-Vincentelli, Felice Balarin:
Task scheduling with RT constraints. 483-488 - Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Marc Massot, Sandra Moral, Claudio Passerone, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli:
Task generation and compile-time scheduling for mixed data-control embedded software. 489-494 - Youngsoo Shin, Daehong Kim, Kiyoung Choi:
Schedulability-driven performance analysis of multiple mode embedded real-time systems. 495-500 - Athanassios Boulis, Mani B. Srivastava:
System design of active basestations based on dynamically reconfigurable hardware. 501-506 - Yanbing Li, Tim Callahan, Ervan Darnell, Randolph E. Harr, Uday Kurkure, Jon Stockwood:
Hardware-software co-design of embedded reconfigurable architectures. 507-512 - Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey:
Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. 513-518 - Sharad Malik, D. K. Arvind, Edward A. Lee, Phil Koopman, Alberto L. Sangiovanni-Vincentelli, Wayne H. Wolf:
Embedded systems education (panel abstract). 519 - Qingjian Yu, Janet Meiling Wang, Ernest S. Kuh:
Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks. 520-525 - Emad Gad, Anestis Dounavis, Michel S. Nakhla, Ramachandra Achar:
Passive model order reduction of multiport distributed interconnects. 526-531 - Bernard N. Sheehan:
Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments. 532-535 - Jinsong Zhao:
Singularity-treated quadrature-evaluated method of moments solver for 3-D capacitance extraction. 536-539 - Zhong Wang, Michael Kirkpatrick, Edwin Hsing-Mean Sha:
Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications. 540-545 - M. Narasimhan, J. Ramanujam:
On lower bounds for scheduling problems in high-level synthesis. 546-551 - Jens Horstmannshoff, Heinrich Meyr:
Efficient building block based RTL code generation from synchronous data flow graphs. 552-555 - Peeter Ellervee, Miguel Miranda, Francky Catthoor, Ahmed Hemani:
System-level data format exploration for dynamically allocated data structures. 556-559 - Daniel Foty, David M. Binkley:
MOSFET modeling and circuit design: re-establishing a lost connection (tutorial). 560 - Brad L. Hutchings, Brent E. Nelson:
Using general-purpose programming languages for FPGA design. 561-566 - Yao-Wen Chang, Yu-Tsang Chang:
An architecture-driven metric for simultaneous placement and global routing for FPGAs. 567-572 - Hartej Singh, Guangming Lu, Eliseu M. Chaves Filho, Rafael Maestre, Ming-Hau Lee, Fadi J. Kurdahi, Nader Bagherzadeh:
MorphoSys: case study of a reconfigurable computing system targeting multimedia applications. 573-578 - Stephan Ohr, Rob A. Rutenbar, Henry Chang, Georges G. E. Gielen, Rudolf Koch, Roy McGuffin, K. C. Murphy:
Survival strategies for mixed-signal systems-on-chip (panel session). 579-580 - Darko Kirovski, David T. Liu, Jennifer L. Wong, Miodrag Potkonjak:
Forensic engineering techniques for VLSI CAD tools. 581-586 - Gang Qu, Miodrag Potkonjak:
Fingerprinting intellectual property using constraint-addition. 587-592 - Marcello Dalpasso, Alessandro Bogliolo, Luca Benini:
Hardware/software IP protection. 593-596 - Alessandro Fin, Franco Fummi:
A Web-CAD methodology for IP-core analysis and simulation. 597-600 - Gianpiero Cabodi, Stefano Quer, Fabio Somenzi:
Optimizing sequential verification by retiming transformations. 601-606 - Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
Efficient methods for embedded system design space exploration. 607-612