28th DAC 1991: San Francisco, California, USA

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Application of Mixed Integer Linear Programming to High-Level Synthesis

Circuit and Timing Simulation


Multi-Layer Area Routing

Synthesis and Delay Testing

Technology Mapping

Design Automation in the Soviet Union


Over the Cell Channel Routing

Fault Simulation

Sequential Synthesis


Leading-Edge Design Systems

Improving Simulator Performance

Synthesis for Programmable Gate Arrays


Layout Systems

Design for Testability and Built In Self Test

Synthesis of Asynchronous Circuits


Global Considerations in Routing

Test Pattern Generation

Datapath and Control Synthesis

Formal Design Verification

Partitioning and Placement

Testability Analysis

Logic Optimization


Module Generators

CAD for Analog Cells and ICs

Interfacing to High-Level Synthesis: Above and Below

Critical Path Analysis of Logic Gate Networks

Timing Modeling of Interconnect

Technology CAD

Synthesis of High-Performance Systems


Placement for Performance Optimization

Extending the Functionality of Discrete Simulation

Scheduling in High-Level Synthesis I