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ORCIDDATE 2008: Munich, Germany
- Donatella Sciuto:
Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008. ACM 2008, ISBN 978-3-9810801-3-1 - Pieter J. Mosterman, Don Orofino, Janos Sztipanovits, Ahmed Amine Jerraya, Wido Kruijtzer, Víctor Reyes, Christos G. Cassandras, Grant Martin:
Automatically Realising Embedded Systems from High-Level Functional Models. - Jürgen Becker, Michael Hübner, Robert Esser, Andreas Herkersdorf, Walter Stechele, Vera Lauer:
Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems. - Rainer Leupers, Gerd Ascheid, Wilfried Verachtert, Tom Ashby, Arnout Vandecappelle:
System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures. - Diana Marculescu
, Sani R. Nassif:
Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level. - Jerry Frenkil, Ken Choi, Kimiyoshi Usami:
Power Gating for Ultra-low Leakage: Physics, Design, and Analysis. - Eugenio Villar, Axel Jantsch, Christoph Grimm, Tim Kogel:
Heterogeneous System-level Specification Using SystemC. - Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen:
Power-Aware Testing and Test Strategies for Low Power Devices. - David M. Binkley, Helmut E. Graeb, Georges G. E. Gielen, Jaijeet S. Roychowdhury:
From Transistor to PLL - Analogue Design and EDA Methods. - Carsten Elgert, Volker Herbig, Anton Ossner, Thomas Harms, Emmanuel Blanc:
DfM in the Analogue and Digital World. - Rolf Ernst, Marek Jersak, Hans Sarnowski, Marco Bekooij, Samarjit Chakraborty:
Formal Methods in System and MpSoC Performance Analysis and Optimisation. - Dimitris Gizopoulos, Kaushik Roy, Subhasish Mitra, Pia N. Sanda:
Soft Errors: System Effects, Protection Techniques and Case Studies. - Giovanni De Micheli:
Designing Micro/Nano Systems for a Safer and Healthier Tomorrow. 1 - Dominique Vernay:
Perspective on Embedded Systems: Challenges, Solutions and Research Priorities. 2 - Yonghyun Hwang, Samar Abdi, Daniel Gajski:
Cycle-approximate Retargetable Performance Estimation at the Transaction Level. 3-8 - Jérôme Cornet, Florence Maraninchi, Laurent Maillet-Contoz:
A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip. 9-14 - Nicola Bombieri, Nicola Deganello, Franco Fummi:
Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation. 15-20 - Walter Fuß:
Tailored Solutions for Safety-Installations in the Loetschberg Tunnel - A Project with Importance for the Trans-European Rail Traffic. 21-25 - Jan B. Freuer, Göran Jerke, Joachim Gerlach, Wolfgang Nebel:
On the Verification of High-Order Constraint Compliance in IC Design. 26-31 - Wido Kruijtzer, Pieter van der Wolf, Erwin A. de Kock, Jan Stuyt, Wolfgang Ecker, Albrecht Mayer, Serge Hustin, Christophe Amerijckx, Serge de Paoli, Emmanuel Vaumorin:
Industrial IP Integration Flows based on IP-XACT Standards. 32-37 - Timo Vogt, Norbert Wehn:
A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment. 38-43 - Ben Cope, Peter Y. K. Cheung, Wayne Luk:
Using Reconfigurable Logic to Optimise GPU Memory Accesses. 44-49 - Katarina Paulsson, Michael Hübner, Jürgen Becker:
Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs. 50-55 - Bernd Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll:
Design flow for embedded FPGAs based on a flexible architecture template. 56-61 - A. Tchegho, Heinz Mattes, Sebastian Sattler:
Optimal High-Resolution Spectral Analyzer. 62-67 - Haralampos-G. D. Stratigopoulos, Jeanne Tongbong, Salvador Mir:
A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation. 68-73 - Amir Zjajo, José Pineda de Gyvez:
Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters. 74-79 - Manuel J. Barragan Asian, Diego Vázquez, Adoración Rueda:
Practical Implementation of a Network Analyzer for Analog BIST Applications. 80-85 - Joost-Pieter Katoen:
Quantitative Evaluation in Embedded System Design: Trends in Modeling and Analysis Techniques. 86-87 - Nicolas Coste, Hubert Garavel, Holger Hermanns, Richard Hersemeule, Yvain Thonnart, Meriem Zidouni:
Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures. 88-89 - Lucia Cloth, Boudewijn R. Haverkort:
Quantitative Evaluation in Embedded System Design: Predicting Battery Lifetime in Mobile Devices. 90-91 - Ying Tan, Qinru Qiu:
A Framework of Stochastic Power Management Using Hidden Markov Model. 92-97 - Yu Zhou, Somnath Paul, Swarup Bhunia:
Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement. 98-103 - Davide Brunelli, Luca Benini, Clemens Moser, Lothar Thiele:
An Efficient Solar Energy Harvester for Wireless Sensor Nodes. 104-109 - Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen P. Boyd, Luca Benini, Giovanni De Micheli:
Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization. 110-115 - Amir Hossein Ghamarian, Marc Geilen, Twan Basten, Sander Stuijk:
Parametric Throughput Analysis of Synchronous Data Flow Graphs. 116-121 - Gunar Schirner, Rainer Dömer:
Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling. 122-127 - Kim Grüttner, Frank Oppenheimer, Wolfgang Nebel, Fabien Colas-Bigey, Anne-Marie Fouilliart:
SystemC-based Modelling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder. 128-133 - Michel Vasilevski, François Pêcheux, Nicolas Beilleau, Hassan Aboushady, Karsten Einwich:
Modeling and Refining Heterogeneous Systems With SystemC-AMS: Application to WSN. 134-139 - Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann:
Sizing Rules for Bipolar Analog Circuit Design. 140-145 - Tom J. Kazmierski, Dafeng Zhou, Bashir M. Al-Hashimi:
Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density. 146-151 - Sawal Ali, Reuben Wilcock, Peter R. Wilson, Andrew D. Brown:
A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits. 152-157 - Michael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich:
Symbolic Reliability Analysis and Optimization of ECU Networks. 158-163 - Djones Lettnin, Pradeep Kumar Nalla, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel, Tobias Kirsten, Volker Schönknecht, Stephan Reitemeyer:
Verification of Temporal Properties in Automotive Embedded Software. 164-169 - Bernd Stube, Bernd Schröder, Eckart Hoene, Andre Lissner:
A Novel Approach for EMI Design of Power Electronics. 170-175 - Nicolas Alt, Christopher Claus, Walter Stechele:
Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments. 176-181 - Ozgur Sinanoglu, Erik Jan Marinissen:
Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing. 182-187 - Anders Larsson, Erik Larsson, Krishnendu Chakrabarty, Petru Eles, Zebo Peng:
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns. 188-193 - Paolo Bernardi, Matteo Sonza Reorda:
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers. 194-199 - Jelte Peter Vink, Kees van Berkel, Pieter van der Wolf:
Performance Analysis of SoC Architectures Based on Latency-Rate Servers. 200-205 - Sujan Pandey, Rolf Drechsler:
Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs. 206-211 - Philip K. F. Hölzenspies, Johann L. Hurink, Jan Kuper, Gerard J. M. Smit:
Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC). 212-217 - Sungchan Kim, Chanik Park, Soonhoi Ha:
Architecture Exploration of NAND Flash-based Multimedia Card. 218-223 - Hwisung Jung, Massoud Pedram:
Resilient Dynamic Power Management under Uncertainty. 224-229 - Clemens Moser, Lothar Thiele, Davide Brunelli, Luca Benini:
Robust and Low Complexity Rate Control for Solar Powered Sensors. 230-235 - Shaobo Liu, Qinru Qiu, Qing Wu:
Energy Aware Dynamic Voltage and Frequency Selection for Real-Time Systems with Energy Harvesting. 236-241 - Sungpack Hong, Sungjoo Yoo, Byeong Bin, Kyu-Myung Choi, Soo-Kwan Eo, Taehwan Kim:
Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution. 242-247 - Thidapat Chantem, Robert P. Dick, Xiaobo Sharon Hu:
Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs. 288-293 - Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran:
A Formal Approach To The Protocol Converter Problem. 294-299 - Arno Moonen, Marco Bekooij, René van den Berg, Jef L. van Meerbergen:
Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip. 300-305 - Greg Hoover, Forrest Brewer:
Synthesizing Synchronous Elastic Flow Networks. 306-311 - Igor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Periodic Steady-State Analysis Augmented with Design Equality Constraints. 312-317 - Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney, Kiran K. Gullapalli:
Analysis of Oscillator Injection Locking by Harmonic Balance Method. 318-323 - Sebastian Steinhorst, Lars Hedrich:
Model Checking of Analog Systems using an Analog Specification Language. 324-329 - Grégory Gailliard, Hugues Balp, Michel Sarlotte, François Verdier:
Mapping Semantics of CORBA IDL and GIOP to Open Core Protocol for Portability and Interoperability of SDR Waveform Components. 330-335 - Luca Sterpone, M. A. Aguirre, Jonathan Noel Tombs, Hipólito Guzmán-Miranda:
On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications. 336-341 - Massimiliano Melani, Lorenzo Bertini, Marco De Marinis, Peter Lange, Francesco D'Ascoli, Luca Fanucci:
Hot Wire Anemometric MEMS Sensor for Water Flow Monitoring. 342-347 - Drew C. Ness, David J. Lilja:
Guiding Circuit Level Fault-Tolerance Design with Statistical Methods. 348-353 - Charu Nagpal, Rajesh Garg, Sunil P. Khatri:
A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. 354-359 - Wenjing Rao, Alex Orailoglu:
Towards fault tolerant parallel prefix adders in nanoelectronic systems. 360-365 - Swaroop Ghosh, Patrick Ndai, Kaushik Roy:
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking. 366-371 - Jan Beutel, Michael Beigl, Adam Dunkels, Koen Langendoen:
Embedded Tutorial - Software for Wireless Networked Embedded Systems. 372 - Lawrence Leinweber, Swarup Bhunia:
Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction. 373-378 - Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
A Scalable Algorithmic Framework for Row-Based Power-Gating. 379-384 - Ehsan Pakbaznia, Massoud Pedram:
Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting. 385-390 - T. Forest, Alberto Ferrari, G. Audisio, Marco Sabatini, Alberto L. Sangiovanni-Vincentelli, Marco Di Natale:
Physical Architectures of Automotive Systems. 391-395 - Nicola Bombieri, Franco Fummi, Graziano Pravadelli:
A Mutation Model for the SystemC TLM 2.0 Communication Interfaces. 396-401 - Weixin Wu, Michael S. Hsiao:
Efficient Design Validation Based on Cultural Algorithms. 402-407 - João Marques-Silva, Jordi Planes:
Algorithms for Maximum Satisfiability using Unsatisfiable Cores. 408-413 - Shan Tang, Qiang Xu:
In-band Cross-Trigger Event Transmission for Transaction-Based Debug. 414-419 - João M. S. Silva, Joel R. Phillips, Luís Miguel Silveira:
Efficient Representation and Analysis of Power Grids. 420-425 - Navin Srivastava, Roberto Suaya, Kaustav Banerjee:
High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. 426-431 - Duo Li, Sheldon X.-D. Tan, Bruce McGaughy:
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis. 432-437 - Basel Halak, Alexandre Yakovlev:
Bandwidth-Centric Optimisation for Area-Constrained Links with Crosstalk Avoidance Methods. 438-443 - Min Li, Bruno Bougard, Weiyu Xu, David Novo, Liesbet Van der Perre, Francky Catthoor:
Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures. 444-449 - Akash Kumar, Kees van Berkel:
Vectorization of Reed Solomon Decoding and Mapping on the EVP. 450-455 - Matthias May, Matthias Alles, Norbert Wehn:
A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder. 456-461 - Anshuman Chandra, Felix Ng, Rohit Kapur:
Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction. 462-467 - Melanie Elm, Hans-Joachim Wunderlich:
Scan Chain Organization for Embedded Diagnosis. 468-473 - Vasileios Tenentes, Xrysovalantis Kavousianos, Emmanouil Kalligeros:
State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores. 474-479 - Jason G. Brown, Brian Taylor, Ronald D. Blanton, Larry T. Pileggi:
Automated Testability Enhancements for Logic Brick Libraries. 480-485 - Alexandre David, Kim Guldstrand Larsen, Shuhao Li, Brian Nielsen:
A Game-Theoretic Approach to Real-Time System Testing. 486-491 - Jonas Rox, Rolf Ernst:
Modeling Event Stream Hierarchies with Hierarchical Event Models. 492-497 - Luiza Gheorghe, Faouzi Bouchhima, Gabriela Nicolescu, Hanifa Boucheneb:
Semantics for Model-Based Validation of Continuous/Discrete Systems. 498-503 - Lisane B. de Brisolara, Marcio Ferreira da Silva Oliveira, Ricardo Miotto Redin, Luís C. Lamb, Luigi Carro, Flávio Rech Wagner:
Using UML as Front-end for Heterogeneous Software Code Generation Strategies. 504-509 - S. Turnoy, Peter Wintermayr, Robert C. Aitken, Rudy Lauwereins, J. Tracy Weed, V. Kiefer, J. Hartmann:
Panel Session - Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm. 510 - Harald Heinecke, Werner Damm, Bernhard Josko, Alexander Metzner, Hermann Kopetz, Alberto L. Sangiovanni-Vincentelli, Marco Di Natale:
Software Components for Reliable Automotive Systems. 549-554 - Herbert Hanselmann:
Model-Based-Design Is Nice But... 555 - Soheil Samii, Sergiu Rafiliu, Petru Eles, Zebo Peng:
A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems. 556-561 - Bao Liu:
Signal Probability Based Statistical Timing Analysis. 562-567 - Behnam Amelifard, Safar Hatami, Hanif Fatemi, Massoud Pedram:
A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect. 568-573 - Amit Goel, Sarma B. K. Vrudhula:
Current source based standard cell model for accurate signal integrity and timing analysis. 574-579 - Wangyang Zhang, Wenjian Yu, Zeyi Wang, Zhiping Yu, Rong Jiang, Jinjun Xiong:
An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation. 580-585 - Jorge Fernandez Villena, Luís Miguel Silveira:
SPARE - a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction. 586-591 - Brian Cline, Kaviraj Chopra, David T. Blaauw, Andres Torres, Savithri Sundareswaran:
Transistor-Specific Delay Modeling for SSTA. 592-597 - Min Li, David Novo, Bruno Bougard, Liesbet Van der Perre, Francky Catthoor:
Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications. 598-603 - Ralf König, Timo Stripf, Jürgen Becker:
A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms. 604-609 - Philippe Bonnot, Fabrice Lemonnier, Gilbert Edelin, Gerard Gaillat, Olivier Ruch, Pascal Gauget:
Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA. 610-615 - Aswin Sreedhar, Alodeep Sanyal, Sandip Kundu:
On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits. 616-621 - Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah, Peter A. Habitz:
Optimal Margin Computation for At-Speed Test. 622-627 - Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker:
Resistive Bridging Fault Simulation of Industrial Circuits. 628-633 - Yen-Tzu Lin, Osei Poku, Naresh K. Bhatti, Ronald D. Blanton:
Physically-Aware N-Detect Test Pattern Selection. 634-639 - Maarten Wiggers, Marco Bekooij, Gerard J. M. Smit:
Computation of Buffer Capacities for Throughput