default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDDATE 2007: Nice, France
- Rudy Lauwereins, Jan Madsen:
2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007. EDA Consortium, San Jose, CA, USA 2007, ISBN 978-3-9810801-2-4 - Tohru Furuyama:
Keynote address: Challenges of digital consumer and mobile SoC's: more Moore possible? 1 - Alan Naumann:
Keynote address: Was Darwin wrong? Has design evolution stopped at the RTL level... or will software and custom processors (or system-level design) extend Moore's law? 2
Design records
- Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun:
ATLAS: a chip-multiprocessor with transactional memory support. 3-8 - Fabio Campi, Antonio Deledda, Matteo Pizzotti
, Luca Ciccarelli, Pier Luigi Rolandi, Claudio Mucci, Andrea Lodi, Arseni Vitkovski, Luca Vanzolini:
A dynamically adaptive DSP for heterogeneous reconfigurable platforms. 9-14 - Phillip Stanley-Marbell, Diana Marculescu:
An 0.9 × 1.2", low power, energy-harvesting system with custom multi-channel communication interface. 15-20 - Zhuan Ye, John Grosspietsch, Gokhan Memik:
Interactive presentation: An FPGA based all-digital transmitter with radio frequency output for software defined radio. 21-26
Design for testability for SoCs
- Ozgur Sinanoglu, Tsvetomir Petrov:
A non-intrusive isolation approach for soft cores. 27-32 - Seongmoon Wang, Wenlong Wei, Srimat T. Chakradhar:
Unknown blocking scheme for low control data volume and high observability. 33-38 - Quming Zhou, Kedarnath J. Balakrishnan:
Test cost reduction for SoC using a combined approach to test data compression and test scheduling. 39-44 - Sying-Jyan Wang, Tung-Hua Yeh:
High-level test synthesis for delay fault testability. 45-50
Communication synthesis under timing constraints
- Traian Pop, Paul Pop, Petru Eles, Zebo Peng:
Bus access optimisation for FlexRay-based distributed embedded systems. 51-56 - Nadathur Satish, Kaushik Ravindran, Kurt Keutzer:
A decomposition-based constraint optimization approach for statically scheduling task graphs with communication delays to multiprocessors. 57-62 - Chuan Lin, Aiguo Xie, Hai Zhou:
Design closure driven delay relaxation based on convex cost network flow. 63-68
Performance modelling and synthesis of analogue/mixed-signal circuits
- Varun Aggarwal, Una-May O'Reilly:
Simulation-based reusable posynomial models for MOS transistor parameters. 69-74 - Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann:
Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming. 75-80 - Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen:
An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection. 81-86 - Ömer Yetik, Muharrem Orkun Saglamdemir, Selçuk Talay, Günhan Dündar:
Interactive presentation: A coefficient optimization and architecture selection tool for SigmaDelta modulators in MATLAB. 87-92
System level mapping and simulation
- Wei Zheng, Marco Di Natale, Claudio Pinello, Paolo Giusto, Alberto L. Sangiovanni-Vincentelli:
Synthesis of task and message activation models in real-time distributed automotive systems. 93-98 - Christopher Ostler, Karam S. Chatha:
An ILP formulation for system-level application mapping on network processor architectures. 99-104 - Paolo Destro, Franco Fummi, Graziano Pravadelli:
A smooth refinement flow for co-designing HW and SW threads. 105-110 - Youssef N. Naguib, Rafik S. Guindi:
Speeding up SystemC simulation through process splitting. 111-116 - Akash Kumar, Andreas Hansson, Jos Huisken, Henk Corporaal:
Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip. 117-122
Algorithms and applications of run-time reconfiguration
- Florian Dittmann, Stefan Frank:
Hard real-time reconfiguration port scheduling. 123-128 - Jin Cui, Qingxu Deng, Xiuqiang He, Zonghua Gu:
An efficient algorithm for online management of 2D area of partially reconfigurable FPGAs. 129-134 - Ahmed A. El Farag, Hatem M. El-Boghdadi, Samir I. Shaheen:
Improving utilization of reconfigurable resources using two dimensional compaction. 135-140 - Roman L. Lysecky:
Low-power warp processor for power efficient high-performance embedded systems. 141-146 - Yang Qu, Juha-Pekka Soininen, Jari Nurmi:
Interactive presentation: Using dynamic voltage scaling to reduce the configuration energy of run time reconfigurable devices. 147-152 - Mona Safar, Mohamed Shalan, M. Watheq El-Kharashi, Ashraf Salem:
Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver. 153-158
IP designs for media processing and other computational intensive kernels
- Markos E. Papadonikolakis, Vasilleios Pantazis, Athanasios Kakarountas:
Efficient high-performance ASIC implementation of JPEG-LS encoder. 159-164 - Yen-Jen Chang, Yuan-Hong Liao, Shanq-Jang Ruan:
Improve CAM power efficiency using decoupled match line scheme. 165-170 - André B. J. Kokkeler, Gerard J. M. Smit, Thijs Krol, Jan Kuper:
Cyclostationary feature detection on a tiled-SoC. 171-176 - C. Arbelo, Andreas Kanstein, Sebastián López, José Francisco López, Mladen Berekovic, Roberto Sarmiento, Jean-Yves Mignolet:
Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter. 177-182 - Esra Sahin, Ilker Hamzaoglu:
Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm. 183-188 - Ramanathan Narayanan, Daniel Honbo, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno:
Interactive presentation: An FPGA implementation of decision tree classification. 189-194 - Nishant R. Srivastava:
Interactive presentation: Radix 4 SRT division with quotient prediction and operand scaling. 195-200
Test infrastructure of SoCs and its verification
- Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon Wang:
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling. 201-206 - Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng:
Optimized integration of test compression and sharing for SOC testing. 207-212 - Oliver Spang, Hans Martin von Staudt, Michael G. Wahl:
A sophisticated memory test engine for LCD display drivers. 213-218 - Thuyen Le, Tilman Glökler, Jason Baumgartner:
Formal verification of a pervasive interconnect bus system in a high-performance microprocessor. 219-224 - Ehab Anis, Nicola Nicolici:
Interactive presentation: Low cost debug architecture using lossy compression for silicon debug. 225-230 - Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara:
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers. 231-236
Hot topic - Microprocessors in the era of terascale integration
- Shekhar Borkar, Norman P. Jouppi, Per Stenström:
Microprocessors in the era of terascale integration. 237-242
Statistical/nonlinear analysis and verification for analogue circuits
- Min Zhang, Markus Olbrich, David Seider, Martin Frerichs, Harald Kinzelbach, Erich Barke:
CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions. 243-248 - Ghiath Al Sammane, Mohamed H. Zaki, Sofiène Tahar:
A symbolic methodology for the verification of analog and mixed signal designs. 249-254 - Dani Tannir, Roni Khazaka:
Efficient nonlinear distortion analysis of RF circuits. 255-260 - Jonathan Borremans, Ludwig De Locht, Piet Wambacq, Yves Rolain:
Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysis. 261-266 - John Lataire, Gerd Vandersteen, Rik Pintelon:
Interactive presentation: Optimizing analog filter designs for minimum nonlinear distortions using multisine excitations. 267-272
System modeling and specification
- Simon Schliecker, Steffen Stein, Rolf Ernst:
Performance analysis of complex systems by integration of dataflow graphs and compositional performance analysis. 273-278 - Hiren D. Patel, Sandeep K. Shukla:
Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL. 279-284 - Marc Geilen, Twan Basten:
A calculator for Pareto points. 285-290 - Shuilong Huang, Huainan Ma, Zhihua Wang:
Modeling and simulation to the design of SigmaDelta fractional-N frequency synthesizer. 291-296 - Fei Gong, Xiaobo Wu:
Interactive presentation: System level power optimization of Sigma-Delta modulator. 297-300 - Leandro Soares Indrusiak, Andreas Thuy, Manfred Glesner:
Interactive presentation: Executable system-level specification models containing UML-based behavioral patterns. 301-306
Design space exploration and nano-technologies for reconfigurable computing
- Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud:
Assessing carbon nanotube bundle interconnect for future FPGA architectures. 307-312 - Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid:
Two-level microprocessor-accelerator partitioning. 313-318 - Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Design space exploration of partially re-configurable embedded processors. 319-324 - Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Maziar Goudarzi:
Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor. 325-330
Implementation of LDPC codecs for various communication standards
- Torben Brack, Matthias Alles, Timo Lehnigk-Emden, Frank Kienle, Norbert Wehn, Nicola E. L'Insalata, Francesco Rossi, Massimo Rovini, Luca Fanucci:
Low complexity LDPC code decoders for next generation standards. 331-336 - John Dielissen, Andries Hekstra:
Non-fractional parallelism in LDPC decoder implementations. 337-342 - Weihuang Wang, Gwan Choi:
Minimum-energy LDPC decoder for real-time mobile application. 343-348 - Zahid Khan, Tughrul Arslan:
Pipelined implementation of a real time programmable encoder for low density parity check code on a reconfigurable instruction cell architecture. 349-354 - Claudio Mucci, Luca Vanzolini, Fabio Campi, Mario Toma:
Interactive presentation: Implementation of AES/Rijndael on a dynamically reconfigurable architecture. 355-360
Testing NoCs
- Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi:
Using the inter- and intra-switch regularity in NoC switch testing. 361-366 - Kim Petersén, Johnny Öberg:
Toward a scalable test methodology for 2D-mesh Network-on-Chips. 367-372 - Oussama Laouamri, Chouki Aktouf:
Remote testing and diagnosis of System-on-Chips using network management frameworks. 373-378
Synthesis at system and architectural levels
- Qubo Hu, Arnout Vandecappelle, Per Gunnar Kjeldsberg, Francky Catthoor, Martin Palkovic:
Fast memory footprint estimation based on maximal dependency vector calculation. 379-384 - Hongwei Zhu, Ilie I. Luican, Florin Balasa:
Mapping multi-dimensional signals into hierarchical memory organizations. 385-390 - Srikanth Kurra, Neeraj Kumar Singh, Preeti Ranjan Panda:
The impact of loop unrolling on controller delay in high level synthesis. 391-396 - Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid:
Clock-frequency assignment for multiple clock domain systems-on-a-chip. 397-402 - Siddharth Garg, Diana Marculescu:
Interactive presentation: System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs. 403-408 - Michael Glaß, Martin Lukasiewycz, Thilo Streichert, Christian Haubelt, Jürgen Teich:
Interactive presentation: Reliability-aware system synthesis. 409-414
Analogue and mixed-signal design and characterization
- Pengbo Sun, Ying Wei, Alex Doboli:
Flexibility-oriented design methodology for reconfigurable DeltaSigma modulators. 415-420 - Gianvito Matarrese, Cristoforo Marzocca, Francesco Corsi, Stefano D'Amico, Andrea Baschirotto:
Experimental validation of a tuning algorithm for high-speed filters. 421-426 - Hamed Aminzadeh, Mohammad Danaie, Reza Lotfi:
Design of high-resolution MOSFET-only pipelined ADCs with digital calibration. 427-432 - Jafar Savoj, Ali-Azam Abbasfar, Amir Amirkhany, Bruno W. Garlepp, Mark A. Horowitz:
A new technique for characterization of digital-to-analog converters in high-speed systems. 433-438
Should you trust the surgeon or the family doctor?
- Marco Casale-Rossi, Andrzej J. Strojwas, Robert C. Aitken, Antun Domic, Carlo Guardiani, Philippe Magarshack, Douglas Pattullo, Joseph Sawicki:
DFM/DFY: should you trust the surgeon or the family doctor? 439-442
Automatic synthesis of computation intensive application specific circuits
- Ajay Kumar Verma, Paolo Ienne:
Automatic synthesis of compressor trees: reevaluating large counters. 443-448 - María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida:
Area optimization of multi-cycle operators in high-level synthesis. 449-454 - Maciej J. Ciesielski, Serkan Askar, Daniel Gomez-Prado, Jérémie Guillot, Emmanuel Boutillon:
Data-flow transformations using Taylor expansion diagrams. 455-460 - Yee Jern Chong, Sri Parameswaran:
Automatic application specific floating-point unit generation. 461-466 - Mario Schölzel:
Interactive presentation: Time-constrained clustering for DSE of clustered VLIW-ASP. 467-472
Embedded tutorial
- Applications for ubiquitous computing and communications. 473
Automotive
- Matthias Krause, Oliver Bringmann, André Hergenhan, Gökhan Tabanoglu, Wolfgang Rosenstiel:
Timing simulation of interconnected AUTOSAR software-components. 474-479 - Sergio Saponara, Esa Petri, Marco Tonarelli, Iacopo Del Corona, Luca Fanucci:
FPGA-based networking systems for high data-rate and reliable in-vehicle communications. 480-485 - Francesco D'Ascoli, Francesco Iozzi, Corrado Marino, Massimiliano Melani, Marco Tonarelli, Luca Fanucci, A. Giambastiani, Alessandro Rocchi, Marco De Marinis:
Low-g accelerometer fast prototyping for automotive applications. 486-491 - Riccardo Mariani, Gabriele Boschi, Federico Colucci:
Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508. 492-497 - Christopher Claus, Johannes Zeppenfeld, Florian Helmut Müller, Walter Stechele:
Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system. 498-503 - Patrick Popp, Marco Di Natale, Paolo Giusto, Sri Kanajan, Claudio Pinello:
Interactive presentation: Towards a methodology for the quantitative evaluation of automotive architectures. 504-509
Test generation for diagnosis, scan testing and advanced memory fault models
- Yu Huang:
Dynamic learning based scan chain diagnosis. 510-515 - Ozgur Sinanoglu, Philip Schremmer:
Diagnosis, modeling and tolerance of scan chain hold-time violations. 516-521 - Irith Pomeranz, Sudhakar M. Reddy:
On test generation by input cube avoidance. 522-527 - Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Slow write driver faults in 65nm SRAM technology: analysis and March test solution. 528-533 - V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. 534-539 - Kunal P. Ganeshpure, Sandip Kundu:
Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults. 540-545
Future design challenges
- Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie:
Temperature-aware NBTI modeling and the impact of input vector control on performance degradation. 546-551 - Tao Xu, Krishnendu Chakrabarty:
A cross-referencing-based droplet manipulation method for high-throughput and pin-constrained digital microfluidic arrays. 552-557 - Zeljko Zilic, Katarzyna Radecka, Ali Kazamiphur:
Reversible circuit technology mapping from non-reversible specifications. 558-563 - Nicholas H. Zamora, Jung-Chun Kao, Radu Marculescu:
Distributed power-management techniques for wireless network video systems. 564-569 - Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli:
Interactive presentation: Improving the fault tolerance of nanometric PLA designs. 570-575 - Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. 576-581
Application-specific architectures
- Seok-Won Seong, Prabhat Mishra:
An efficient code compression technique using application-aware bitmask and dictionary selection methods. 582-587 - Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar:
Optimizing instruction-set extensible processors under data bandwidth constraints. 588-593 - Juan Hamers, Lieven Eeckhout:
Resource prediction for media stream decoding. 594-599 - JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally:
Register pointer architecture for efficient embedded processors. 600-605 - Sven van Haastregt, Peter M. W. Knijnenburg:
Interactive presentation: Feasibility of combined area and performance optimization for superscalar processors using random search. 606-611 - Athanasios Milidonis, Nikolaos Alachiotis, Vasileios Porpodas, Haralambos Michail, Athanasios Kakarountas, Constantinos E. Goutis:
Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy. 612-617
Technology and process aware low power circuit design
- Nikhil Jayakumar, Sunil P. Khatri:
An algorithm to minimize leakage through simultaneous input vector control and circuit modification. 618-623 - Meeta Sharma Gupta, Jarod L. Oatley, Russ Joseph, Gu-Yeon Wei, David M. Brooks:
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network. 624-629 - Nilanjan Banerjee, Georgios Karakonstantis, Kaushik Roy:
Process variation tolerant low power DCT architecture. 630-635 - Yan Lin, Lei He:
Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction. 636-641
Hardware implementation of MPSoCs and NoCs architectures
- André C. Nácul, Francesco Regazzoni, Marcello Lajolo:
Hardware scheduling support in SMP architectures. 642-647