VTS 2006: Berkeley, CA, USA

Introduction

Session 1A: Delay Testing I

Session 1B: High Speed Interconnect Test

Session 1C - IP Session: Reliability Screening Methods for High-Performance Processors in Advanced Technologies

Session 2A: Heat and Power Issues in Test

Session 2B: Test Quality

Session 2C - IP Session: Scan Compression: Techniques, Tradeoffs and Entitlement

Session 3A: IP Protection and Interconnect Testing

Session 3B: Flash and Memory Testing

Session 3C - IP Session: Nanometer IC Testing: Perspective from Foundries

Session 4A: Yield Analysis

Session 4B - New Topic Session: Emerging Nanoelectronic Devices for High-Speed, Low-Power Applications

Session 4C - IP Session: TRP in Action: Embedded Instrumentation in FPGAs

Session 5A: - Special Session: The Future of DFT Sector: Point Tools or Integrated Solutions

Session 5B - Special Session: Elevator Talks

Session 5C - Embedded Tutorial: Functional ATPG

Session 6A: Test Generation and Test Flows

Session 6B: IDDQ, MEMS, and Wireless Testing

Session 6C - IP Session: Test Strategies of Leading Edge SoCs

Session 7A: Designing Robust CMOS and Nanoelectronics

Session 7B: RF Testing

Session 7C - IP Sessin: High Test Parallelism, Throughput and Quality at a Low Cost: Which Test Cells and Which Partitioning of Test Resources Can Enable All This?

Session 8A: Test Size Reductions

Session 8B: Transistor Level Diagnosis

Session 8C - IP Session: Soft Error Impact on Modern Systems

Session 9A - Panel Session: Real-Time Volume Diagnostics: Requirements and Challenges

Session 9B - Special Sesion: Doctoral Thesis Award

Session 9C - Panel Session: Three Questions to Oracle

Session 10A: Delay Testing II

Session 10B: Analog Test

Session 10C - IP Session: System-in-Package Design and Test Practices

Session 11A: Delay Testing III

Session 11B: Nanoscale Testing

Session 11C - IP Session: Impact of Variations on Designs and Test

Session 12A: Scan Based Diagnosis

Session 12B: Mixed Signal Test

Session 12C - IP Session: Making the (Yield) Difference: DFY/DFM

Session 13A: Embedded Tutorial: Silicon Debug Challenges for Nanometer Designs

Session 13B - Hot Topic Session: Signal Integrity: How Can It be Designed into Multiprocessor Platforms, Systems On-Chip, and Systems in-Package?

Session 13C - Panel Session: Changing Role of Test: Is ATE Ready?

a service of Schloss Dagstuhl - Leibniz Center for Informatics