"Functional test generation for delay faults in combinational circuits."

Irith Pomeranz, Sudhakar M. Reddy (1998)

> Home

Details and statistics

DOI: 10.1145/290833.290845

access: closed

type: Journal Article

metadata version: 2018-11-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/todaes/PomeranzR98
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/todaes/PomeranzR98
Irith Pomeranz, Sudhakar M. Reddy:
Functional test generation for delay faults in combinational circuits. ACM Trans. Design Autom. Electr. Syst. 3(2): 231-248 (1998)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.