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ORCIDICCAD 2003: San Jose, California, USA
- 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003. IEEE Computer Society / ACM 2003, ISBN 1-58113-762-1
- Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
Adapative Error Protection for Energy Efficiency. 2-7 - Ruibing Lu, Cheng-Kok Koh:
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. 8-12 - Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao:
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. 13-20 - Vishnu Swaminathan, Krishnendu Chakrabarty:
Generalized Network Flow Techniques for Dynamic Voltage Scaling in Hard Real-Time Systems. 21-25 - Shaoxiong Hua, Gang Qu:
Approaching the Maximum Energy Saving on Embedded Systems with Multiple Voltages. 26-29 - Le Yan, Jiong Luo, Niraj K. Jha:
Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems. 30-38 - Qi Wang, Sumit Roy:
RTL Power Optimization with Gate-Level Accuracy. 39-45 - Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. 46-53 - Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh:
Achieving Design Closure Through Delay Relaxation Parameter. 54-57 - Brian Swahn, Soha Hassoun:
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading. 58-65 - Hua Xiang, Xiaoping Tang, Martin D. F. Wong
:
Bus-Driven Floorplanning. 66-73 - Peter G. Sassone, Sung Kyu Lim:
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning. 74-80 - Cristinel Ababei, Kia Bazargan:
Placement Method Targeting Predictability Robustness and Performance. 81-85 - Brent Goplen, Sachin S. Sapatnekar:
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach. 86-90 - Ozgur Sinanoglu, Alex Orailoglu:
Partial Core Encryption for Performance-Efficient Test of SOCs. 91-94 - Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty:
TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers. 95-99 - Yu Xia, Malgorzata Chrzanowska-Jeske, Benyi Wang, Marcin Jeske:
Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints. 100-106 - Alberto García Ortiz, Lukusa D. Kabulepa, Tudor Murgan, Manfred Glesner:
Moment-Based Power Estimation in Very Deep Submicron Technologies. 107-112 - Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir:
IDAP: A Tool for High Level Power Estimation of Custom Array Structures. 113-119 - D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Murat R. Becer, Alexandre Ardelea, A. Patel:
SOI Transistor Model for Fast Transient Simulation. 120128 - Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri:
Design and CAD Challenges in sub-90nm CMOS Technologies. 129-137 - In-Cheol Park, Se-Hyeon Kang, Yongseok Yi:
Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation. 138-141 - Jun Yuan, Carl Pixley, Adnan Aziz, Ken Albin:
A Framework for Constrained Functional Verification. 142-145 - Yunshan Zhu, James H. Kukula:
Generator-based Verification. 146-153 - Alan J. Hu, Jeremy Casas, Jin Yang:
Efficient Generation of Monitor Circuits for GSTE Assertion Graphs. 154-160 - Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail:
Weibull Based Analytical Waveform Model. 161-168 - Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera:
Equivalent Waveform Propagation for Static Timing Analysis. 169-175 - Rubil Ahmadi, Farid N. Najm:
Timing Analysis in Presence of Power Supply and Ground Voltage Variations. 176-183 - Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda:
Vectorless Analysis of Supply Noise Induced Delay Variation. 184-192 - Guilin Chen, Mahmut T. Kandemir, A. Nadgir, Ugur Sezer:
Array Composition and Decomposition for Optimizing Embedded Applications. 193-196 - Junhyung Um, Taewhan Kim:
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design. 197-200 - Jinfeng Liu, Pai H. Chou:
Energy Optimization of Distributed Embedded Processors by Combined Data Compression and Functional Partitioning. 201-208 - Ying Zhang, Krishnendu Chakrabarty, Vishnu Swaminathan:
Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded Systems. 209-214 - Chuan Lin, Hai Zhou:
Retiming for Wire Pipelining in System-On-Chip. 215-220 - Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu:
Retiming with Interconnect and Gate Delay. 221-226 - Ruibing Lu, Cheng-Kok Koh:
Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels. 227-231 - Stephan Held, Bernhard Korte, Jens Maßberg, Matthias Ringe, Jens Vygen:
Clock Scheduling and Clocktree Construction for High Performance ASICS. 232-240 - Guido Stehr, Michael Pronath, Frank Schenkel, Helmut E. Graeb, Kurt Antreich:
Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification. 241-246 - Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
A Generalized Method for Computing Oscillator Phase Noise Spectra. 247-250 - Fabrice Veersé:
Efficient Iterative Time Preconditioners for Harmonic Balance RF Circuit Simulation. 251-255 - Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller:
Fredkin/Toffoli Templates for Reversible Logic Synthesis. 256-261 - Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky:
Evaluation of Placement Techniques for DNA Probe Array Layout. 262-269 - S. K. De, Narayan R. Aluru:
Physical And Reduced-Order Dynamic Analysis of MEMS. 270-274 - Claire Fang Fang, Rob A. Rutenbar, Tsuhan Chen:
Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs. 275-282 - Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
A Scalable Application-Specific Processor Synthesis Methodology. 283-290 - Newton Cheung, Sri Parameswaran, Jörg Henkel:
INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors. 291-298 - Tony F. Chan, Jason Cong, Tim Kong, Joseph R. Shinnerl, Kenton Sze:
An Enhanced Multilevel Algorithm for Circuit Placement. 299-306 - Ameya R. Agnihotri, Mehmet Can Yildiz, Ateen Khatkhate, Ajita Mathur, Satoshi Ono, Patrick H. Madden:
Fractional Cut: Improved Recursive Bisection Placement. 307-310 - Saurabh N. Adya, Igor L. Markov, Paul Villarrubia:
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis. 311-319 - Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng:
SATORI - A Fast Sequential SAT Engine for Circuits. 320-325 - Cong Liu, Andreas Kuehlmann, Matthew W. Moskewicz:
CAMA: A Multi-Valued Satisfiability Solver. 326-333 - Chao Wang, Gary D. Hachtel, Fabio Somenzi:
The Compositional Far Side of Image Computation. 334-341 - Arijit Ghosh, Tony Givargis:
Cache Optimization For Embedded Processor Cores: An Analytical Approach. 342-347 - Diana Marculescu, Nicholas H. Zamora, Phillip Stanley-Marbell, Radu Marculescu:
Fault-Tolerant Techniques for Ambient Intelligent Distributed Systems. 348-355 - Rami Beidas, Jianwen Zhu:
Performance Efficiency of Context-Flow System-on-Chip Platform. 356-362 - Won Namgoong, Jongrit Lerdworatawee:
Amplification of Ultrawideband Signals. 363-366 - Mohammad Taherzadeh-Sani, Reza Lotfi, Omid Shoaei:
A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline ADCs. 367-370 - Reza Lotfi, Mohammad Taherzadeh-Sani, M. Yaser Azizi, Omid Shoaei:
Systematic Design for Power Minimization of Pipelined Analog-to-Digital Converters. 371-374 - Dean Liu, Stefanos Sidiropoulos, Mark Horowitz:
A Framework for Designing Reusable Analog Circuits. 375-381 - Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee:
A Fast Crosstalk- and Performance-Driven Multilevel Routing System. 382-387 - Seokjin Lee, Yongseok Cheon, Martin D. F. Wong:
A Min-Cost Flow Based Detailed Router for FPGAs. 388-393 - Muhammet Mustafa Ozdal, Martin D. F. Wong:
Length-Matching Routing for High-Speed Printed Circuit Boards. 394-400 - Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu:
Analytical Bound for Unwanted Clock Skew due to Wire Width Variation. 401-407 - Chao Wang, Bing Li, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi:
Improving Ariadneýs Bundle by Following Multiple Threads in Abstraction Refinement. 408-415 - Aarti Gupta, Malay K. Ganai, Zijiang Yang, Pranav Ashar:
Iterative Abstraction using SAT-based BMC with Proof Analysis. 416-423 - Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda:
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. 424-432 - Gérard Berry, Michael Kishinevsky, Satnam Singh:
System Level Design and Verification Using a Synchronous Language. 433-440 - Alper Demir:
Noise Analysis for Optical Fiber Communication Systems. 441-445 - Joel R. Phillips, João Afonso, Arlindo L. Oliveira, Luís Miguel Silveira:
Analog Macromodeling using Kernel Methods. 446-453 - Peng Li, Xin Li, Yang Xu, Lawrence T. Pileggi:
A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits. 454-462 - Wonjoon Choi, Kia Bazargan:
Incremental Placement for Timing Optimization. 463-466 - Huaiyu Xu, Maogang Wang, Bo-Kyung Choi, Majid Sarrafzadeh:
A Trade-off Oriented Placement Tool. 467-471 - Jason Cong, Michail Romesis, Min Xie:
Optimality and Stability Study of Timing-Driven Placement Algorithms. 472-479 - R. Iris Bahar, Joseph L. Mundy, Jie Chen:
A Probabilistic-Based Design Methodology for Nanoscale Computation. 480-486 - Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy:
Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation. 487-490 - Jiayong Le, Lawrence T. Pileggi, Anirudh Devgan:
Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics. 491-496 - Santanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian M. Ionescu:
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits. 497-503 - Ali Iranli, Hanif Fatemi, Massoud Pedram:
A Game Theoretic Approach to Dynamic Energy Minimization in Wireless Transceivers. 504-509 - Girish Varatkar, Radu Marculescu:
Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization. 510-517 - Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel:
LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches. 518-522 - Peter Petrov, Alex Orailoglu:
Compiler-Based Register Name Adjustment for Low-Power Embedded Processors. 523-528 - Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason Cong:
Gradual Relaxation Techniques with Applications to Behavioral Synthesis. 529-535 - Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang:
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. 536-543 - Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel:
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis. 544-550 - Pallav Gupta, Lin Zhong, Niraj K. Jha:
A High-level Interconnect Power Model for Design Space Exploration. 551-559 - Vishal Khandelwal, Azadeh Davoodi, Akash Nanavati, Ankur Srivastava:
A Probabilistic Approach to Buffer Insertion. 560-567 - Giuseppe S. Garcea, N. P. van der Meijs, Ralph H. J. M. Otten:
Simultaneous Analytic Area and Power Optimization for Repeater Insertion. 568-573 - Weiping Liao, Lei He:
Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion. 574-580 - Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng:
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing. 581-587 - Michael Nicolaidis, Nadir Achouri, Slimane Boutobza:
Dynamic Data-bit Memory Built-In Self- Repair. 588-594 - Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu:
FAME: A Fault-Pattern Based Memory Failure Analysis Framework. 595-598 - Bai Hong Fang, Qiang Xu, Nicola Nicolici:
Hardware/Software Co-testing of Embedded Memories in Complex SOCs. 599-606 - Anirudh Devgan, Chandramouli V. Kashyap:
Block-based Static Timing Analysis with Uncertainty. 607-614 - Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw:
AU: Timing Analysis Under Uncertainty. 615-620 - Hongliang Chang, Sachin S. Sapatnekar:
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal. 621-626 - Nam Sung Kim, David T. Blaauw, Trevor N. Mudge:
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches. 627-632 - Phillip Stanley-Marbell, Diana Marculescu:
Dynamic Fault-Tolerance and Metrics for Battery Powered, Failure-Prone Systems. 633-640 - Krishna Sekar, Kanishka Lahiri, Sujit Dey:
Dynamic Platform Management for Configurable Platform-Based System-on-Chips. 641-649 - Sheldon X.-D. Tan:
A General S-Domain Hierarchical Network Reduction Algorithm. 650-657 - Bernard N. Sheehan:
Branch Merge Reduction of RLCM Networks. 658-664 - Yannick L. Le Coz, Dhivya Krishna, Dusan M. Petranovic, William M. Loh, Peter Bendix:
A Sum-over-Paths Impulse-Response Moment-Extraction Algorithm for IC-Interconnect Networks: Verification, Coupled RC Lines. 665-671 - Bozena Kaminska, Karim Arabi:
Mixed Signal DFT: A Concise Overview. 672-680 - Puneet Gupta, Andrew B. Kahng:
Manufacturing-Aware Physical Design. 681-688 - Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown:
A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. 689-692 - Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Hsien-Hsin S. Lee:
Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level. 693-700 - Julien Lamoureux, Steven J. E. Wilton:
On the Interaction Between Power-Aware FPGA CAD Algorithms. 701-708 - Alan Mishchenko, Robert K. Brayton:
A Theory of Non-Deterministic Networks. 709-717 - Yongseok Cheon, Seokjin Lee, Martin D. F. Wong:
Stable Multiway Circuit Partitioning for ECO. 718-725 - Navaratnasothie Selvakkumaran, George Karypis:
Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization. 726-733 - Jianhua Liu, Shuo Zhou, Haikun Zhu, Chung-Kuan Cheng:
An Algorithmic Approach for Generic Parallel Adders. 734-740 - Lei Yang, Chuanjin Richard Shi:
FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits. 741-747 - Abhishek Singh, Jitin Tharian, Jim Plusquellic:
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis. 748-753 - Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma:
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage. 754-759 - Aman Kokrady, C. P. Ravikumar:
Static Verification of Test Vectors for IR Drop Failure. 760-764 - Rahul Kundu, R. D. (Shawn) Blanton:
ATPG for Noise-Induced Switch Failures in Domino Logic. 765-769 - Imad A. Ferzli, Farid N. Najm:
Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations. 770-777 - Alessandra Nardi, Haibo Zeng, Joshua L. Garrett, Luca Daniel, Alberto L. Sangiovanni-Vincentelli:
A Methodology for the Computation of an Upper Bound on Nose Current Spectrum of CMOS Switching Activity. 778-785 - Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen:
SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation. 786-792 - Zhao Li, Chuanjin Richard Shi:
SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects. 793-800 - Kaushik Ravindran, Andreas Kuehlmann, Ellen Sentovich:
Multi-Domain Clock Skew Scheduling. 801-808 - Shih-Hsu Huang, Yow-Tyng Nieh:
Clock Period Minimization of Non-Zero Clock Skew Circuits. 809-812 - Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Minimum-Area Sequential Budgeting for FPGA. 813-817 - Josep Carmona, Jordi Cortadella:
ILP Models for the Synthesis of Asynchronous Control Circuits. 818-826 - Traianos V. Yioultsis, Anne Woo, Andreas C. Cangellaris:
Passive Synthesis of Compact Frequency-Dependent Interconnect Models via Quadrature Spectral Rules. 827-834 - Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen:
Analytic Modeling of Interconnects for Deep Sub-Micron Circuits. 835-842 - Ben Song, Zhenhai Zhu, John D. Rockway, Jacob K. White:
A New Surface Integral Formulation For Wideband Impedance Extraction of 3-D Structures. 843-847 - Yu Cao, Xiaodong Yang, Xuejue Huang, Dennis Sylvester:
Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis. 848-854 - Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer:
On Compacting Test Response Data Containing Unknown Values. 855-862 - C. V. Krishna, Nur A. Touba:
Adjustable Width Linear Combinational Scan Vector Decompression. 863-866 - Irith Pomeranz, Sudhakar M. Reddy:
On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic. 867-873 - Rajesh K. Gupta, Sandy Irani, Sandeep K. Shukla:
Formal Methods for Dynamic Power Management. 874-882 - Jason Cong, Tim Kong, Joseph R. Shinnerl, Min Xie, Xin Yuan:
Large-Scale Circuit Placement: Gap and Promise. 883-890 - Maogang Wang, Abhishek Ranjan, Salil Raje:
Multi-Million Gate FPGA Physical Design Challenges. 891-899 - Aseem Agarwal, David T. Blaauw, Vladimir Zolotov:
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations. 900-907 - Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera:
A Statistical Gate-Delay Model Considering Intra-Gate Variability. 908-913 - Aseem Agarwal, David T. Blaauw, Vladimir Zolotov:
Statistical Clock Skew Analysis Considering Intra-Die Process Variations. 914-921
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