DATE 2006: Munich, Germany

• 
  Georges G. E. Gielen:
  Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006. European Design and Automation Association, Leuven, Belgium 2006, ISBN 3-9810801-1-4

Keynote Addresses

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  René Penning de Vries:
  EDA challenges in the converging application world. 1
• 
  Walden C. Rhines:
  Sociology of design and EDA. 2

Allocation and scheduling for MPSoCs and NoCs

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  Martino Ruggiero, Alessio Guerri, Davide Bertozzi, Francesco Poletti, Michela Milano:
  Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip. 3-8
• 
  Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
  Efficient link capacity and QoS design for network-on-chip. 9-14
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  Stefano Bertozzi, Andrea Acquaviva, Davide Bertozzi, Antonio Poggiali:
  Supporting task migration in multi-processor systems-on-chip: a feasibility study. 15-20

Power grid and large interconnect network analysis

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  Xuan Zeng, Lihong Feng, Yangfeng Su, Wei Cai, Dian Zhou, Charles C. Chiang:
  Time domain model order reduction by wavelet collocation method. 21-26
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  Quming Zhou, Kai Sun, Kartik Mohanram, Danny C. Sorensen:
  Large power grid analysis using domain decomposition. 27-32
• 
  J. Balachandran, Steven Brebels, Geert Carchon, Tomas Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne:
  Analysis and modeling of power grid transmission lines. 33-38
• 
  Baohua Wang, Pinaki Mazumder:
  A logarithmic full-chip thermal analysis algorithm based on multi-layer Green's function. 39-44

Interactive presentation

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  Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai:
  Large scale RLC circuit analysis using RLCG-MNA formulation. 45-46

On-line testing and fault tolerance

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  Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff:
  Soft delay error analysis in logic circuits. 47-52
• 
  Tsu-Wei Tseng, Jin-Fu Li, Da-Ming Chang:
  A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap. 53-58
• 
  Daniele Rossi, Carlo Steiner, Cecilia Metra:
  Analysis of the impact of bus implemented EDCs on on-chip SSN. 59-64
• 
  Nektarios Kranitis, Andreas Merentitis, N. Laoutaris, George Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos, Constantin Halatsis:
  Optimal periodic testing of intermittent faults in embedded pipelined processor applications. 65-70

Interactive presentation

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  Sobeeh Almukhaizim, Yiorgos Makris:
  Berger code-based concurrent error detection in asynchronous burst-mode machines. 71-72

Chip design records

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  Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner:
  Two-phase resonant clocking for ultra-low-power hearing aid applications. 73-78
• 
  Se-Joong Lee, Kwanho Kim, Hyejung Kim, Namjun Cho, Hoi-Jun Yoo:
  A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes. 79-80
• 
  Cristiano Niclass, Maximilian Sergio, Edoardo Charbon:
  A single photon avalanche diode array fabricated in deep-submicron CMOS technology. 81-86

Model based design and test

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  Jon Friedman:
  MATLAB/Simulink for automotive systems design. 87-88
• 
  Mirko Conrad, Heiko Dörr:
  Model-based development of in-vehicle software. 89-90
• 
  Klaus Lamberg:
  Model-based testing of automotive electronics. 91
• 
  John Heighton:
  Designing signal processing systems for FPGAs. 92
• 
  Yves Vanderperren, Wim Dehaene:
  From UML/SysML to Matlab/Simulink: current state and future perspectives. 93

Transaction level modelling based validation

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  Emmanuel Viaud, François Pêcheux, Alain Greiner:
  An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles. 94-99
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  Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Damien Lyonnard, Chuck Pilkington:
  Exploiting TLM and object introspection for system-level simulation. 100-105
• 
  Ali Habibi, Sofiène Tahar, Amer Samarah, Donglin Li, Otmane Aït Mohamed:
  Efficient assertion based verification using TLM. 106-111
• 
  Joseph D'Errico, Wei Qin:
  Constructing portable compiled instruction-set simulators: an ADL-driven approach. 112-117

Application-specific network on chip design

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  Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli:
  A methodology for mapping multiple use-cases onto networks on chips. 118-123
• 
  Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo:
  Contrasting a NoC and a traditional interconnect fabric with layout awareness. 124-129
• 
  Krishnan Srinivasan, Karam S. Chatha:
  A low complexity heuristic for design of custom network-on-chip architectures. 130-135

Interactive presentation

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  Thilo Pionteck, Carsten Albrecht, Roman Koch:
  A dynamically reconfigurable packet-switched network-on-chip. 136-137

Methods and tools for systematic analogue design

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  Vahid Majidzadeh, Omid Shoaei:
  Arbitrary design of high order noise transfer function for a novel class of reduced-sample-rate sigma-delta-pipeline ADCs. 138-143
• 
  Mohammad Yavari, Omid Shoaei, Ángel Rodríguez-Vázquez:
  Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation. 144-149
• 
  Gerd Vandersteen, Stephane Bronckers, Petr Dobrovolný, Yves Rolain:
  Systematic stability-analysis method for analog circuits. 150-155
• 
  Hui Zhang, Yang Zhao, Alex Doboli:
  ALAMO: an improved alpha-space based methodology for modeling process parameter variations in analog circuits. 156-161

Interactive presentation

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  Vito Giannini, Pierluigi Nuzzo, Fernando De Bernardinis, Jan Craninckx, Boris Come, Stefano D'Amico, Andrea Baschirotto:
  A synthesis tool for power-efficient base-band filter design. 162-163

Soft error analysis and concurrent testing

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  Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester:
  An efficient static algorithm for computing the soft error rates of combinational circuits. 164-169
• 
  Martin Omaña, José Manuel Cazeaux, Daniele Rossi, Cecilia Metra:
  Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. 170-175
• 
  Udo Krautz, Matthias Pflanz, Christian Jacobi, Hans-Werner Tast, Kai Weber, Heinrich Theodor Vierhaus:
  Evaluating coverage of error detection logic for soft errors using formal methods. 176-181
• 
  N. Ignat, Bogdan Nicolescu, Yvon Savaria, Gabriela Nicolescu:
  Soft-error classification and impact analysis on real-time operating systems. 182-187

System design records

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  H. Shrikumar:
  40Gbps de-layered silicon protocol engine for TCP record. 188-193
• 
  Amilcar do Carmo Lucas, Sven Heithecker, Peter Rüffer, Rolf Ernst, Holger Rückert, Gerhard Wischermann, Karin Gebel, Reinhard Fach, Wolfgang Huther, Stefan Eichner, Gunter Scheller:
  A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications. 194-199
• 
  Torben Brack, Frank Kienle, Norbert Wehn:
  Disclosing the LDPC code decoder design space. 200-205

Application-specific architectures

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  Robert G. Dimond, Oskar Mencer, Wayne Luk:
  Automating processor customisation: optimised memory access and resource sharing. 206-211
• 
  Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi:
  Automatic identification of application-specific functional units with architecturally visible storage. 212-217
• 
  Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay K. Verma:
  Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. 218-223
• 
  Ahmad Zmily, Christos Kozyrakis:
  Simultaneously improving code size, performance, and energy in embedded processors. 224-229

System level performance analysis

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  Gunar Schirner, Rainer Dömer:
  Quantitative analysis of transaction level models for the AMBA bus. 230-235
• 
  Simon Künzli, Francesco Poletti, Luca Benini, Lothar Thiele:
  Combining simulation and formal methods for system-level performance analysis. 236-241
• 
  Alexander Viehl, Timo Schönwald, Oliver Bringmann, Wolfgang Rosenstiel:
  Formal performance analysis and simulation of UML/SysML models for ESL design. 242-247
• 
  Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf:
  Performance evaluation for system-on-chip architectures using trace-based transaction level simulation. 248-253

Hot topic - 'Network': the Next 'Big Idea' in design? network paradigms in systems, sensors, and silicon

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  Radu Marculescu, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli:
  Is "Network" the next "Big Idea" in design? 254-256

Advances in verification and synthesis for analogue design automation

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  Goran Frehse, Bruce H. Krogh, Rob A. Rutenbar:
  Verifying analog oscillator circuits using forward/backward abstraction refinement. 257-262
• 
  Ting Mei, Jaijeet S. Roychowdhury:
  Efficient AC analysis of oscillators using least-squares methods. 263-268
• 
  Trent McConaghy, Georges G. E. Gielen:
  Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns. 269-274
• 
  Ewout Martens, Georges G. E. Gielen:
  Top-down heterogeneous synthesis of analog and mixed-signal systems. 275-280

Interactive presentation

• 
  Jose A. Martinez, Steven P. Levitan, Donald M. Chiarulli:
  Nonlinear model order reduction using remainder functions. 281-282
• 
  Huiying Yang, Ranga Vemuri:
  Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis. 283-284

Advanced SoC test scheduling

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  Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty:
  Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. 285-290
• 
  Zhiyuan He, Zebo Peng, Petru Eles:
  Power constrained and defect-probability driven SoC test scheduling with test set partitioning. 291-296
• 
  Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara:
  Power-constrained test scheduling for multi-clock domain SoCs. 297-302
• 
  Chunsheng Liu, Zach Link, Dhiraj K. Pradhan:
  Reuse-based test access and integrated test scheduling for network-on-chip. 303-308

Interactive presentation

• 
  Sandip Kundu:
  A design for failure analysis (DFFA) technique to ensure incorruptible signatures. 309-310

Design methodologies for emerging technologies

• 
  Pallav Gupta, Niraj K. Jha, Loganathan Lingappan:
  Test generation for combinational quantum cellular automata (QCA) circuits. 311-316
• 
  Afshin Abdollahi, Massoud Pedram:
  Analysis and synthesis of quantum circuits by using quantum decision diagrams. 317-322
• 
  Fei Su, William L. Hwang, Krishnendu Chakrabarty:
  Droplet routing in the synthesis of digital microfluidic biochips. 323-328
• 
  Andrew J. Ricketts, Kevin M. Irick, Narayanan Vijaykrishnan, Mary Jane Irwin:
  Priority scheduling in digital microfluidics-based biochips. 329-334

Interactive presentation

• 
  Debayan Bhaduri, Sandeep K. Shukla, Deji Coker, Valerie E. Taylor, Paul S. Graham, Maya Gokhale:
  A hybrid framework for design and analysis of fault-tolerant architectures. 335-336
• 
  Jacob R. Minz, Somaskanda Thyagaraja, Sung Kyu Lim:
  Optical routing for 3D system-on-package. 337-338

Processor and memory design

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  Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest:
  Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors. 339-344
• 
  Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven:
  Compositional, efficient caches for a chip multi-processor. 345-350
• 
  Stijn Eyerman, Lieven Eeckhout, Koen De Bosschere:
  Efficient design space exploration of high performance embedded out-of-order processors. 351-356
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  Hans Vandierendonck, Philippe Manet, Jean-Didier Legat:
  Application-specific reconfigurable XOR-indexing to eliminate cache conflict misses. 357-362

Spatial and temporal mapping for reconfigurable computing

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  Minwook Ahn, Jonghee W. Yoon, Yunheung Paek, Yoonjin Kim, Mary Kiemb, Kiyoung Choi:
  A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures. 363-368
• 
  Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis:
  Compiler-driven FPGA-area allocation for reconfigurable computing. 369-374
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  Paulo Sérgio B. do Nascimento, Manoel Eusebio de Lima:
  Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures. 375-380
• 
  Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawam, Tughrul Arslan, Iain Lindsay:
  System-level scheduling on instruction cell based reconfigurable systems. 381-386

DFM/DFY design for manufacturability and yield

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  Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp:
  DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. 387-392

Analogue and mixed-signal design

• 
  Ying Wei, Hua Tang, Alex Doboli:
  Systematic methodology for designing reconfigurable Delta-Sigma modulator topologies for multimode communication systems. 393-398
• 
  Mohammad Yavari, Omid Shoaei, Ángel Rodríguez-Vázquez:
  Double-sampling single-loop sigma-delta modulator topologies for broadband applications. 399-404
• 
  Kambiz K. Moez, Mohamed I. Elmasry:
  A 10-GHz 15-dB four-stage distributed amplifier in 0.18 µm CMOS process. 405-409

Interactive presentation

• 
  José C. García, Juan A. Montiel-Nelson, Saeid Nooshabadi:
  Bootstrapped full-swing CMOS driver for low supply voltage operation. 410-411

Processor self-test and fault diagnosis

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  Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda:
  An effective technique for minimizing the cost of processor software-based diagnosis in SoCs. 412-417
• 
  Kai Yang, Kwang-Ting Cheng:
  Timing-reasoning-based delay fault diagnosis. 418-423
• 
  Yung-Chieh Lin, Kwang-Ting Cheng:
  Multiple-fault diagnosis based on single-fault activation and single-output observation. 424-429
• 
  Jun Zhou, Hans-Joachim Wunderlich:
  Software-based self-test of processors under power constraints. 430-435

Interactive presentation

• 
  Yu Huang, Keith Gallie:
  Diagnosis of defects on scan enable and clock trees. 436-437

Scheduling for real-time and energy

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  Hyeonjoong Cho, Binoy Ravindran, E. Douglas Jensen:
  Lock-free synchronization for dynamic embedded real-time systems. 438-443
• 
  Ernesto Wandeler, Alexander Maxiaguine, Lothar Thiele:
  Performance analysis of greedy shapers in real-time systems. 444-449
• 
  Rafik Henia, Rolf Ernst:
  Improved offset-analysis using multiple timing-references. 450-455
• 
  Zhijian Lu, Yan Zhang, Mircea R. Stan, John Lach, Kevin Skadron:
  Procrastinating voltage scheduling with discrete frequency sets. 456-461

System level modelling and simulation

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  Guang Yang, Xi Chen, Felice Balarin, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli:
  Communication and co-simulation infrastructure for heterogeneous system integration. 462-467
• 
  Torsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
  A SW performance estimation framework for early system-level-design using fine-grained instrumentation. 468-473
• 
  Víctor Reyes, Wido Kruijtzer, Tomás Bautista, Ghiath Alkadi, Antonio Núñez:
  A unified system-level modeling and simulation environment for MPSoC design: MPEG-4 decoder case study. 474-479

Interactive presentation

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  Martin Streubühr, Joachim Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch, Thomas Schlipf:
  Task-accurate performance modeling in SystemC for real-time multi-processor architectures. 480-481

Hot topic: system level design of SoC (4G wireless special day)

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  Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Olivier Benny, Damien Lyonnard, Bruno Lavigueur, David Lo:
  Distributed object models for multi-processor SoC's, with application to low-power multimedia wireless systems. 482-487
• 
  Tim Kogel, Matthew Braun:
  Virtual prototyping of embedded platforms for wireless and multimedia. 488-490
• 
  Luca Benini:
  Application specific NoC design. 491-495

Power-efficient hardware/software architectures

• 
  Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt Jr.:
  Automatic insertion of low power annotations in RTL for pipelined microprocessors. 496-501
• 
  Bren Mochocki, Kanishka Lahiri, Srihari Cadambi:
  Power analysis of mobile 3D graphics. 502-507
• 
  Nathaniel Pettis, Jason Ridenour, Yung-Hsiang Lu:
  Automatic run-time selection of power policies for operating systems. 508-513
• 
  Changjiu Xian, Yung-Hsiang Lu:
  Energy reduction by workload adaptation in a multi-process environment. 514-519

Interactive presentation

• 
  Jongsun Park, Jung Hwan Choi, Kaushik Roy:
  Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off. 520-521

Timing and noise analysis

• 
  Brock J. LaMeres, Sunil P. Khatri:
  Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission. 522-527
• 
  Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen:
  Statistical timing analysis with path reconvergence and spatial correlations. 528-532
• 
  Soroush Abbaspour, Hanif Fatemi, Massoud Pedram:
  Non-gaussian statistical interconnect timing analysis. 533-538
• 
  Shahin Nazarian, Massoud Pedram:
  Cell delay analysis based on rate-of-current change. 539-544

Interactive presentation

• 
  Frank Liu:
  A practical method to estimate interconnect responses to variabilities. 545-546

Test and reliability challenges in automotive microelectronics

• 
  Christian Sebeke, C. Jung, Klaus Harbich, S. Fuchs, J. Schwarz, Peter Göhner:
  Test and reliability challenges in automotive microelectronics. 547

Communication methods and networking in automotive systems

• 
  Sri Kanajan, Haibo Zeng, Claudio Pinello, Alberto L. Sangiovanni-Vincentelli:
  Exploring trade-off's between centralized versus decentralized automotive architectures using a virtual integration environment. 548-553
• 
  Thomas Weber:
  Management of complex automotive communication networks. 554-555
• 
  Andreas Herkersdorf, Walter Stechele:
  AutoVision: flexible processor architecture for video-assisted driving. 556
• 
  Klaus D. Müller-Glaser:
  Domain specific model driven design for automotive electronic control units. 557
• 
  Pascal Dégardins:
  Electric and electronic vehicle architecture assessment. 558
• 
  Patrick Leteinturier:
  Automotive semi-conductor trend & challenges. 559

System level modelling

• 
  Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-Taek Kim, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, Taewhan Kim:
  A systematic IP and bus subsystem modeling for platform-based system design. 560-564
• 
  Hiren D. Patel, Sandeep K. Shukla, Reinaldo A. Bergamaschi:
  Heterogeneous behavioral hierarchy for system level designs. 565-570
• 
  Patrick Schaumont, Sandeep K. Shukla, Ingrid Verbauwhede:
  Design with race-free hardware semantics. 571-576

Interactive presentation

• 
  Steffen Prochnow, Reinhard von Hanxleden:
  Comfortable modeling of complex reactive systems. 577-578
• 
  Waseem Ahmed, Doug Myers:
  Faster exploration of high level design alternatives using UML for better partitions. 579-580

Hot topic: architectures and NoC (4G wireles special day)

• 
  Rainer Leupers, Kingshuk Karuri, Stefan Kraemer, M. Pandey:
  A design flow for configurable embedded processors based on optimized instruction set extension synthesis. 581-586
• 
  Pablo Robelly, Hendrik Seidel, K. C. Chen, Gerhard P. Fettweis:
  Energy efficiency vs. programmability trade-off: architectures and design principles. 587-592
• 
  Andreas Burg, Moritz Borgmann, Markus Wenk, Christoph Studer, Helmut Bölcskei:
  Advanced receiver algorithms for MIMO wireless communications. 593-598

Keynote

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