DATE 2006:
Munich, Germany
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https://dblp.org/rec/conf/date/2006p Georges G. E. Gielen :
Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006. European Design and Automation Association, Leuven, Belgium 2006 , ISBN
3-9810801-1-4
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Allocation and scheduling for MPSoCs and NoCs
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Power grid and large interconnect network analysis
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On-line testing and fault tolerance
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Model based design and test
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https://dblp.org/rec/conf/date/Friedman06 Jon Friedman :
MATLAB/Simulink for automotive systems design. 87-88 share record
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Transaction level modelling based validation
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Wei Qin :
Constructing portable compiled instruction-set simulators: an ADL-driven approach. 112-117
Application-specific network on chip design
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Methods and tools for systematic analogue design
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https://dblp.org/rec/conf/date/MajidzadehS06 Vahid Majidzadeh ,
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Arbitrary design of high order noise transfer function for a novel class of reduced-sample-rate sigma-delta-pipeline ADCs. 138-143 share record
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https://dblp.org/rec/conf/date/ZhangZD06 Hui Zhang ,
Yang Zhao ,
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ALAMO: an improved alpha-space based methodology for modeling process parameter variations in analog circuits. 156-161
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Soft error analysis and concurrent testing
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https://dblp.org/rec/conf/date/Shrikumar06 H. Shrikumar :
40Gbps de-layered silicon protocol engine for TCP record. 188-193 export record
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https://dblp.org/rec/conf/date/LucasHRERWGFHES06 Amilcar do Carmo Lucas ,
Sven Heithecker ,
Peter Rüffer ,
Rolf Ernst ,
Holger Rückert ,
Gerhard Wischermann ,
Karin Gebel ,
Reinhard Fach ,
Wolfgang Huther ,
Stefan Eichner ,
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A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications. 194-199 share record
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System level performance analysis
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Hot topic - 'Network':
the Next 'Big Idea' in design? network paradigms in systems, sensors, and silicon
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https://dblp.org/rec/conf/date/McConaghyG06 Trent McConaghy ,
Georges G. E. Gielen :
Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns. 269-274 share record
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https://dblp.org/rec/conf/date/MartensE06
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https://dblp.org/rec/conf/date/YangV06 Huiying Yang ,
Ranga Vemuri :
Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis. 283-284
Advanced SoC test scheduling
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https://dblp.org/rec/conf/date/Kundu06 Sandip Kundu :
A design for failure analysis (DFFA) technique to ensure incorruptible signatures. 309-310
Design methodologies for emerging technologies
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Processor and memory design
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Spatial and temporal mapping for reconfigurable computing
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DFM/DFY design for manufacturability and yield
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Analogue and mixed-signal design
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https://dblp.org/rec/conf/date/WeiTD06 Ying Wei ,
Hua Tang ,
Alex Doboli :
Systematic methodology for designing reconfigurable Delta-Sigma modulator topologies for multimode communication systems. 393-398 share record
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Processor self-test and fault diagnosis
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https://dblp.org/rec/conf/date/Liu06 Frank Liu :
A practical method to estimate interconnect responses to variabilities. 545-546
Test and reliability challenges in automotive microelectronics
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Communication methods and networking in automotive systems
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https://dblp.org/rec/conf/date/KanajanZPS06 share record
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https://dblp.org/rec/conf/date/Weber06 Thomas Weber :
Management of complex automotive communication networks. 554-555 share record
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Doug Myers :
Faster exploration of high level design alternatives using UML for better partitions. 579-580
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