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ORCIDIEEE Transactions on Very Large Scale Integration Systems, Volume 27
Volume 27, Number 1, January 2019
- Scott Lerner
, Baris Taskin:
Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis. 1-10
- Ryuichi Enomoto, Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada:
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. 11-19 - Martin Omaña, Alessandro Fiore, Marco Mongitore, Cecilia Metra:
Fault-Tolerant Inverters for Reliable Photovoltaic Systems. 20-28 - Chun-Chi Chen, Chao-Lieh Chen, Yi Lin, Song-Quan You:
An All-Digital Time-Domain Smart Temperature Sensor With a Cost-Efficient Curvature Correction. 29-36 - Maryam Rezaei Khezeli, Mohammad Hossein Moaiyeri, Ali Jalali:
Comparative Analysis of Simultaneous Switching Noise Effects in MWCNT Bundle and Cu Power Interconnects in CNTFET-Based Ternary Circuits. 37-46 - Pan Xue, Yilei Shen, Dan Fang, Chenyang Wang, Haijun Shao, Ting Yi, Xiaoyang Zeng, Zhiliang Hong:
A 2-D Predistortion Based on Profile Inversion for Fully Digital Cartesian Transmitter. 47-56 - Jai-Ming Lin, You-Lun Deng, Szu-Ting Li, Bo-Heng Yu, Li-Yen Chang, Te-Wei Peng:
Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles. 57-68 - Ricardo Martins, Nuno Lourenço, Nuno Horta, Jun Yin, Pui-In Mak, Rui Paulo Martins:
Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications. 69-82 - Ned Bingham, Rajit Manohar:
QDI Constant-Time Counters. 83-91 - Jiwoong Choi, Boyeal Kim, Hyun Kim, Hyuk-Jae Lee:
A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace. 92-102 - Daniel Morrison, Dennis Delic, Mehmet Rasit Yuce, Jean-Michel Redoute:
Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications. 103-115 - Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso:
Dynamic Partial Reconfiguration of Customized Single-Row Accelerators. 116-125 - Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim:
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS. 126-137 - Sungju Ryu, Naebeom Park, Jae-Joon Kim:
Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator. 138-146 - Jae Young Hur:
Contiguity Representation in Page Table for Memory Management Units. 147-158 - Xunzhao Yin, Xiaoming Chen, Michael T. Niemier, Xiaobo Sharon Hu:
Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits. 159-172 - Jiangtao Xu, Wei Li, Kaiming Nie, Liqiang Han, Xiyang Zhao:
A Method to Reduce the Effect on Image Quality Caused by Resistance of Column Bus. 173-181 - Amir Bazrafshan, Mohammad Taherzadeh-Sani, Frederic Nabki:
An Analog LO Harmonic Suppression Technique for SDR Receivers. 182-192 - ByongChan Lim, Mark Horowitz:
An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification. 193-204 - Xu Fang, Yang Yu, Xiyuan Peng:
TSV Prebond Test Method Based on Switched Capacitors. 205-218 - Mi Zhou, Zhuochao Sun, Qiong Wei Low, Liter Siek:
Multiloop Control for Fast Transient DC-DC Converter. 219-228 - Longfei Wang, S. Karen Khatamifard, Ulya R. Karpuzcu, Selçuk Köse:
Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation. 229-242 - Chenchang Zhan, Guigang Cai, Wing-Hung Ki:
A Transient-Enhanced Output-Capacitor-Free Low-Dropout Regulator With Dynamic Miller Compensation. 243-247 - Amandeep Kaur, Deepak Mishra, Mukul Sarkar:
A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC. 248-252
Volume 27, Number 2, February 2019
- Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. 253-280 - Guillaume Renaud, Mamadou Diallo, Manuel J. Barragán, Salvador Mir:
Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs. 281-293 - Anindita Paul, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal:
CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency. 294-303 - Nicolas Laflamme-Mayer, Gilbert Kowarzyk, Yves Blaquière, Yvon Savaria, Mohamad Sawan:
A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration. 304-315 - Tomasz Kulej, Fabian Khateb, Luis Henrique de Carvalho Ferreira:
A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta-Sigma Modulator in 0.18-µm CMOS. 316-325 - Chih-Wen Lu, Ping-Yeh Yin, Mu-Yong Lin:
A 10-bit Two-Stage R-DAC With Isolating Source Followers for TFT-LCD and AMOLED Column-Driver ICs. 326-336 - Yang Zhang, Debajit Basak, Kong-Pang Pun:
Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI. 337-349 - Kshitij Bhardwaj, Steven M. Nowick:
A Continuous-Time Replication Strategy for Efficient Multicast in Asynchronous NoCs. 350-363 - Mohammad A. Usmani, Shahrzad Keshavarz, Eric Matthews, Lesley Shannon, Russell Tessier, Daniel E. Holcomb:
Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration. 364-375 - Shivani Bathla, Rahul M. Rao, Nitin Chandrachoodan:
A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits. 376-386 - Sara Choi, Hong Keun Ahn, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories. 387-397 - Pratheep Bondalapati, Won Namgoong:
Timing Jitter Distribution and Power Spectral Density of a Second-Order Bang-Bang Digital PLL With Transport Delay Using Fokker-Planck Equations. 398-406 - Chunyu Peng, Jiati Huang, Changyong Liu, Qiang Zhao, Songsong Xiao, Xiulong Wu, Zhiting Lin, Junning Chen, Xuan Zeng:
Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application. 407-415 - Md. Badruddoja Majumder, Md Sakib Hasan, Mesbah Uddin, Garrett S. Rose:
A Secure Integrity Checking System for Nanoelectronic Resistive RAM. 416-429 - Murali K. Rajendran, V. Priya, Shourya Kansal, Gajendranath Chowdary, Ashudeb Dutta:
A 100-mV-2.5-V Burst Mode Constant on-Time- Controlled Battery Charger With 92% Peak Efficiency and Integrated FOCV Technique. 430-443 - Zahi Moudallal, Farid N. Najm:
Power Scheduling With Active RC Power Grids. 444-457 - Qin Wang, Zechen Liu, Jianfei Jiang, Naifeng Jing, Weiguang Sheng:
A New Cellular-Based Redundant TSV Structure for Clustered Faults. 458-467 - Panagiotis Chaourani, Saul Rodriguez, Per-Erik Hellström, Ana Rusu:
Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines. 468-480 - Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector. 481-485 - Pedro Reviriego, Salvatore Pontarelli, Anees Ullah:
Error Detection and Correction in SRAM Emulated TCAMs. 486-490 - Elena Ioana Vatajelu, Giorgio Di Natale:
High-Entropy STT-MTJ-Based TRNG. 491-495 - Irith Pomeranz:
Test Compaction by Test Removal Under Transparent Scan. 496-500
Volume 27, Number 3, March 2019
- Cheng-En Hsieh, Shen-Iuan Liu:
A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient. 501-510 - Shaohan Liu, Dake Liu:
A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G. 511-523 - Liming Xiu, Xiangye Wei, Yuhai Ma:
A Full Digital Fractional-N TAF-FLL for Digital Applications: Demonstration of the Principle of a Frequency-Locked Loop Built on Time-Average-Frequency. 524-534 - Gaurav Saini, Maryam Shojaei Baghini:
A Generic Power Management Circuit for Energy Harvesters With Shared Components Between the MPPT and Regulator. 535-548 - Donkyu Baek, Naehyuck Chang:
Runtime Power Management of Battery Electric Vehicles for Extended Range With Consideration of Driving Time. 549-559 - Shubham Rai, Jens Trommer, Michael Raitza, Thomas Mikolajick, Walter M. Weber, Akash Kumar:
Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors. 560-572 - Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske:
Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization. 573-586 - Amard Afzalian, Hossein Miar Naimi, Massoud Dousti:
What Is the Maximum Achievable Oscillation Frequency in a Specified CMOS Process? 587-600 - Marko Simicic, Pieter Weckx, Bertrand Parvais, Philippe Roussel, Ben Kaczer, Georges G. E. Gielen:
Understanding the Impact of Time-Dependent Random Variability on Analog ICs: From Single Transistor Measurements to Circuit Simulations. 601-610 - Xiang Ge, Fan Yang, Hengliang Zhu, Xuan Zeng, Dian Zhou:
An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition. 611-623 - Haomiao Wang, Prabu Thiagaraj, Oliver Sinnen:
Harmonic-Summing Module of SKA on FPGA - Optimizing the Irregular Memory Accesses. 624-636 - Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs. 637-650 - Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jörg Henkel, Hossein Asadi:
Estimating and Mitigating Aging Effects in Routing Network of FPGAs. 651-664 - Zhiming Zhang, Laurent Njilla, Charles A. Kamhoua, Qiaoyan Yu:
Thwarting Security Threats From Malicious FPGA Tools With Novel FPGA-Oriented Moving Target Defense. 665-678 - Shinwoong Park, Sanjay Raman:
Analysis and Optimization of Multisection Capacitive DACs for Mixed-Signal Processing. 679-690 - Wael Dghais, Malek Souilem, Muhammad Alam:
Mixed-Signal Overclocked I/O Buffers Model Abstraction for Signal Integrity Assessment. 691-699 - Scott Lerner, Isikcan Yilmaz, Baris Taskin:
Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors. 700-710 - Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak:
Design and Optimization of Inductive-Coupling Links for 3-D-ICs. 711-723 - Daewoong Lee, Dongil Lee, Yong-Hun Kim, Lee-Sup Kim:
A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control. 724-728 - Arpan Thakkar, Srinivas Theertham, Peeyoosh Mirajkar, Sankaran Aniruddhan:
Techniques for Improved Continuous and Discrete Tuning Range in Millimeter-Wave VCOs. 729-733 - Mehrnaz Ahmadi, Sahand Salamat, Bijan Alizadeh:
A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs. 734-737 - Ausmita Sarker, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Hardware Constructions for Error Detection of Number-Theoretic Transform Utilized in Secure Cryptographic Architectures. 738-741 - Yuqi Wang, Amira Aouina, Hui Li, Ian O'Connor, Gabriela Nicolescu, Sébastien Le Beux:
Thermal-Aware Design Method for Laser Group Control in Nanophotonic Interconnects. 742-746
Volume 27, Number 4, April 2019
- Thinh Hung Pham, Phong Tran, Siew-Kei Lam:
High-Throughput and Area-Optimized Architecture for rBRIEF Feature Extraction. 747-756 - Tianchan Guan, Xiaoyang Zeng, Mingoo Seok:
Recursive Synaptic Bit Reuse: An Efficient Way to Increase Memory Capacity in Associative Memory. 757-768 - Duncan J. M. Moss, David Boland, Philip H. W. Leong:
A Two-Speed, Radix-4, Serial-Parallel Multiplier. 769-777 - Siyuan Xu, Benjamin Carrión Schäfer:
Toward Self-Tunable Approximate Computing. 778-789 - Dina M. Ellaithy, Magdy A. El-Moursy, Amal Zaki, Abdelhalim Zekry:
Dual-Channel Multiplier for Piecewise-Polynomial Function Evaluation for Low-Power 3-D Graphics. 790-798 - Nitish Kumar Srivastava, Rajit Manohar:
Operation-Dependent Frequency Scaling Using Desynchronization. 799-809 - Christopher Cowan:
Drafting in Self-Timed Circuits. 810-820 - Takao Oshita, Jonathan Douglas, Arun Krishnamoorthy:
High-Volume Testing and DC Offset Trimming Technique of On-Die Bandgap Voltage Reference for SOCs and Microprocessors. 821-829 - Shirin Pourashraf, Jaime Ramírez-Angulo, Jose Maria Hinojo Montero, Ramón González Carvajal, Antonio J. López-Martín:
±0.25-V Class-AB CMOS Capacitance Multiplier and Precision Rectifiers. 830-842 - Bing Li, Ji-Ping Na, Wei Wang, Jia Liu, Qian Yang, Pui-In Mak:
A 13-bit 8-kS/s Δ-Σ Readout IC Using ZCB Integrators With an Embedded Resistive Sensor Achieving 1.05-pJ/Conversion Step and a 65-dB PSRR. 843-853 - Xuan Dong, Lihong Zhang:
EA-Based LDE-Aware Fast Analog Layout Retargeting With Device Abstraction. 854-863 - Weicheng Liu, Can Sitik, Emre Salman, Baris Taskin, Savithri Sundareswaran, Benjamin Huang:
SLECTS: Slew-Driven Clock Tree Synthesis. 864-874 - Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler:
Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits. 875-887 - Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim:
System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs. 888-898 - Abdullah Guler, Niraj K. Jha:
Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage. 899-912 - Christian Pilato, Kanad Basu, Francesco Regazzoni, Ramesh Karri:
Black-Hat High-Level Synthesis: Myth or Reality? 913-926 - Hadi Jahanirad:
CC-SPRA: Correlation Coefficients Approach for Signal Probability-Based Reliability Analysis. 927-939 - Han Zhou, Zeyu Sun, Sheriff Sadiqbatcha, Naehyuck Chang, Sheldon X.-D. Tan:
EM-Aware and Lifetime-Constrained Optimization for Multisegment Power Grid Networks. 940-953 - Yintang Yang, Ke Chen, Huaxi Gu, Bowen Zhang, Lijing Zhu:
TAONoC: A Regular Passive Optical Network-on-Chip Architecture Based on Comb Switches. 954-963 - Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto:
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation. 964-968 - Yi-An Chang, Trio Adiono, Amy Hamidah, Shen-Iuan Liu:
An On-Chip Relaxation Oscillator With Comparator Delay Compensation. 969-973 - Jusung Kim, Han-Shin Jo, Kyoung-Jae Lee, Dong-Ho Lee, Dae-Hyun Choi, Sangkil Kim:
A Low-Complexity I/Q Imbalance Calibration Method for Quadrature Modulator. 974-977 - Joo-Hyung Chae, Hyeongjun Ko, Jihwan Park, Suhwan Kim:
A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator. 978-982 - Safwat Mostafa Noor, Eugene John, Manoj Panday:
Design and Implementation of an Ultralow-Energy FFT ASIC for Processing ECG in Cardiac Pacemakers. 983-987 - Panni Wang, Feng Xu, Bo Wang, Bin Gao, Huaqiang Wu, He Qian, Shimeng Yu:
Three-Dimensional nand Flash for Vector-Matrix Multiplication. 988-991
Volume 27, Number 5, May 2019
- Manas Kumar Lenka, Gaurab Banerjee:
A Wideband Blocker-Tolerant Receiver With Frequency-Translational Resistive Feedback. 993-1006 - Omar Elsayed, Jorge Zarate-Roldan, Amr Abuellil, Faisal Abdel-Latif Hussien, Ahmed Eladawy, Edgar Sánchez-Sinencio:
Highly Linear Low-Power Wireless RF Receiver for WSN. 1007-1016 - Tutu Wan, Yasha Karimi, Milutin Stanacevic, Emre Salman:
AC Computing Methodology for RF-Powered IoT Devices. 1017-1028 - Heikki Kultala, Timo Viitanen, Heikki Berg, Pekka Jääskeläinen, Joonas Multanen, Mikko Kokkonen, Kalle Raiskila, Tommi Zetterman, Jarmo Takala:
LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor. 1029-1042 - Yuejun Zhang, Zhao Pan, Pengjun Wang, Dailu Ding, Qiaoyan Yu:
A 0.1-pJ/b and ACF <0.04 Multiple-Valued PUF for Chip Identification Using Bit-Line Sharing Strategy in 65-nm CMOS. 1043-1052 - Sandhya Koteshwara, Amitabh Das, Keshab K. Parhi:
Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms. 1053-1066 - Michael Weiner, Wolfgang Wieser, Emili Lupon, Georg Sigl, Salvador Manich:
A Calibratable Detector for Invasive Attacks. 1067-1079 - Partha De, Chittaranjan Mandal, Udaya Parampalli:
Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks. 1080-1092 - Yushan Jiang, Dong Wang, Pak Kwong Chan:
A Quiescent 407-nA Output-Capacitorless Low-Dropout Regulator With 0-100-mA Load Current Range. 1093-1104 - Yaqub Mahnashi, Fang Z. Peng:
A Monolithic Voltage-Scalable Fibonacci Switched-Capacitor DC-DC Converter With Intrinsic Parasitic Charge Recycling. 1105-1113 - Abdulqader Nael Mahmoud, Mohammad Alhawari, Baker Mohammad, Hani H. Saleh, Mohammed Ismail:
A Gain-Controlled, Low-Leakage Dickson Charge Pump for Energy-Harvesting Applications. 1114-1123 - Swati Bhardwaj, Shashank Raghuraman, Amit Acharyya:
Simplex FastICA: An Accelerated and Low Complex Architecture Design Methodology for $n$ D FastICA. 1124-1137 - Hareesh-Reddy Basireddy, Karthikeya Challa, Tooraj Nikoubin:
Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures. 1138-1147 - Mario Garrido, Jesús Grajal, Oscar Gustafsson:
Optimum Circuits for Bit-Dimension Permutations. 1148-1160 - Shaghayegh Vahdat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier. 1161-1173 - Qinghui Hong, Qiujie Wu, Xiaoping Wang, Zhigang Zeng:
Novel Nonlinear Function Shift Method for Generating Multiscroll Attractors Using Memristor-Based Control Circuit. 1174-1185 - John Vista, Ashish Ranjan:
A Simple Floating MOS-Memristor for High-Frequency Applications. 1186-1195 - Pavan Kumar Javvaji, Spyros Tragoudas:
On the Sensitization Probability of a Critical Path Considering Process Variations and Path Correlations. 1196-1205