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2020 – today
- 2021
[j8]Irith Pomeranz
, Xijiang Lin:
Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. 29(2): 423-433 (2021)- [c49]Xijiang Lin, Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz:
On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation. ATS 2021: 103-108 - [c48]Wei Li, Shih-Yu Yang, Khen Wee, Ricardo Sanchez, Jay Desai, Kun-Han Tsai, Xijiang Lin:
Timing Critical Path Validation for Intel ATOM Cores Using Structural Test. VTS 2021: 1-6 - 2020
- [c47]Uri Shpiro, Khen Wee, Kun-Han Tsai, Justyna Zawada, Xijiang Lin:
Test Challenges of Intel IA Cores. ITC 2020: 1-5
2010 – 2019
- 2019
- [c46]Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz:
TEA: A Test Generation Algorithm for Designs with Timing Exceptions. ATS 2019: 19-24 - [c45]Xijiang Lin, Sudhakar M. Reddy:
On Generating Fault Diagnosis Patterns for Designs with X Sources. ETS 2019: 1-6 - 2017
- [c44]Naixing Wang, Bo Yao, Xijiang Lin, Irith Pomeranz:
Functional Broadside Test Generation Using a Commercial ATPG Tool. ISVLSI 2017: 308-313 - [c43]Xijiang Lin:
On applying scan based structural test for designs with dual-edge triggered flip-flops. ITC 2017: 1-8 - 2016
- [j7]Dong Xiang, Kele Shen, Bhargab B. Bhattacharya, Xiaoqing Wen, Xijiang Lin:
Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3): 499-512 (2016) - [c42]Xijiang Lin, Sudhakar M. Reddy, Wu-Tung Cheng:
On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection. ATS 2016: 132-137 - [c41]Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski:
Transistor stuck-on fault detection tests for digital CMOS circuits. ETS 2016: 1-6 - 2015
- [c40]Xijiang Lin, Wu-Tung Cheng, Janusz Rajski:
On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults. ATS 2015: 97-102 - [c39]Xijiang Lin, Sudhakar M. Reddy:
On generating high quality tests based on cell functions. ITC 2015: 1-9 - [c38]Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski:
Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits. VLSID 2015: 399-404 - 2014
- [c37]Xijiang Lin, Mark Kassab, Janusz Rajski:
Using dynamic shift to reduce test data volume in high-compression designs. ETS 2014: 1-6 - [p1]Mark Kassab, Benoit Nadeau-Dostie, Xijiang Lin:
Timing-Aware ATPG. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 49-72 - 2013
- [j6]Dong Xiang, Jianbo Li, Krishnendu Chakrabarty, Xijiang Lin:
Test compaction for small-delay defects using an effective path selection scheme. ACM Trans. Design Autom. Electr. Syst. 18(3): 44:1-44:23 (2013) - [c36]Kun-Han Tsai, Xijiang Lin:
Multicycle-aware At-speed Test Methodology. Asian Test Symposium 2013: 49 - 2012
- [c35]Xijiang Lin, Janusz Rajski:
On Utilizing Test Cube Properties to Reduce Test Data Volume Further. Asian Test Symposium 2012: 83-88 - [c34]Xijiang Lin:
Power Supply Droop and Its Impacts on Structural At-Speed Testing. Asian Test Symposium 2012: 239-244 - 2011
- [c33]Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer:
Power Aware Embedded Test. Asian Test Symposium 2011: 511-516 - [c32]Xijiang Lin:
Low power testing - What can commercial DFT tools provide? IGCC 2011: 1-6 - 2010
- [j5]Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak:
On Reducing Scan Shift Activity at RTL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1110-1120 (2010) - [c31]Xijiang Lin, Janusz Rajski:
Adaptive Low Shift Power Test Pattern Generator for Logic BIST. Asian Test Symposium 2010: 355-360 - [c30]Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab:
Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. ITC 2010: 114-123 - [c29]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab:
Low capture power at-speed test in EDT environment. ITC 2010: 714-723 - [c28]Dat Tran, LeRoy Winemberg, Darrell Carder, Xijiang Lin, Joe LeBritton, Bruce Swanson:
Detecting and diagnosing open defects. ITC 2010: 811
2000 – 2009
- 2009
- [j4]Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low-Power Scan Operation in Test Compression Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1742-1755 (2009) - [c27]Xijiang Lin, Mark Kassab:
Test Generation for Designs with On-Chip Clock Generators. Asian Test Symposium 2009: 411-417 - 2008
- [j3]Xijiang Lin, Yu Huang:
Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells. J. Electron. Test. 24(4): 327-334 (2008) - [c26]Xijiang Lin, Janusz Rajski:
Test Power Reduction by Blocking Scan Cell Outputs. ATS 2008: 329-336 - [c25]Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low Power Scan Shift and Capture in the EDT Environment. ITC 2008: 1-10 - [c24]Xijiang Lin, Janusz Rajski:
Test Generation for Interconnect Opens. ITC 2008: 1-7 - [c23]Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak:
Reducing Scan Shift Power at RTL. VTS 2008: 139-146 - 2007
- [j2]Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
Scan-Based Tests with Low Switching Activity. IEEE Des. Test Comput. 24(3): 268-275 (2007) - [c22]Yu Huang, Xijiang Lin:
Programmable Logic BIST for At-speed Test. ATS 2007: 295-300 - [c21]Xijiang Lin, Mark Kassab, Janusz Rajski:
Test Generation for Timing-Critical Transition Faults. ATS 2007: 493-500 - [c20]Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
Low Shift and Capture Power Scan Tests. VLSI Design 2007: 793-798 - [i1]Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press:
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. CoRR abs/0710.4763 (2007) - 2006
- [c19]Xijiang Lin, Kun-Han Tsai, Chen Wang, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo:
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. ATS 2006: 139-146 - [c18]Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. ITC 2006: 1-10 - [c17]Xijiang Lin, Janusz Rajski:
The Impacts of Untestable Defects on Transition Fault Testing. VTS 2006: 2-7 - [c16]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski:
Scan Tests with Multiple Fault Activation Cycles for Delay Faults. VTS 2006: 343-348 - 2005
- [c15]Xijiang Lin, Janusz Rajski:
Propagation delay fault: a new fault model to test delay faults. ASP-DAC 2005: 178-183 - [c14]Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press:
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. DATE 2005: 56-61 - [c13]Matthias Beck, Olivier Barondeau, Frank Poehl, Xijiang Lin, Ron Press:
Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study. VTS 2005: 223-228 - 2003
- [j1]Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli:
High-Frequency, At-Speed Scan Testing. IEEE Des. Test Comput. 20(5): 17-25 (2003) - [c12]Xijiang Lin, Rob Thompson:
Test generation for designs with multiple clocks. DAC 2003: 662-667 - 2002
- [c11]Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski:
Conflict driven techniques for improving deterministic test pattern generation. ICCAD 2002: 87-93 - [c10]Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich:
Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. VTS 2002: 3-8 - 2001
- [c9]Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin:
Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan. Asian Test Symposium 2001: 467 - [c8]Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy:
On static test compaction and test pattern ordering for scan designs. ITC 2001: 1088-1097 - 2000
- [c7]Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy:
SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. VTS 2000: 205-212
1990 – 1999
- 1999
- [c6]Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
Full Scan Fault Coverage With Partial Scan. DATE 1999: 468-472 - [c5]Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
Techniques for improving the efficiency of sequential circuit test generation. ICCAD 1999: 147-151 - [c4]Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin:
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. VTS 1999: 275-283 - 1998
- [c3]Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
On finding undetectable and redundant faults in synchronous sequential circuits. ICCD 1998: 498-503 - [c2]Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
MIX: A Test Generation System for Synchronous Sequential Circuits. VLSI Design 1998: 456-463 - [c1]Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
On Removing Redundant Faults in Synchronous Sequential Circuits. VTS 1998: 168-175
Coauthor Index
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last updated on 2023-09-28 02:42 CEST by the dblp team
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