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ORCID52nd DAC 2015: San Francisco, CA, USA
- Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015. ACM 2015, ISBN 978-1-4503-3520-1
- Moomen Chaari, Wolfgang Ecker, Cristiano Novello, Bogdan-Andrei Tabacaru, Thomas Kruse:
A model-based and simulation-assisted FMEDA approach for safety-relevant E/E systems. 1:1-1:6 - Kenji Nishimiya, Toru Saito, Satoshi Shimada:
Evaluation of functional mock-up interface for vehicle power network modeling. 2:1-2:6 - Armin Wasicek, Edward A. Lee, Hokeun Kim
, Lev Greenberg, Akihito Iwai, Ilge Akkaya:
System simulation from operational data. 3:1-3:6 - Andrew B. Kahng:
New game, new goal posts: a recent history of timing closure. 4:1-4:6 - Carl Bowen:
Walking a thin line: performance and quality grading vs. yield overcut. 5:1-5:2 - Karthi Duraisamy, Ryan Gary Kim, Wonje Choi, Guangshuo Liu, Partha Pratim Pande, Radu Marculescu, Diana Marculescu:
Energy efficient MapReduce with VFI-enabled multicore platforms. 6:1-6:6 - Hui Li, Sébastien Le Beux, Yvain Thonnart, Ian O'Connor:
Complementary communication path for energy efficient on-chip optical interconnects. 7:1-7:6 - Jason Cong, Michael Gill, Yuchen Hao, Glenn Reinman, Bo Yuan:
On-chip interconnection network for accelerator-rich architectures. 8:1-8:6 - Hyunjun Jang, Jinchun Kim, Paul Gratz, Ki Hwan Yum, Eun Jung Kim:
Bandwidth-efficient on-chip interconnect designs for GPGPUs. 9:1-9:6 - Jia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, Yuan Xie:
DimNoC: a dim silicon approach towards power-efficient on-chip network. 10:1-10:6 - Donald Kline Jr., Haifeng Xu, Rami G. Melhem, Alex K. Jones:
Domain-wall memory buffer for low-energy NoCs. 11:1-11:6 - Wei Wen, Chi-Ruo Wu, Xiaofang Hu, Beiye Liu, Tsung-Yi Ho, Xin Li, Yiran Chen:
An EDA framework for large scale hybrid neuromorphic computing systems. 12:1-12:6 - Boxun Li, Lixue Xia, Peng Gu, Yu Wang, Huazhong Yang:
Merging the interface: power, area and accuracy co-optimization for RRAM crossbar-based mixed-signal computing system. 13:1-13:6 - Chenchen Liu, Bonan Yan, Chaofei Yang, Linghao Song, Zheng Li, Beiye Liu, Yiran Chen, Hai Li, Qing Wu, Hao Jiang:
A spiking neuromorphic design with resistive crossbar. 14:1-14:6 - Beiye Liu, Hai Li, Yiran Chen, Xin Li, Qing Wu, Tingwen Huang:
Vortex: variation-aware training for memristor X-bar. 15:1-15:6 - Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang:
Jump test for metallic CNTs in CNFET-based SRAM. 16:1-16:6 - Gai Liu, Zhiru Zhang:
A reconfigurable analog substrate for highly efficient maximum flow computation. 17:1-17:6 - Sebastian Graf, Sebastian Reinhart, Michael Glaß, Jürgen Teich, Daniel Platte:
Robust design of E/E architecture component platforms. 18:1-18:6 - Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li:
RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory. 19:1-19:6 - Shouzhen Gu, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Yiran Chen, Jingtong Hu:
Area and performance co-optimization for domain wall memory in application-specific embedded systems. 20:1-20:6 - Rujia Wang, Lei Jiang, Youtao Zhang, Linzhang Wang, Jun Yang:
Selective restore: an energy efficient read disturbance mitigation scheme for future STT-MRAM. 21:1-21:6 - Andreas Tretter, Pratyush Kumar, Lothar Thiele:
Interleaved multi-bank scratchpad memories: a probabilistic description of access conflicts. 22:1-22:6 - Seyed Mohammad Seyedzadeh, Rakan Maddah, Alex K. Jones, Rami G. Melhem:
PRES: pseudo-random encoding scheme to increase the bit flip reduction in the memory. 23:1-23:6 - Yohan Ko, Reiley Jeyapaul, Youngbin Kim, Kyoungwoo Lee, Aviral Shrivastava:
Guidelines to design parity protected write-back L1 data cache. 24:1-24:6 - Rickard Ewetz, Shankarshana Janarthanan, Cheng-Kok Koh:
Construction of reconfigurable clock trees for MCMM designs. 25:1-25:6 - Kwangsoo Han, Jiajia Li, Andrew B. Kahng, Siddhartha Nath, Jongpil Lee:
A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction. 26:1-26:6 - Sheng-Yen Chen, Yao-Wen Chang:
Routing-architecture-aware analytical placement for heterogeneous FPGAs. 27:1-27:6 - Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan:
PARR: pin access planning and regular routing for self-aligned double patterning. 28:1-28:6 - Adrian Bock, Stephan Held, Nicolas Kämmerling, Ulrike Schorr:
Local search algorithms for timing-driven placement under arbitrary delay models. 29:1-29:6 - Wei-Ting Jonas Chan, Siddhartha Nath, Andrew B. Kahng, Yang Du, Kambiz Samadi:
3DIC benefit estimation and implementation guidance from 2DIC implementation. 30:1-30:6 - Yannan Liu, Jie Zhang, Lingxiao Wei, Feng Yuan, Qiang Xu:
DERA: yet another differential fault attack on cryptographic devices based on error rate analysis. 31:1-31:6 - Younghyun Kim, Woo Suk Lee, Vijay Raghunathan, Niraj K. Jha, Anand Raghunathan:
Vibration-based secure side channel for medical devices. 32:1-32:6 - Giovanni Agosta, Alessandro Barenghi, Gerardo Pelosi, Michele Scandale:
Information leakage chaff: feeding red herrings to side channel attackers. 33:1-33:6 - Ferdinand Brasser, Brahim El Mahjoub, Ahmad-Reza Sadeghi, Christian Wachsmann, Patrick Koeberl:
TyTAN: tiny trust anchor for tiny devices. 34:1-34:6 - Man-Ki Yoon, Lui Sha, Sibin Mohan, Jaesik Choi:
Memory heat map: anomaly detection in real-time embedded systems using memory behavior. 35:1-35:6 - Ebrahim M. Songhori, Siam U. Hussain, Ahmad-Reza Sadeghi, Farinaz Koushanfar:
Compacting privacy-preserving k-nearest neighbor search using logic synthesis. 36:1-36:6 - Korosh Vatanparvar, Mohammad Abdullah Al Faruque:
Battery lifetime-aware automotive climate control for electric vehicles. 37:1-37:6 - Philipp Mundhenk, Sebastian Steinhorst, Martin Lukasiewycz, Suhaib A. Fahmy, Samarjit Chakraborty:
Security analysis of automotive architectures using probabilistic model checking. 38:1-38:6 - Shanker Shreejith, Suhaib A. Fahmy:
Security aware network controllers for next generation automotive embedded systems. 39:1-39:6 - Jaime Espinosa, Carles Hernández, Jaume Abella, David de Andrés, Juan-Carlos Ruiz-Garcia:
Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification. 40:1-40:6 - Daniel Thiele, Philip Axer, Rolf Ernst:
Improving formal timing analysis of switched ethernet by exploiting FIFO scheduling. 41:1-41:6 - Sebastian Kehr, Eduardo Quiñones, Bert Böddeker, Günter Schäfer:
Parallel execution of AUTOSAR legacy applications on multicore ECUs with timed implicit communication. 42:1-42:6 - Michael K. Papamichael, Peter A. Milder, James C. Hoe:
Nautilus: fast automated IP design space search using guided genetic algorithms. 43:1-43:6 - Sascha Roloff, David Schafhauser, Frank Hannig, Jürgen Teich:
Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures. 44:1-44:6 - Junbin Wang, Leibo Liu, Jianfeng Zhu, Shouyi Yin, Shaojun Wei:
Acceleration of control flows on reconfigurable architecture with a composite method. 45:1-45:6 - Munish Jassi, Daniel Müller-Gritschneder, Ulf Schlichtmann:
GRIP: grammar-based IP integration and packaging for acceleration-rich SoC designs. 46:1-46:6 - Ying Wang, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li:
ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing. 47:1-47:6 - Harry D. Foster:
Trends in functional verification: a 2014 industry study. 48:1-48:6 - Vladimir Herdt, Hoang Minh Le, Rolf Drechsler:
Verifying SystemC using stateful symbolic simulation. 49:1-49:6 - Tim Todman, Stephan Stilkerich, Wayne Luk:
In-circuit temporal monitors for runtime verification of reconfigurable designs. 50:1-50:6 - Yu-Yun Dai, Kei-Yong Khoo, Robert K. Brayton:
Sequential equivalence checking of clock-gated circuits. 51:1-51:6 - Maciej J. Ciesielski, Cunxi Yu, Walter Brown, Duo Liu, André Rossi:
Verification of gate-level arithmetic circuits by function extraction. 52:1-52:6 - Keith A. Campbell, David Lin, Subhasish Mitra, Deming Chen:
Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles. 53:1-53:6 - Ahmad-Reza Sadeghi, Christian Wachsmann, Michael Waidner:
Security and privacy challenges in industrial internet of things. 54:1-54:6 - Stephen McLaughlin:
Blocking unsafe behaviors in control systems through static and dynamic policy enforcement. 55:1-55:6 - Dirk Ziegenbein, Arne Hamann:
Timing-aware control software design for automotive systems. 56:1-56:6 - Shankara Narayanan Krishna, Ganesh Khandu Narwane, S. Ramesh, Ashutosh Trivedi:
Compositional modeling and analysis of automotive feature product lines. 57:1-57:6 - Huafeng Yu, Prachi Joshi, Jean-Pierre Talpin, Sandeep K. Shukla, Shin'ichi Shiraishi:
The challenge of interoperability: model-based integration for automotive control software. 58:1-58:6 - John P. Hayes:
Introduction to stochastic computing and its challenges. 59:1-59:3 - Alexandru Paler, Simon J. Devitt:
An introduction into fault-tolerant quantum computing. 60:1-60:6 - Ilia Polian, Austin G. Fowler:
Design automation challenges for scalable quantum architectures. 61:1-61:6 - David Kadjo, Raid Ayoub, Michael Kishinevsky, Paul V. Gratz:
A control-theoretic approach for energy efficient CPU-GPU subsystem in mobile platforms. 62:1-62:6 - Hu Chen, Dieudonne Manzi, Sanghamitra Roy, Koushik Chakraborty:
Opportunistic turbo execution in NTC: exploiting the paradigm shift in performance bottlenecks. 63:1-63:6 - Jinil Chung, Kenneth Ramclam, Jongsun Park, Swaroop Ghosh:
Domain wall memory based digital signal processors for area and energy-efficiency. 64:1-64:6 - Xiang Chen, Yiran Chen, Chun Jason Xue:
DaTuM: dynamic tone mapping technique for OLED display power saving based on video classification. 65:1-65:6 - Xiaoxiao Liu, Mengjie Mao, Beiye Liu, Hai Li, Yiran Chen, Boxun Li, Yu Wang, Hao Jiang, Mark Barnell, Qing Wu, Jianhua Joshua Yang:
RENO: a high-efficient reconfigurable neuromorphic computing accelerator design. 66:1-66:6 - Swagath Venkataramani, Anand Raghunathan, Jie Liu, Mohammed Shoaib:
Scalable-effort classifiers for energy-efficient machine learning. 67:1-67:6 - Kwangsoo Han, Andrew B. Kahng, Hyein Lee:
Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router. 68:1-68:6 - Yixiao Ding, Chris C. N. Chu, Wai-Kei Mak:
Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography. 69:1-69:6 - Yasmine Badr, Andres Torres, Puneet Gupta:
Mask assignment and synthesis of DSA-MP hybrid lithography for sub-7nm contacts/vias. 70:1-70:6 - Yibo Lin, Bei Yu, David Z. Pan:
High performance dummy fill insertion with coupling and uniformity constraints. 71:1-71:6 - Yixiao Ding, Chris C. N. Chu, Xin Zhou:
An efficient shift invariant rasterization algorithm for all-angle mask patterns in ILT. 72:1-72:6 - Abde Ali Kagalwalla, Puneet Gupta:
Effective model-based mask fracturing for mask cost reduction. 73:1-73:6 - Lucas Davi, Matthias Hanreich, Debayan Paul, Ahmad-Reza Sadeghi, Patrick Koeberl, Dean Sullivan, Orlando Arias, Yier Jin:
HAFIX: hardware-assisted flow integrity extension. 74:1-74:6 - Garrett S. Rose, Chauncey A. Meade:
Performance analysis of a memristive crossbar PUF design. 75:1-75:6 - Teng Xu, Dongfang Li, Miodrag Potkonjak:
Adaptive characterization and emulation of delay-based physical unclonable functions using statistical models. 76:1-76:6 - Jae-Won Jang, Jongsun Park, Swaroop Ghosh, Swarup Bhunia:
Self-correcting STTRAM under magnetic field attacks. 77:1-77:6 - Edward Tashjian, Azadeh Davoodi:
On using control signals for word-level identification in a gate-level netlist. 78:1-78:6 - Jinyong Lee, Ingoo Heo, Yongje Lee, Yunheung Paek:
Efficient dynamic information flow tracking on a processor with core debug interface. 79:1-79:6 - Marilyn Wolf, Eric Feron:
What don't we know about CPS architectures? 80:1-80:4 - Janos Sztipanovits, Ted Bapty, Sandeep Neema, Xenofon D. Koutsoukos, Ethan K. Jackson:
Design tool chain for cyber-physical systems: lessons learned. 81:1-81:6 - Bharathan Balaji, Mohammad Abdullah Al Faruque, Nikil D. Dutt, Rajesh K. Gupta, Yuvraj Agarwal:
Models, abstractions, and architectures: the missing links in cyber-physical systems. 82:1-82:6 - Mengjie Mao, Jingtong Hu, Yiran Chen, Hai Li:
VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications. 83:1-83:6 - Nasibeh Teimouri, Hamed Tabkhi, Gunar Schirner:
Revisiting accelerator-rich CMPs: challenges and solutions. 84:1-84:6 - Haseeb Bokhari, Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran:
SuperNet: multimode interconnect architecture for manycore chips. 85:1-85:6 - Muhammad Shafique, Waqas Ahmad, Rehan Hafiz, Jörg Henkel:
A low latency generic accuracy configurable adder. 86:1-86:6 - Guangli Jiang, Leibo Liu, Wenping Zhu, Shouyi Yin, Shaojun Wei:
A 127 fps in full hd accelerator based on optimized AKAZE with efficiency and effectiveness for image feature extraction. 87:1-87:6 - Rujia Wang, Lei Jiang, Youtao Zhang, Linzhang Wang, Jun Yang:
Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory. 88:1-88:6 - Hyungmin Cho, Chen-Yong Cher, Thomas Shepherd, Subhasish Mitra:
Understanding soft errors in uncore components. 89:1-89:6 - Hai-Bao Chen, Sheldon X.-D. Tan, Valeriy Sukharev, Xin Huang, Taeyoung Kim:
Interconnect reliability modeling and analysis for multi-branch interconnect trees. 90:1-90:6 - Yarui Peng, Bon Woong Ku, Youn-Sik Park, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi, Sung Kyu Lim:
Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM. 91:1-91:6 - Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim:
Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications. 92:1-92:6 - Ye Wang, Meng Li, Xinyang Yi, Zhao Song, Michael Orshansky, Constantine Caramanis:
Novel power grid reduction method based on L1 regularization. 93:1-93:6 - Xiaochen Liu, Shupeng Sun, Pingqiang Zhou, Xin Li, Haifeng Qian:
A statistical methodology for noise sensor placement and full-chip voltage map generation. 94:1-94:6 - Beiye Liu, Chunpeng Wu, Hai Li, Yiran Chen, Qing Wu, Mark Barnell, Qinru Qiu:
Cloning your mind: security challenges in cognitive system designs and their solutions. 95:1-95:5 - Bowen Zheng, Wenchao Li, Peng Deng, Léonard Gérard, Qi Zhu, Natarajan Shankar:
Design and verification for transportation system security. 96:1-96:6 - Yang Liu, Shiyan Hu, Jie Wu, Yiyu Shi, Yier Jin, Yu Hu, Xiaowei Li:
Impact assessment of net metering on smart home cyberattack detection. 97:1-97:6 - Adam D. Sherer, John Rose, Riccardo Oddone:
Ensuring functional safety compliance for ISO 26262. 98:1-98:3 - Bernhard Schätz, Sebastian Voss, Sergey Zverlov:
Automating design-space exploration: optimal deployment of automotive SW-components in an ISO26262 context. 99:1-99:6 - Hsiang-Jen Tsai, Keng-Hao Yang, Yin-Chi Peng, Chien-Chen Lin, Ya-Han Tsao, Meng-Fan Chang, Tien-Fu Chen:
Energy-efficient non-volatile TCAM search engine design using priority-decision in memory technology for DPI. 100:1-100:6 - Muhammad Shafique, Muhammad Usman Karim Khan, Adnan Orcun Tüfek, Jörg Henkel:
EnAAM: energy-efficient anti-aging for on-chip video memories. 101:1-101:6 - Shrikanth Ganapathy, Georgios Karakonstantis, Adam Teman, Andreas Burg:
Mitigating the impact of faults in unreliable memories for error-resilient applications. 102:1-102:6 - Gushu Li, Xiaoming Chen, Guangyu Sun, Henry Hoffmann, Yongpan Liu, Yu Wang, Huazhong Yang:
A STT-RAM-based low-power hybrid register file for GPGPUs. 103:1-103:6 - Chaofan Li, Wei Luo, Sachin S. Sapatnekar, Jiang Hu:
Joint precision optimization and high level synthesis for approximate computing. 104:1-104:6 - Georgios Tziantzioulis, Ali Murat Gok, S. M. Faisal, Nikolaos Hardavellas, Seda Ogrenci Memik, Srinivasan Parthasarathy:
b-HiVE: a bit-level history-based error model with value correlation for voltage-scaled integer and floating point units. 105:1-105:6 - YoungHoon Jung, Luca P. Carloni:
ΣVP: host-GPU multiplexing for efficient simulation of multiple embedded GPUs on virtual platforms. 106:1-106:6 - Jaeyoung Yun, Jinsu Park, Woongki Baek:
HARS: a heterogeneity-aware runtime system for self-adaptive multithreaded applications. 107:1-107:6 - Lukas Cavigelli, Michele Magno, Luca Benini:
Accelerating real-time embedded scene labeling with convolutional networks. 108:1-108:6 - Santanu Sarma, Tiago Mück, Luis Angel D. Bathen, Nikil D. Dutt, Alexandru Nicolau:
SmartBalance: a sensing-driven linux load balancer for energy efficiency of heterogeneous MPSoCs. 109:1-109:6 - Hongsik Lee, Dong Nguyen, Jongeun Lee:
Optimizing stream program performance on CGRA-based systems. 110:1-110:6 - Boyou Zhou, Ronen Adato, Mahmoud Zangeneh, Tianyu Yang, Aydan Uyar, Bennett B. Goldberg, M. Selim Ünlü, Ajay Joshi:
Detecting hardware trojans using backside optical imaging of embedded watermarks. 111:1-111:6 - Jeyavijayan Rajendran, Vivekananda Vedula, Ramesh Karri:
Detecting malicious modifications of data in third-party intellectual property cores. 112:1-112:6 - Carson Dunbar, Gang Qu:
A practical circuit fingerprinting method utilizing observability don't care conditions. 113:1-113:6 - Zimu Guo, Mark Tehranipoor, Domenic Forte, Jia Di:
Investigation of obfuscation-based anti-reverse engineering for printed circuit boards. 114:1-114:6 - Weize Yu, Orhun Aras Uzun, Selçuk Köse:
Leveraging on-chip voltage regulators as a countermeasure against side-channel attacks. 115:1-115:6 - Vladimir Rozic, Bohan Yang, Wim Dehaene, Ingrid Verbauwhede:
Highly efficient entropy extraction for true random number generators on FPGAs. 116:1-116:6 - Veit B. Kleeberger, Stefan Rutkowski, Ruth Coppens:
Design & verification of automotive SoC firmware. 117:1-117:6 - Alexandre Petrenko, Omer Nguena-Timo, S. Ramesh:
Model-based testing of automotive software: some challenges and solutions. 118:1-118:6 - Jörg Henkel, Heba Khdr, Santiago Pagani, Muhammad Shafique:
New trends in dark silicon. 119:1-119:6 - Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Approximate computing and the quest for computing efficiency. 120:1-120:6 - Hsiang-Yun Cheng, Jia Zhan, Jishen Zhao, Yuan Xie, Jack Sampson, Mary Jane Irwin:
Core vs. uncore: the heart of darkness. 121:1-121:6 - Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler:
A generic representation of CCSL time constraints for UML/MARTE models. 122:1-122:6 - Mohamed Ismail, Daniel Lo, G. Edward Suh:
Improving worst-case cache performance through selective bypassing and register-indexed cache. 123:1-123:6 - Suzana Milutinovic, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla:
PACO: fast average-performance estimation for time-randomized caches. 124:1-124:6 - Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla:
Increasing confidence on measurement-based contention bounds for real-time round-robin buses. 125:1-125:6 - Daming Zhang, Yongpan Liu, Xiao Sheng, Jinyang Li, Tongda Wu, Chun Jason Xue, Huazhong Yang:
Deadline-aware task scheduling for solar-powered nonvolatile sensor nodes with global energy migration. 126:1-126:6 - Martin Lukasiewycz, Florian Sagstetter, Sebastian Steinhorst:
Efficient design space exploration of embedded platforms. 127:1-127:6 - Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits. 128:1-128:6 - Subhendu Roy, Derong Liu, Junhyung Um, David Z. Pan:
OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions. 129:1-129:6 - Ting-Wei Chiang, Kai-Hui Chang, Yen-Ting Liu, Jie-Hong R. Jiang:
Scalable sequence-constrained retention register minimization in power gating design. 130:1-130:6 - Te-Hsuan Chen, John P. Hayes:
Equivalence among stochastic logic circuits and its application. 131:1-131:6 - Zhiheng Wang, Naman Saraf, Kia Bazargan, Arnd Scheel:
Randomness meets feedback: stochastic implementation of logistic map dynamical system. 132:1-132:7 - Runjie Zhang, Kaushik Mazumdar, Brett H. Meyer, Ke Wang, Kevin Skadron, Mircea R. Stan:
A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC. 133:1-133:6 - Tiansong Cui, Yanzhi Wang, Shuang Chen, Qi Zhu, Shahin Nazarian, Massoud Pedram:
Optimal control of PEVs for energy cost minimization and frequency regulation in the smart grid accounting for battery state-of-health degradation. 134:1-134:6 - Jaeseong Lee, Yohan Chon, Hojung Cha:
Evaluating battery aging on mobile devices. 135:1-135:6 - Haluk Konuk, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Deepak Solanki, Jerzy Tyszer, Justyna Zawada:
Design for low test pattern counts. 136:1-136:6 - Irith Pomeranz:
Generation of close-to-functional broadside tests with equal primary input vectors. 137:1-137:6 - Yu-Hsuan Su, Yao-Wen Chang:
Nanowire-aware routing considering high cut mask complexity. 138:1-138:6 - Xianzhang Chen, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Penglin Dai, Weiwen Jiang:
Optimizing data placement for reducing shift operations on domain wall memories. 139:1-139:6 - Ying-Yu Chen, Zelei Sun, Deming Chen:
A SPICE model of flexible transition metal dichalcogenide field-effect transistors. 140:1-140:6 - Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping. 141:1-141:6 - Hailong Yao, Tsung-Yi Ho, Yici Cai:
PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips. 142:1-142:6 - Joydeep Rakshit, Runlai Wan, Kai Tak Lam, Jing Guo, Kartik Mohanram:
Monolayer transition metal dichalcogenide and black phosphorus transistors for low power robust SRAM design. 143:1-143:6 - Eric Peeters:
SoC security architecture: current practices and emerging needs. 144:1-144:6 - Xiaolong Guo, Raj Gautam Dutta, Yier Jin, Farimah Farahmandi, Prabhat Mishra:
Pre-silicon security verification and validation: a formal perspective. 145:1-145:6 - Sandip Ray, Jin Yang, Abhishek Basak, Swarup Bhunia:
Correctness and security at odds: post-silicon validation of modern SoC designs. 146:1-146:6 - Yanzhi Wang, Xue Lin, Massoud Pedram, Naehyuck Chang:
Joint automatic control of the powertrain and auxiliary systems to enhance the electromobility in hybrid electric vehicles. 147:1-147:6 - Sanjit A. Seshia, Dorsa Sadigh, S. Shankar Sastry:
Formal methods for semi-autonomous driving. 148:1-148:5 - Samantak Gangopadhyay, Saad Bin Nasir, Arijit Raychowdhury:
Integrated power management in IoT devices under wide dynamic ranges of operation. 149:1-149:6 - Yongpan Liu, Zewei Li, Hehe Li, Yiqun Wang, Xueqing Li, Kaisheng Ma, Shuangchen Li, Meng-Fan Chang, John Sampson, Yuan Xie, Jiwu Shu, Huazhong Yang:
Ambient energy harvesting nonvolatile processors: from circuit to system. 150:1-150:6 - Mohammad Khavari Tavana, Mohammad Hossein Hajkazemi, Divya Pathak, Ioannis Savidis, Houman Homayoun:
ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling. 151:1-151:6 - Abbas Rahimi, Daniele Cesarini, Andrea Marongiu, Rajesh K. Gupta, Luca Benini:
Task scheduling strategies to mitigate hardware variability in embedded shared memory clusters. 152:1-152:6 - Hamid Mirzaei Buini, Steffen Peter, Tony Givargis:
Including variability of physical models into the design automation of cyber-physical systems. 153:1-153:6 - Wen-Hung Huang, Jian-Jia Chen, Husheng Zhou, Cong Liu:
PASS: priority assignment of real-time tasks with dynamic suspending behavior under fixed-priority scheduling. 154:1-154:6 - Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla:
Resource usage templates and signatures for COTS multicore processors. 155:1-155:6 - Rui Santos, Shyamsundar Venkataraman, Akash Kumar:
Dynamically adaptive scrubbing mechanism for improved reliability in reconfigurable embedded systems. 156:1-156:6 - Ritchie Zhao, Mingxing Tan, Steve Dai, Zhiru Zhang:
Area-efficient pipelining for FPGA-targeted high-level synthesis. 157:1-157:6 - Peng Zhang, Muhuan Huang, Bingjun Xiao, Hui Huang, Jason Cong:
CMOST: a system-level FPGA compilation framework. 158:1-158:6 - Karel Heyse, Dirk Stroobandt:
Avoiding transitional effects in dynamic circuit specialisation on FPGAs. 159:1-159:6 - Chenyue Meng, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei:
Efficient memory partitioning for parallel data access in multidimensional arrays. 160:1-160:6 - Keith A. Campbell, Pranay Vissa, David Z. Pan, Deming Chen:
High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths. 161:1-161:6 - Masato Tatsuoka, Ryosuke Watanabe, Tatsushi Otsuka, Takashi Hasegawa, Qiang Zhu, Ryosuke Okamura, Xingri Li, Tsuyoshi Takabatake:
Physically aware high level synthesis design flow. 162:1-162:6 - Hao Zhuang, Wenjian Yu, Ilgweon Kang, Xinan Wang, Chung-Kuan Cheng:
An algorithmic framework for efficient large-scale circuit simulation using exponential integrators. 163:1-163:6 - Vladimir Zolotov, Peter Feldmann:
Variation aware cross-talk aggressor alignment by mixed integer linear programming. 164:1-164:6 - Jasper C. C. Chang, Ryan H.-M. Huang, Louis Y.-Z. Lin, Charles H.-P. Wen:
TA-FTA: transition-aware functional timing analysis with a four-valued encoding. 165:1-165:6 - S. Ramprasath, Vinita Vasudevan:
An efficient algorithm for statistical timing yield optimization. 166:1-166:6 - Yu-Ming Yang, King Ho Tam, Iris Hui-Ru Jiang:
Criticality-dependency-aware timing characterization and analysis. 167:1-167:6 - Subramanyam Sripada, Murthy Palla:
A timing graph based approach to mode merging. 168:1-168:6 - Qicheng Huang, Chenlei Fang, Fan Yang, Xuan Zeng, Xin Li:
Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits. 169:1-169:6 - Manzil Zaheer, Fa Wang, Chenjie Gu, Xin Li:
mTunes: efficient post-silicon tuning of mixed-signal/RF integrated circuits based on Markov decision process. 170:1-170:6 - Ons Lahiouel, Mohamed H. Zaki, Sofiène Tahar:
Towards enhancing analog circuits sizing using SMT-based techniques. 171:1-171:6 - Hafiz ul Asad, Kevin D. Jones:
Verifying inevitability of phase-locking in a charge pump phase lock loop using sum of squares programming. 172:1-172:6 - Aosen Wang, Zhanpeng Jin, Chen Song, Wenyao Xu:
Adaptive compressed sensing architecture in wireless brain-computer interface. 173:1-173:6 - Zhewei Jiang, Qi Wang, Mingoo Seok:
A low power unsupervised spike sorting accelerator insensitive to clustering initialization in sub-optimal feature space. 174:1-174:6 - Ray Beaulieu, Douglas Shors, Jason Smith, Stefan Treatman-Clark, Bryan Weeks, Louis Wingers:
The SIMON and SPECK lightweight block ciphers. 175:1-175:6 - Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Naofumi Homma, Yu-ichi Hayashi, Takafumi Aoki:
EM attack sensor: concept, circuit, and design-automation methodology. 176:1-176:6 - Megan Wachs, Daniel Ip:
Design and integration challenges of building security hardware IP. 177:1-177:6 - Ajay Kashyap, Soenke Grimpen, Shyam Sundaramoorthy:
Achieving power and reliability sign-off for automotive semiconductor designs. 178:1-178:6 - Heba Khdr, Santiago Pagani, Muhammad Shafique, Jörg Henkel:
Thermal constrained resource management for mixed ILP-TLP workloads in dark silicon chips. 179:1-179:6 - Dennis Gnad, Muhammad Shafique, Florian Kriebel, Semeen Rehman, Duo Sun, Jörg Henkel:
Hayat: harnessing dark silicon and variability for aging deceleration and balancing. 180:1-180:6 - Jun Liu, Jagadish Kotra, Wei Ding, Mahmut T. Kandemir:
Network footprint reduction through data access and computation placement in NoC-based manycores. 181:1-181:6 - Matthias Beckert, Rolf Ernst:
Designing time partitions for real-time hypervisor with sufficient temporal independence. 182:1-182:6 - Qing'an Li, Mengying Zhao, Jingtong Hu, Yongpan Liu, Yanxiang He, Chun Jason Xue:
Compiler directed automatic stack trimming for efficient non-volatile processors. 183:1-183:6 - Mimi Xie, Mengying Zhao, Chen Pan, Jingtong Hu, Yongpan Liu, Chun Jason Xue:
Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor. 184:1-184:6 - Lengfei Han, Zhuo Feng:
Transient-simulation guided graph sparsification approach to scalable harmonic balance (HB) analysis of post-layout RF circuits leveraging heterogeneous CPU-GPU computing systems. 185:1-185:6 - Ahmed E. Helal, Amr M. Bayoumi, Yasser Y. Hanafy:
Parallel circuit simulation using the direct method on a heterogeneous cloud. 186:1-186:6 - Vinita Vasudevan, M. Ramakrishna:
An efficient algorithm for frequency-weighted balanced truncation of VLSI interconnects in descriptor form. 187:1-187:6 - Tianshi Wang, Jaijeet Roychowdhury:
Design tools for oscillator-based computing systems. 188:1-188:6 - Hung-Chih Ou, Kai-Han Tseng, Jhao-Yan Liu, I-Peng Wu, Yao-Wen Chang:
Layout-dependent-effects-aware analytical analog placement. 189:1-189:6 - Hung-Chih Ou, Kai-Han Tseng, Yao-Wen Chang:
Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography. 190:1-190:6 - Sangwook Shane Hahn, Jihong Kim, Sungjin Lee:
To collect or not to collect: just-in-time garbage collection for high-performance SSDs with long lifetimes. 191:1-191:6 - Yu-Ming Chang, Yuan-Hao Chang, Tei-Wei Kuo, Yung-Chun Li, Hsiang-Pang Li:
Achieving SLC performance with MLC flash memory. 192:1-192:6 - Ming-Chang Yang, Yuan-Hao Chang, Tei-Wei Kuo:
Virtual flash chips: rethinking the layer design of flash devices to improve data recoverability. 193:1-193:6 - Jie Guo, Wujie Wen, Jingtong Hu, Danghui Wang, Hai Li, Yiran Chen:
FlexLevel: a novel NAND flash storage system design for LDPC latency reduction. 194:1-194:6 - Ashish Ranjan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan:
Approximate storage for energy efficient spintronic memories. 195:1-195:6 - Huseyin Ekin Sumbul, Kaushik Vaidyanathan, Qiuling Zhu, Franz Franchetti, Larry T. Pileggi:
A synthesis methodology for application-specific logic-in-memory designs. 196:1-196:6 - David Z. Pan, Lars Liebmann, Bei Yu, Xiaoqing Xu, Yibo Lin:
Pushing multiple patterning in sub-10nm: are we ready? 197:1-197:6 - Yao-Wen Chang, Ru-Gun Liu, Shao-Yun Fang:
EUV and e-beam manufacturability: challenges and solutions. 198:1-198:6 - Zigang Xiao, Daifeng Guo, Martin D. F. Wong, He Yi, Maryann C. Tung, H.-S. Philip Wong:
Layout optimization and template pattern verification for directed self-assembly (DSA). 199:1-199:6 - Jakob Engblom:
Virtual to the (near) end: using virtual platforms for continuous integration. 200:1-200:6 - Anuj Pathania, Alexandru Eugen Irimiea, Alok Prakash, Tulika Mitra:
Power-Performance Modelling of Mobile Gaming Workloads on Heterogeneous MPSoCs. 201:1-201:6 - Emilio G. Cota, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni:
An Analysis of Accelerator Coupling in Heterogeneous Architectures. 202:1-202:6 - Weiwei Jiang, Kshitij Bhardwaj, Geoffray Lacourba, Steven M. Nowick:
A Lightweight Early Arbitration Method for Low-Latency Asynchronous 2D-Mesh NoC's. 203:1-203:6
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