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ORCID26th Asian Test Symposium 2017: Taipei City, Taiwan
- 26th IEEE Asian Test Symposium, ATS 2017, Taipei City, Taiwan, November 27-30, 2017. IEEE Computer Society 2017, ISBN 978-1-5386-2437-1
Session 1B: Interconnect Test and Measurement
- Pok Man Preston Law, Cheng-Wen Wu
, Long-Yi Lin, Hao-Chiao Hong:
An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages. 5-10 - Songwei Pei, Alrashdi Ahmed Rabehb, Song Jin:
On-Chip Ring Oscillator Based Scheme for TSV Delay Measurement. 11-16 - Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Masayuki Sato, Mitsunori Katsu, Shoichi Sekiguchi:
Testing of Interconnect Defects in Memory Based Reconfigurable Logic Device (MRLD). 17-22
Session 1C: Test Compression
- Chih-Ming Chang, Kai-Jie Yang, James Chien-Mo Li, Hung Chen:
Test Pattern Compression for Probabilistic Circuits. 23-27 - Chang-Wen Chen, Yi-Cheng Kong, Kuen-Jong Lee:
Test Compression with Single-Input Data Spreader and Multiple Test Sessions. 28-33 - Irith Pomeranz:
Test Compaction with Dynamic Updating of Faults for Coverage of Undetected Transition Fault Sites. 34-39
Session 2A: Hardware Security
- Aijiao Cui, Xuesen Qian, Gang Qu, Huawei Li:
A New Active IC Metering Technique Based on Locking Scan Cells. 40-45 - Yung-Chih Chen:
Tree-Based Logic Encryption for Resisting SAT Attack. 46-51 - Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue, Alex Orailoglu:
Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection. 52-57 - Satyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Virendra Singh:
On Securing Scan Design from Scan-Based Side-Channel Attacks. 58-63
Session 2B: Circuits and Systems Reliability-Enhancement Techniques
- Si-Rong He, Nguyen Cao Qui, Yu-Hsuan Kuo, Chien-Nan Jimmy Liu:
An Incremental Aging Analysis Method Based on Delta Circuit Simulation Technique. 64-69 - Zih-Huan Gao, Hau Hsu, Ting-Shuo Hsu, Jing-Jia Liou:
Post-Silicon Test Flow for Aging Prediction. 70-75 - Guan-Hao Lian, Shi-Yu Huang, Wei-yi Chen:
Cloud-Based PVT Monitoring System for IoT Devices. 76-81 - Marko S. Andjelkovic, Milos Krstic, Rolf Kraemer, Varadan Savulimedu Veeravalli, Andreas Steininger:
A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study. 82-87
Session 2C: Techniques for Testing and Reliability
- Yang-Kai Huang, Kuan-Te Li, Chih-Lung Hsiao, Chia-An Lee, Jiun-Lang Huang, Terry Kuo:
Design and Implementation of an EG-Pool Based FPGA Formatter with Temperature Compensation. 88-93 - Yuki Ozawa, Takashi Ida, Richen Jiang, Shotaro Sakurai, Seiya Takigami, Nobukazu Tsukiji, Ryoji Shiota, Haruo Kobayashi:
SAR TDC Architecture with Self-Calibration Employing Trigger Circuit. 94-99 - Christian M. Fuchs, Todor P. Stefanov, Nadia Murillo, Aske Plaat:
Bringing Fault-Tolerant GigaHertz-Computing to Space: A Multi-stage Software-Side Fault-Tolerance Approach for Miniaturized Spacecraft. 100-107 - Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler:
Identification of Efficient Clustering Techniques for Test Power Activity on the Layout. 108-113
Session 3A: Special Session on Hardware-Oriented Security and Trust
- Jack Tang, Mohamed Ibrahim, Krishnendu Chakrabarty, Ramesh Karri:
Security Implications of Cyberphysical Flow-Based Microfluidic Biochips. 115-120 - Wei Zhou, Aijiao Cui, Huawei Li, Gang Qu:
How to Secure Scan Design Against Scan-Based Side-Channel Attacks? 121-126
Session 3B: Scan Test
- Dominik Ull, Michael A. Kochte, Hans-Joachim Wunderlich:
Structure-Oriented Test of Reconfigurable Scan Networks. 127-132 - Irith Pomeranz:
Compaction of a Transparent-Scan Sequence to Reduce the Fail Data Volume for Scan Chain Faults. 133-138 - Amitava Majumdar, Balakrishna Jayadev, Da Cheng, Albert Lin:
Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs. 139-144 - Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian:
Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption. 145-150
Session 3C: Advanced Testing Techniques
- Kentaro Kato:
Deterministic Path Delay Measurement Using Short Cycle Test Pattern. 151-156 - Seetal Potluri, Aaron Mathew, Rambabu Nerukonda, Ismed Hartanto, Shahin Toutounchi:
Cell-Aware ATPG to Improve Defect Coverage for FPGA IPs and Next Generation Zynq® MPSoCs. 157-162 - Sying-Jyan Wang, Hsiang-Hsueh Chen, Chin-Hung Lien, Katherine Shu-Min Li:
Testing Clock Distribution Networks. 163-168 - Kun-Han Tsai, Srinivasan Gopalakrishnan:
Test Coverage Analysis for Designs with Timing Exceptions. 169-174
Session 4A: Special Session on Test and Reliability of Emerging Memories
- Said Hamdioui, Peyman Pouyan, Huawei Li, Ying Wang, Arijit Raychowdhury, Insik Yoon:
Test and Reliability of Emerging Non-volatile Memories. 175-183
Session 4B: Debugging and Design Verification
- Surya Piplani, Humberto Fonseca, Vivek Mohan Sharma, Daniele Cervini, David Hardisty:
Test and Debug Strategy for High Speed JESD204B Rx PHY. 184-188 - Kentaro Iwata, Amir Masoud Gharehbaghi, Mehdi Baradaran Tahoori, Masahiro Fujita:
Post Silicon Debugging of Electrical Bugs Using Trace Buffers. 189-194 - Huina Chao, Huawei Li, Xiaoyu Song, Tiancheng Wang, Xiaowei Li:
On Evaluating and Constraining Assertions Using Conflicts in Absent Scenarios. 195-200
Session 4C: Yield Enhancement and Diagnosis
- Keitaro Koga, Hiromitsu Awano, Makoto Ikeda:
Yield Enhancement by Repair Circuits for Ultra-Fine Pitch Stacked-Chip Connections. 201-205 - Tong-Yu Hsieh, Tai-Ang Cheng, Chao-Ru Chen:
Error-Tolerability Evaluation and Test for Images in Face Detection Applications. 206-211 - Soumya Mittal, R. D. (Shawn) Blanton:
PADLOC: Physically-Aware Defect Localization and Characterization. 212-218
Session 5A: Advanced Diagnosis Techniques
- Wu-Tung Cheng, Randy Klingenberg, Brady Benware, Wu Yang, Manish Sharma, Geir Eide, Yue Tian, Sudhakar M. Reddy, Yan Pan, Sherwin Fernandes, Atul Chittora:
Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data. 219-224 - Yu Huang, Brady Benware, Randy Klingenberg, Huaxing Tang, Jayant Dsouza, Wu-Tung Cheng:
Scan Chain Diagnosis Based on Unsupervised Machine Learning. 225-230 - Huaxing Tang, Arvind Jain, Sanil Kumark Pillai, Dharmesh Joshi, Shamitha Rao:
Using Cell Aware Diagnostic Patterns to Improve Diagnosis Resolution for Cell Internal Defects. 231-236
Session 5B: Design for Testability
- Yoichi Maeda, Jun Matsushima, Ron Press:
Automotive IC On-line Test Techniques and the Application of Deterministic ATPG-Based Runtime Test. 237-241 - Ayumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, Masaki Hashizume, Shyue-Kung Lu:
Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs. 242-247 - Joyati Mondal, Debesh Kumar Das:
Design for Testability Technique of Reversible Logic Circuits Based on Exclusive Testing. 248-253
Session 5C: Memory Test and Reliability
- Shyue-Kung Lu, Shu-Chi Yu, Masaki Hashizume, Hiroyuki Yotsuyanagi:
Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories. 254-259 - Yen-Chun Ko, Shih-Hsu Huang:
3D IC Memory BIST Controller Allocation for Test Time Minimization Under Power Constraints. 260-265 - Xiaole Cui, Yichi Luo, Qiujun Lin, Xiaoxin Cui:
A Heuristic Algorithm for Automatic Generation of March Tests. 266-271
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