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ORCIDIEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 16
Volume 16, Number 1, January 2008
- Toomas P. Plaks:
Guest Editorial Special Section on Configurable Computing Design- I: High-Level Reconfiguration. 1-2 - Gerard K. Rauwerda, Paul M. Heysters, Gerard J. M. Smit:
Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware. 3-13 - Mitchell J. Myjak
, José G. Delgado-Frias:
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance. 14-23 - Vincent Nollet, Prabhat Avasare, Hendrik Eeckhaut, Diederik Verkest, Henk Corporaal:
Run-Time Management of a MPSoC Containing FPGA Fabric Tiles. 24-33 - David Andrews, Ron Sass, Erik K. Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp:
Achieving Programming Model Abstractions for Reconfigurable Computing. 34-44 - Jingzhao Ou, Viktor K. Prasanna:
A Cooperative Management Scheme for Power Efficient Implementations of Real-Time Operating Systems on Soft Processors. 45-56 - Sherif Yusuf, Wayne Luk, Morris Sloman, Naranker Dulay, Emil C. Lupu, Geoffrey Brown:
Reconfigurable Architecture for Network Flow Analysis. 57-65 - Justin L. Tripp, Maya B. Gokhale, Anders A. Hansson:
A Case Study of Hardware/Software Partitioning of Traffic Simulation on the Cray XD1. 66-74 - Sami Khawam, Ioannis Nousias, Mark Milward, Ying Yi, Mark Muir, Tughrul Arslan:
The Reconfigurable Instruction Cell Array. 75-85 - Kanak Agarwal, Sani R. Nassif:
The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies. 86-97 - Irith Pomeranz, Sudhakar M. Reddy:
Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects. 98-107 - Chia-Yi Chang, Hung-Ming Chen:
Design Migration From Peripheral ASIC Design to Area-I/O Flip-Chip Design by Chip I/O Planning and Legalization. 108-112
Volume 16, Number 2, February 2008
- Toomas P. Plaks:
Guest Editorial Special Section on Configurable Computing Design-II: Hardware Level Reconfiguration. 113-114 - Paul Beckett:
A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors. 115-123 - Yan Lin, Lei He, Mike Hutton:
Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs. 124-133 - Peter Zipf:
Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays. 134-143 - Guy Gogniat, Tilman Wolf, Wayne P. Burleson, Jean-Philippe Diguet, Lilian Bossuet, Romain Vaslin:
Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective. 144-155 - Ioannis Sourdis, Dionisios N. Pnevmatikatos, Stamatis Vassiliadis:
Scalable Multigigabit Pattern Matching for Packet Inspection. 156-166 - Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna:
Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores. 167-176 - Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert:
Architectural Modifications to Enhance the Floating-Point Performance of FPGAs. 177-187 - Xinming Huang, Cao Liang, Jing Ma:
System Architecture and Implementation of MIMO Sphere Decoders on FPGA. 188-197 - William N. Chelton, Mohammed Benaissa:
Fast Elliptic Curve Cryptography on FPGA. 198-205 - Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim:
Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property. 206-209 - Saralees Nadarajah, Samuel Kotz:
Exact Distribution of the Max/Min of Two Gaussian Random Variables. 210-212
Volume 16, Number 3, March 2008
- Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger M. Goodall:
A Novel Delta Sigma Control System Processor and Its VLSI Implementation. 217-228 - Eriko Nurvitadhi, Jumnit Hong, Shih-Lien Lu:
Active Cache Emulator. 229-240 - Ruiming Chen, Hai Zhou:
Fast Estimation of Timing Yield Bounds for Process Variations. 241-248 - Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
Body Bias Voltage Computations for Process and Temperature Compensation. 249-262 - Achintya Halder, Soumendu Bhattacharya, Abhijit Chatterjee:
System-Level Specification Testing Of Wireless Transceivers. 263-276 - Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ding-Yeong Wang, Yuan-Jen Lee, Ming-Jer Kao:
Write Disturbance Modeling and Testing for MRAM. 277-288 - Hyuk-Jun Lee, Eui-Young Chung:
Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory. 289-301 - Ke Xu, Oliver Chiu-sing Choy:
A Power-Efficient and Self-Adaptive Prediction Engine for H.264/AVC Decoding. 302-313 - Srinivasa R. Sridhara, Ganesh Balamurugan, Naresh R. Shanbhag:
Joint Equalization and Coding for On-Chip Bus Communication. 314-318 - Cosmin Popa:
Improved Accuracy Pseudo-Exponential Function Generator With Applications in Analog Signal Processing. 318-321 - Youngmoon Choi, Earl E. Swartzlander Jr.:
Speculative Carry Generation With Prefix Adder. 321-326 - Sabyasachi Das, Sunil P. Khatri:
A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic. 326-331 - Shanq-Jang Ruan, Chi-Yu Wu, Jui-Yuan Hsieh:
Low Power Design of Precomputation-Based Content-Addressable Memory. 331-335
Volume 16, Number 4, April 2008
- Ian Harris, Dhiraj Pradhan:
Guest Editorial Special Section on Design Verification and Validation. 337-338 - Deepak Mathaikutty, Sreekumar V. Kodakara, Ajit Dingankar, Sandeep K. Shukla, David J. Lilja:
MMV: A Metamodeling Based Microprocessor Validation Environment. 339-352 - Panagiotis Manolios, Sudarshan K. Srinivasan:
A Refinement-Based Compositional Reasoning Framework for Pipelined Machine Verification. 353-364 - Shih-Chieh Wu, Chun-Yao Wang, Yung-Chih Chen:
Novel Probabilistic Combinational Equivalence Checking. 365-375 - Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu:
Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra. 376-387 - Jayanta Bhadra, Ekaterina Trofimova, Magdy S. Abadir:
Validating Power ArchitectureTM Technology-Based MPSoCs Through Executable Specifications. 388-396 - Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian:
IEEE Standard 1500 Compliance Verification for Embedded Cores. 397-407 - Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti, Vivekananda M. Vedula, K. S. Maneperambil:
Automatic Constraint Based Test Generation for Behavioral HDL Models. 408-421 - David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil:
Fault Emulation for Dependability Evaluation of VLSI Systems. 422-431 - Philip Y. Paik, Vamsee K. Pamula, Krishnendu Chakrabarty:
Adaptive Cooling of Integrated Circuits Using Digital Microfluidics. 432-443 - Yuh-Fang Tsai, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin:
Design Space Exploration for 3-D Cache. 444-455 - Jonggab Kil, Jie Gu, Chris H. Kim:
A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting. 456-465 - Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski:
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors. 466-475 - Eric Karl, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge:
Multi-Mechanism Reliability Modeling and Management in Dynamic Systems. 476-487 - Zhiyu Liu, Volkan Kursun:
Characterization of a Novel Nine-Transistor SRAM Cell. 488-492
Volume 16, Number 5, May 2008
- Katherine Compton, Scott Hauck:
Automatic Design of Reconfigurable Domain-Specific Flexible Cores. 493-503 - Heng Tan, Ronald F. DeMara:
A Multilayer Framework Supporting Autonomous Run-Time Partial Reconfiguration. 504-516 - Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel:
A Compact and Accurate Gaussian Variate Generator. 517-527 - Sanjukta Bhanja, Sudeep Sarkar:
Thermal Switching Error Versus Delay Tradeoffs in Clocked QCA Circuits. 528-541 - Daniele Rossi, André K. Nieuwland, Steven V. E. S. van Dijk, Richard P. Kleihorst, Cecilia Metra:
Power Consumption of Fault Tolerant Busses. 542-553 - Banit Agrawal, Timothy Sherwood:
Ternary CAM Power and Delay Model: Extensions and Uses. 554-564 - Yongmei Dai, Zhiyuan Yan, Ning Chen:
Optimal Overlapped Message Passing Decoding of Quasi-Cyclic LDPC Codes. 565-578 - Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton:
Practical Asynchronous Interconnect Network Design. 579-588 - Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen:
Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime. 589-593 - Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng:
A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic. 594-598 - John Keane, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim:
Stack Sizing for Optimal Current Drivability in Subthreshold Circuits. 598-602 - Zhenyu (Peter) Gu, Changyun Zhu, Li Shang, Robert P. Dick:
Application-Specific MPSoC Reliability Optimization. 603-608
Volume 16, Number 6, June 2008
- Diana Marculescu, Jörg Henkel:
Guest Editorial Special Section on Low-Power Electronics and Design. 609-610 - Dongsheng Ma, Feng Luo:
Robust Multiple-Phase Switched-Capacitor DC-DC Power Converter With Digital Interleaving Regulation Scheme. 611-619 - Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. 620-627 - Elham Safi, Andreas Moshovos, Andreas G. Veneris:
L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture. 628-638 - Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers. 639-649 - Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose:
Selective Writeback: Reducing Register File Pressure and Energy Consumption. 650-661 - Wonbok Lee, Kimish Patel, Massoud Pedram:
GOP-Level Dynamic Thermal Management in MPEG-2 Decoding. 662-672 - Prashant Singh, Jae-sun Seo, David T. Blaauw, Dennis Sylvester:
Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect. 673-677 - Jianwei Zhang, Yizheng Ye, Bin-Da Liu:
A Current-Recycling Technique for Shadow-Match-Line Sensing in Content-Addressable Memories. 677-682 - Azadeh Davoodi, Ankur Srivastava:
Variability Driven Gate Sizing for Binning Yield Optimization. 683-692 - Juan Carlos Baraza, Joaquin Gracia, Sara Blanc, Daniel Gil, Pedro J. Gil:
Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code. 693-706 - Rohit Singhal, Gwan Choi, Rabi N. Mahapatra:
Data Handling Limits of On-Chip Interconnects. 707-713 - Chong Zhao, Yi Zhao, Sujit Dey:
Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits. 714-724 - Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Stamatis Vassiliadis:
Test Set Development for Cache Memory in Modern Microprocessors. 725-732 - Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices. 733-744 - Kaveh Shakeri, James D. Meindl:
Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method. 745-754 - Ying-Yen Chen, Jing-Jia Liou:
Diagnosis Framework for Locating Failed Segments of Path Delay Faults. 755-765 - Sampo Tuuna, Li-Rong Zheng, Jouni Isoaho, Hannu Tenhunen:
Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid. 766-770 - Shizhong Mei:
Timing Jitter and Power Spectral Density of Random Walk Noise in VCO. 770-774 - Mohamed Anane, Hamid Bessalah, Mohamed Issad, Nadjia Anane, Hassen Salhi:
Higher Radix and Redundancy Factor for Floating Point SRT Division. 774-779
Volume 16, Number 7, July 2008
- Kieran McLaughlin, Sakir Sezer, Holger Blume, Xin Yang, Friederich Kupzog, Tobias G. Noll:
A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling. 781-791 - Deepak Mathaikutty, Sandeep K. Shukla:
MCF: A Metamodeling-Based Component Composition Framework - Composing SystemC IPs for Executable System Models. 792-805 - Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy:
Profit Aware Circuit Design Under Process Variations Considering Speed Binning. 806-815 - Brian Swahn, Soha Hassoun:
Electro-Thermal Analysis of Multi-Fin Devices. 816-829 - Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner:
Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers. 830-836 - Giorgos Dimitrakopoulos, Costas Galanopoulos, Christos Mavrokefalidis, Dimitris Nikolos:
Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units. 837-850 - Behnam Amelifard, Farzan Fallah, Massoud Pedram:
Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology. 851-860 - Shengqi Yang, Wenping Wang, Tiehan Lv, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie:
Case Study of Reliability-Aware and Low-Power Design. 861-873 - David Choi, Kyu Choi, John D. Villasenor:
New Non-Volatile Memory Structures for FPGA Architectures. 874-881 - Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arifur Rahman:
Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues. 882-893 - Mikhail Popovich, Michael Sotman, Avinoam Kolodny, Eby G. Friedman:
Effective Radii of On-Chip Decoupling Capacitors. 894-907 - Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny:
On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits. 908-921 - Xiaomeng Shi, Kiat Seng Yeo, Jianguo Ma, Manh Anh Do, Erping Li:
Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs. 922-926 - Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains. 926-931 - Irith Pomeranz, Sudhakar M. Reddy:
Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion. 931-936 - Chua-Chin Wang, Chi-Chun Huang, Jian-Ming Huang, Chih-Yi Chang, Chih-Peng Li:
ZigBee 868/915-MHz Modulator/Demodulator for Wireless Personal Area Network. 936-939
Volume 16, Number 8, August 2008
- Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta:
Satisfiability Models for Maximum Transition Power. 941-951 - Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng:
Energy-Aware Flash Memory Management in Virtual Memory System. 952-964 - Yen-Jen Chang, Yuan-Hong Liao:
Hybrid-Type CAM Design for Both Power and Performance Efficiency. 965-974 - Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow:
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing. 975-984 - Daler N. Rakhmatov:
Energy Budget Approximations for Battery-Powered Systems With a Fixed Schedule of Active Intervals. 985-998 - Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis:
Cost-Efficient SHA Hardware Accelerators. 999-1008 - Lei Wang, Niral Patel:
Improving Error Tolerance for Multithreaded Register Files. 1009-1020 - Zhonghai Lu, Axel Jantsch:
TDM Virtual-Circuit Configuration for Network-on-Chip. 1021-1034 - Pallav Gupta, Rui Zhang, Niraj K. Jha:
Automatic Test Generation for Combinational Threshold Logic Networks. 1035-1045 - Dan Zhao, Yi Wang:
MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip. 1046-1057 - Chin-Teng Lin, Yuan-Chu Yu, Lan-Da Van:
Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor. 1058-1071 - Chung-Ming Chen, Chung-Ho Chen:
Configurable VLSI Architecture for Deblocking Filter in H.264/AVC. 1072-1082 - Joshua Noseworthy, Miriam Leeser:
Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA. 1083-1090 - Miriam J. Akl, Magdy A. Bayoumi:
Transition Skew Coding for Global On-Chip Interconnect. 1091-1096 - Sammy H. M. Kwok, Edmund Y. Lam:
Effective Uses of FPGAs for Brute-Force Attack on RC4 Ciphers. 1096-1100
Volume 16, Number 9, September 2008
- Yu Wang, Ku He, Rong Luo, Hui Wang, Huazhong Yang:
Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits. 1101-1113 - Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry:
A Comparative Study Between Static and Dynamic Sleep Signal Generation Techniques for Leakage Tolerant Designs. 1114-1126 - Ayse K. Coskun, Tajana Simunic Rosing, Keith Whisnant, Kenny C. Gross:
Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs. 1127-1140