Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDITC 2003: Charlotte, NC, USA
- Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA. IEEE Computer Society 2003, ISBN 0-7803-8106-8
Plenary
- David W. Yen:
Seeing Chip Testability Through a Systems Person's Eyes. 12 - Janusz Rajski:
Test Challenges of Nanometer Technology. 13-22
Memory Testing And Diagnosis
- Jean-Michel Portal, Hassen Aziza, Didier Née:
EEPROM Memory: Threshold Voltage Built In Self Diagnosis. 23-28 - Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang:
Fault Pattern Oriented Defect Diagnosis for Memories. 29-38 - Derek Wright, Manoj Sachdev:
Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie. 39-47
Jitter Testing Techniques for > GB/S TX/RX Links
- Masashi Shimanouchi:
Periodic Jitter Injection with Direct Time Synthesis by SPPTM ATE for SerDes Jitter Tolerance Test in Production. 48-57 - Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Makoto Kurosawa, Hirobumi Musha:
Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements. 58-66 - Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz:
CMOS Built-In Test Architecture for High-Speed Jitter Measurement. 67-76
High Yield And Effective Testing And Burn-In
- Thomas S. Barnett, Adit D. Singh:
Relating Yield Models to Burn-In Fall-Out in Time. 77-84 - Yoshihito Nishizaki, Osamu Nakayama, Chiaki Matsumoto, Yoshitaka Kimura, Toshimi Kobayashi, Hiroyuki Nakamura:
Testing DSM ASIC With Static, \DeltaIDDQ, And Dynamic Test Suite: Implementation And Results. 85-94 - Oleg Semenov, Arman Vassighi, Manoj Sachdev, Ali Keshavarzi, Charles F. Hawkins:
Burn-in Temperature Projections for Deep Sub-micron Technologies. 95-104
Crosstalk And Delay Test
- Haihua Yan, Adit D. Singh:
Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die. 105-111 - Xiaoliang Bai, Sujit Dey, Angela Krstic:
HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk. 112-121 - Rahul Kundu, R. D. (Shawn) Blanton:
Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk. 122-130
Improving Design Validation Coverage
- S. R. Seward, Parag K. Lala:
Fault Injection for Verifying Testability at the VHDL Level. 131-137 - Miroslav N. Velev:
Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs. 138-147 - Amir Hekmatpour, James Coulter:
Coverage-Directed Management and Optimization of Random Functional Verification. 148-155
Lecture Series-Board And System Test: Is PXI The Future of Functional Board Test?
- Eric Starkloff, Tim Fountain, Garth Black:
The PXI Modular Instrumentation Architecture. 156-165
Pushing The Envelope of ATE
- J. S. Davis, David C. Keezer, Odile Liboiron-Ladouceur, Keren Bergman:
Application and Demonstration of a Digital Test Core: Optoelectronic Test Bed and Wafer-level Prober. 166-174 - Ahmed Rashid Syed:
RIC/DICMOS - Multi-channel CMOS Formatter. 175-184 - Maurizio Gavardoni:
Data flow within an open architecture tester. 185-190 - David C. Keezer, Dany Minier, Marie-Christine Caron:
A Production-Oriented Multiplexing System for Testing above 2.5 Gbps. 191-200
ADC Test
- Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell:
A New Methodology For ADC Test Flow Optimization. 201-209 - Gwenolé Maugard, Carsten Wegener, Tom O'Dwyer, Michael Peter Kennedy:
Method of reducing contactor effect when testing high-precision ADCs. 210-217 - Le Jin, Kumar L. Parthasarathy, Turker Kuyel, Degang Chen, Randall L. Geiger:
Linearity Testing of Precision Analog-to-Digital Converters Using Stationary Nonlinear Inputs. 218-227 - Stephen K. Sunter:
Testing High Frequency ADCs and DACs with a Low Frequency Analog Bus. 228-235
Advances in Testing And Analysis Methods
- Franco Stellari, Peilin Song, Moyra K. McManus, Robert Gauthier, Alan J. Weger, Kiran V. Chatty, Mujahid Muhammad, Pia N. Sanda:
Optical and Electrical Testing of Latchup in I/O Interface Circuits. 236-245 - Keneth R. Wilsher:
Designed -in-diagnostics: A new optical method. 246-253 - Romain Desplats, Felix Beaudoin, Philippe Perdu, Nagamani Nataraj, Ted R. Lundquist, Ketan Shah:
Fault Localization using Time Resolved Photon Emission and STIL Waveforms. 254-263 - Jeremy A. Rowlette
, Travis M. Eiles:
Critical Timing Analysis in Microprocessors Using Near-IR Laser Assisted Device Alteration (LADA). 264-273
Novel ATPG Approaches
- Vishwani D. Agrawal, A. V. S. S. Prasad, Madhusudan V. Atre:
Fault Collapsing via Functional Dominance. 274-280 - Qingwei Wu, Michael S. Hsiao:
Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal. 281-289 - Liang Zhang, Indradeep Ghosh, Michael S. Hsiao:
Efficient Sequential ATPG for Functional RTL Circuits. 290-298 - Mahesh A. Iyer:
Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation. 299-308
Advances in Diagnostics
- Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Blanton:
Progressive Bridge Identification. 309-318 - Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung:
Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault. 319-328 - Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski:
An Efficient and Effective Methodology on the Multiple Fault Diagnosis. 329-338 - Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak:
Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies. 339-348
Board And System Test: Advanced Applications of Boundary-Scan
- YongJoon Kim, DongSub Song, YongSeung Shin, Sunghoon Chun, Sungho Kang:
A New Maximal Diagnosis Algorithm for Bus-structured Systems. 349-357 - Kevin Melocco, Hina Arora, Paul Setlak, Gary Kunselman, Shazia Mardhani:
A Comprehensive Approach to Assessing and Analyzing 1149.1 Test Logic. 358-367 - Kendrick Baker:
Constructive Pattern Generation Heuristic for Meeting SSO Limits. 368 - Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen:
Optimal Interconnect ATPG Under a Ground-Bounce Constraint. 369-378
Embedded Memory BIST and Repair
- Davide Appello, Paolo Bernardi, Alessandra Fudoli, Maurizio Rebaudengo, Matteo Sonza Reorda, Vincenzo Tancorre, Massimo Violante:
Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores. 379-385 - Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, Sherry Lai:
BIST for Deep Submicron ASIC Memories with High Performance Application. 386-392 - Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow:
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. 393-402
Interface Magic
- Kranthi K. Pinjala, Bruce C. Kim, Pramodchandran N. Variyam:
Automatic Diagnostic Program Generation for Mixed Signal Load Board. 403-409 - Nobuhiro Sato, Yoshihiro Hashimoto:
A High Precision IDDQ Measurement System With Improved Dynamic Load Regulation. 410-414
Test And Verification For Cores And SOCS
- Tomokazu Yoneda, Tetsuo Uchiyama, Hideo Fujiwara:
Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability. 415-422 - Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris:
Extraction Error Diagnosis and Correction in High-Performance Designs. 423-430 - Nektarios Kranitis, George Xenoulis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian:
Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores. 431-440
Keep Compressing This Test Data!
- Irith Pomeranz:
Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan Chains. 441-450 - Armin Würtenberger, Christofer S. Tautermann, Sybille Hellebrand:
A Hybrid Coding Strategy For Optimized Test Data Compression. 451-459 - Lei Li, Krishnendu Chakrabarty:
Deterministic BIST Based on a Reconfigurable Interconnection Network. 460-469
Low-Power Scan
- Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang:
Double-Tree Scan: A Novel Low-Power Scan-Path Architecture. 470-479 - Takaki Yoshida, Masafumi Watari:
A New Approach for Low Power Scan Testing. 480-487 - Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. 488-493
Lecture Series-Board And System Test: IEEE 1149.6-A Practical Perspective
- Bill Eklow, Carl Barnhart, Mike Ricchetti, Terry Borroz:
IEEE 1149.6 - A Practical Perspective. 494-502
Extremely Low-Cost Testers
- Kenneth E. Posse, Geir Eide:
Key Impediments to DFT-Focused Test and How to Overcome Them. 503-511 - George Bao:
Challenges in Low Cost Test Approach for ARM9TM Core Based Mixed-Signal SoC DragonBallTM-MX1. 512-519 - Michael A. Jones:
Ultra Low Cost Linear Testing. 520-527
Application Series-Developing Test Interfaces
- Jie Sun, Mike Li:
A Generic Test Path and DUT Model for DataCom ATE. 528-536 - Thomas P. Warwick:
Mitigating the Effects of The DUT Interface board and Test System Parasitics in Gigabit-Plus Measurements. 537-544
Practical Application of IDDQ
- Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota:
Test Vector Generation Based on Correlation Model for Ratio-Iddq. 545-554 - Yukio Okuda, Nobuyuki Furukawa:
Hysteresis of Intrinsic IDDQ Currents. 555-564 - Chris Schuermyer, Brady Benware, Kevin Cota, Robert Madge, W. Robert Daasch, L. Ning:
Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ. 565-573
Delay Test
- Seongmoon Wang, Srimat T. Chakradhar:
A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs. 574-583 - Puneet Gupta, Michael S. Hsiao:
High Quality ATPG for Delay Defects. 584-591 - Wangqi Qiu, D. M. H. Walker:
An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit. 592-601
Optimizing Efficiency in SOC Testing
- Ozgur Sinanoglu, Alex Orailoglu:
Modeling Scan Chain Modifications For Scan-in Test Power Minimization. 602-611 - Érika F. Cota, Luigi Carro, Flávio Rech Wagner, Marcelo Lubaszewski:
Power-aware NoC Reuse on the Testing of Core-based Systems. 612-621 - Qiang Xu, Nicola Nicolici:
On Reducing Wrapper Boundary Register Cells in Modular SOC Testing. 622-631
Board And System Test: AC-Interconnect Board Test Techniques
- Suzette Vandivier, Mark Wahl, Jeff Rearick:
First IC Validation of IEEE Std. 1149.6. 632-639 - Ivan Duzevik:
Design and Implementation of IEEE 1149.6. 640 - Lee Whetsel:
Adapting JTAG for AC Interconnect Testing. 641-650
RF Testing
- José Pineda de Gyvez, Guido Gronthoud, Rashid Amine:
VDD Ramp Testing for RF Circuits. 651-658 - Iboun Taimiya Sylla:
Building An RF Source For Low Cost Testers Using An ADPLL Controlled By Texas Instruments Digital Signal Processor (DSP) TMS320C5402. 659-664 - Achintya Halder, Soumendu Bhattacharya, Abhijit Chatterjee:
Automatic Multitone Alternate Test Generation For RF Circuits Using Behavioral Models. 665-673
Lecture Series-Introduction to MEMS
- Jeremy A. Walraven:
Introduction to Applications and Industries for Microelectromechanical Systems (MEMS). 674-680 - Tamal Mukherjee:
MEMS Design And Verification. 681-690 - Gary K. Fedder:
MEMS Fabrication. 691-698
Application of IDDX
- Wanli Jiang, Eric Peterson, Bob Robotka:
Effectiveness Improvement of ECR Tests. 699-708 - Dhruva Acharyya, Jim Plusquellic:
Impedance Profile of a Commercial Power Grid and Test System. 709-718 - Bartomeu Alorda, Brad Bloechel, Ali Keshavarzi, Jaume Segura:
CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing. 719-726
Logic BIST
- Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin:
X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture. 727-736 - Ramesh C. Tekumalla:
On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures. 737-744 - Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy:
Convolutional Compaction of Test Responses. 745-754
Microprocessor Test
- Peter Dahlgren, Paul Dickinson, Ishwar Parulkar:
Latch Divergency In Microprocessor Failure Analysis. 755-763 - Scott Erlanger, Dilip K. Bhavsar, Richard A. Davies:
Testability Features of the Alpha 21364 Microprocessor. 764-772 - Teresa L. McLaurin, Frank Frederick, Rich Slobodnik:
The Testability Features of The ARM1026EJ Microprocessor Core. 773-782
Board And System Test: Advances in Testing Microprocessor Motherboards
- Jay J. Nejedlo:
TRIBuTETM Board and Platform Test Methodology: Intel's Next-Generation Test and Validation Methodology for Platforms. 783 - Jay J. Nejedlo:
IBISTTM (Interconnect Built-in Self-Test) Architecture and Methodology for PCI Express: Intel?s Next-Generation Test and Validation Methodology for Performance IO. 784 - Leon van de Logt, Frank van der Heyden, Tom Waayers:
An extension to JTAG for at-speed debug on a system. 785-792
Latest Developments in ATE Software
- A. T. Sivaram, Daniel Fan, Jon Pryce:
XML And Java For Open ATE Programming Environment. 793-801 - Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Luca Tagliaferri:
Data Critically Estimation In Software Applications. 802-810 - Daniel Fan, Steve Roehling, Rusty Carruth:
Case Study - Using STIL as Test Pattern Language. 811-817 - Paul Buxton, Paul Tabor:
Outlier Detection for DPPM Reduction. 818-827
Lecture Series-MEMS Testing
- Jeremy A. Walraven:
Failure Mechanisms in MEMS. 828-833 - Jeremy A. Walraven:
Tools and Techniques for Failure Analysis and Qualification of MEMS. 834-842 - Theresa Maudie, Alex Hardt, Rick Nielsen, Dennis Stanerson, Ron Bieschke, Mike Miller:
MEMS Manufacturing Testing: An Accelerometer Case Study. 843-849 - Jeremy A. Walraven:
Future Challenges for MEMS Failure Analysis. 850-855
Failure Mechanisms And Test Solutions For DSM ICS
- Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey:
Deformations of IC Structure in Test and Yield Learning. 856-865 - Bram Kruseman, Stefan van den Oetelaar:
Detection of Resistive Shorts in Deep Sub-micron Technologies. 866-875 - R. D. (Shawn) Blanton, Kumar N. Dwarakanath, Anirudh B. Shah:
Analyzing the Effectiveness of Multiple-Detect Test Sets. 876-885 - Martin Omaña, Daniele Rossi, Cecilia Metra:
Novel Transient Fault Hardened Static Latch. 886-892
Can Concurrent Detection Be Achieved At Low Cost?
- Kartik Mohanram, Nur A. Touba:
Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. 893-901 - Kaijie Wu, Ramesh Karri:
Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis. 902-911 - B. Kiran Kumar, Parag K. Lala:
On-line Detection of Faults in Carry-Select Adders. 912-918 - Ramesh Karri, Grigori Kuznetsov, Michael Gössel:
Parity-Based Concurrent Error Detection in Symmetric Block Ciphers. 919-926
Test Economics
- Hamidreza Hashempour, Fred J. Meyer, Fabrizio Lombardi, Farzin Karimi:
Hybrid Multisite Testing at Manufacturing. 927-936 - Zhen Shi, Peter Sandborn:
Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic Systems Assembly Using Real-Coded Genetic Algorithms. 937-946 - Burnell G. West:
Simultaneous Bidirectional Test Data Flow for a Low-cost Wafer Test Strategy. 947-951
Board And System Test: Testing Multiboard Systems
- Liviu Miclea, Szilárd Enyedi, Gavril Toderean, Alfredo Benso, Paolo Prinetto:
Agent Based DBIST/DBISR And Its Web/Wireless Management. 952-960 - Olivier Caty, Ismet Bayraktaroglu, Amitava Majumdar, Richard Lee, John Bell, Lisa Curhan:
Instruction Based BIST for Board/System Level Test of External Memories and Internconnects. 961-970 - Hardi Hungar, Tiziana Margaria, Bernhard Steffen:
Test-Based Model Generation For Legacy Systems. 971-980 - Rakesh N. Joshi, Kenneth L. Williams, Lee Whetsel:
Evolution of IEEE 1149.1 Addressable Shadow Protocol Devices. 981-987
Lecture Series-P1500 Mergeable Cores
- Francisco DaSilva, Yervant Zorian, Lee Whetsel, Karim Arabi, Rohit Kapur:
Overview of the IEEE P1500 Standard. 988-997 - Michael G. Wahl, Sudipta Bhawmik, Kamran Zarrineh, Pradipta Ghosh, Scott Davidson, Peter Harrod:
The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data. 998-1007
I/O Testing-Probe or Not?
- Kenichi Kataoka, Toshihiro Itoh, Tadatomo Suga:
Low Contact-Force Fritting Probe Card Using Buckling Microcantilevers. 1008-1013 - Mike Tripp, T. M. Mak, Anne Meixner:
Elimination of Traditional Functional Testing of Interface Timings at Intel. 1014-1022 - Cheng Jia, Linda S. Milor:
A BIST Solution for The Test of I/O Speed. 1023-1030