default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDDATE 2002: Paris, France
- 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France. IEEE Computer Society 2002, ISBN 0-7695-1471-5
Plenary - Keynote Session
- Hugo De Man:
On Nanoscale Integration and Gigascale Complexity in the Post.Com World. 12 - Taylor Scanlon:
Global Responsibilities in SOC Design. 12
How to Choose Semiconductor IP?
- Ian Phillips:
How to Choose Semiconductor IP? - Embedded Processor. 14 - Vincent Ratford:
Make Your SoC Design a Winner: Select the Right Memory IP. 15 - Grant Martin:
How to Choose Semiconductor IP: Embedded Software. 16 - Pierre Bricaud:
IP Day: How to Choose Semiconductor IP? 17
Formal Verification of Complex Designs
- Roope Kaivola, Naren Narasimhan:
Formal Verification of the Pentium ® 4 Floating-Point Multiplier. 20-27 - Miroslav N. Velev
:
Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer. 28-35 - Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama:
Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. 36-43 - Marco A. Peña, Jordi Cortadella, Alexander B. Smirnov, Enric Pastor:
A Case Study for the Verification of Complex Timed Circuits: IPCMOS. 44-51
Cooling Layout Arrangements
- Juan de Vicente, Juan Lanchares, Román Hermida:
FPGA Placement by Thermodynamic Combinatorial Optimization. 54-60 - Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin:
An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees. 61-68 - Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang:
Arbitrary Convex and Concave Rectilinear Module Packing Using TCG. 69-75
Defect Oriented Test
- Michael Pronath, Helmut E. Graeb, Kurt Antreich:
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits. 78-83 - Saravanan Padmanaban, Spyros Tragoudas:
Exact Grading of Multiple Path Delay Faults. 84-88 - Zaid Al-Ars, Ad J. van de Goor:
Modeling Techniques and Tests for Partial Faults in Memory Devices. 89-93 - Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael R. Grimaila, M. Ray Mercer:
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults. 94-99
Power Analysis and Management in Networks and Processors
- Davide Bertozzi, Luca Benini, Giovanni De Micheli:
Low Power Error Resilient Encoding for On-Chip Data Buses. 102-109 - Tajana Simunic, Stephen P. Boyd:
Managing Power Consumption in Networks on Chip. 110-116 - Sandy Irani, Rajesh K. Gupta, Sandeep K. Shukla:
Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States. 117-123 - Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose:
AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors. 124-129
Panel - What is the Right IP Business Model?
- Vernon P. Essi Jr.:
IP is All About Implementation and Customer Satisfaction. 132
SAT and BDD Techniques
- Evguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton:
Using Problem Symmetry in Search Based Satisfiability Algorithms. 134-141 - Evguenii I. Goldberg, Yakov Novikov:
BerkMin: A Fast and Robust Sat-Solver. 142-149 - Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Dynamic Scheduling and Clustering in Symbolic Image Computation. 150-156
Technology and Interconnect Issues in Low Power Design
- Luca Macchiarulo, Enrico Macii, Massimo Poncino:
Wire Placement for Crosstalk Energy Minimization in Address Buses. 158-162 - Chris H. Kim, Kaushik Roy:
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction. 163-167 - Ana Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau:
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints. 168-175 - Arindam Mukherjee, Kai Wang, Lauren Hui Chen, Malgorzata Marek-Sadowska:
Sizing Power/Ground Meshes for Clocking and Computing Circuit Components. 176-183
Advanced Mixed Signal Test
- Ramakrishna Voorakaranam, Sasikumar Cherubal, Abhijit Chatterjee:
A Signature Test Framework for Rapid Production Testing of RF Circuits. 186-191 - Carlo Guardiani, Patrick McNamara, Lidia Daldoss, Sharad Saxena, Stefano Zanella, Wei Xiang, Suli Liu:
Analog IP Testing: Diagnosis and Optimization. 192-196 - Christoph Hoffmann:
A New Design Flow and Testability Measure for the Generation of a Structural Test and BIST for Analogue and Mixed-Signal Circuits. 197-204 - Yolanda Lechuga, Román Mozuelos, Mar Martínez, Salvador Bracho:
Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal Ics. 205-211
Collaborative Design
- L. Ghanmi, A. Ghrab, M. Hamdoun, B. Missaoui, K. Skiba, Gabriele Saucier:
E-Design Based on the Reuse Paradigm. 214-220 - André Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová:
Internet-Based Collaborative Test Generation with MOSCITO. 221-226 - Tom J. Kazmierski, Neil Clayton:
A Two-Tier Distributed Electronic Design Framework. 227-231 - Achim Rettberg, Wolfgang Thronicke:
Embedded System Design Based On Webservices. 232-236
Panel - Who Owns the Platform?
- Vassilios Gerousis, Oz Levia, Pierre G. Paulin, Mark Pinto, Chris Rowen, Gabriele Saucier:
Who Owns the Platform? 238
Embedded Tutorial - The Need for Infrastructure IP in SoCs
- Michael Nicolaidis:
IP for Embedded Robustness. 240-241 - Stephen Pateras:
Embedded Diagnosis IP. 242-243 - Eric Dupont, Michael Nicolaidis, Peter Rohr:
Embedded Robustness Ips. 244-245
Advances in Logic Synthesis
- Sezer Gören, F. Joel Ferguson:
CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines. 248-254 - Mitchell A. Thornton, Kenneth Fazel, Robert B. Reese, Cherrice Traver:
Generalized Early Evaluation in Self-Timed Circuits. 255-259 - Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. 260-265
Novel Applications of Symbolic Techniques to Analogue and Digital Circuit Design
- Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics. 268-273 - Ralf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke:
Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. 274-278 - Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices. 279-284 - Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre:
Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. 285-289
EDA Tools for RF: Myth or Reality?
- EDA Tools for RF: Myth or Reality? 292-293
Platform-Based Design and Virtual-Component Reuse
- Tin-Man Lee, Wayne H. Wolf, Jörg Henkel:
Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based Designs. 296-301 - Robert Pasko, Serge Vernalde, Patrick Schaumont:
Techniques to Evolve a C++ Based System Design Language. 302-309 - Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda, Ralf Seepold, Natividad Martínez Madrid:
A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects. 310-314
Analogue Circuit Characterisation and Simulation
- Wenceslas Rahajandraibe, Christian Dufaza, Daniel Auvergne, Bruno Cialdella, Bernard Majoux, Vivek Chowdhury:
Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications. 316-321 - S. Lampe, S. Laur:
Global Optimization Applied to the Oscillator Problem. 322-326
Panel - MEDEA+ and ITRS Roadmaps
- Joseph Borel, Gérard Matheron, Ahmed Amine Jerraya, S. Resve, M. Rogers, Wolfgang Rosenstiel, Irmtraud Rugen-Herzig, F. Theewen:
MEDEA+ and ITRS Roadmaps. 328
Asynchronous Circuits and Clock Scheduling
- Tiberiu Chelcea, Steven M. Nowick, Andrew Bardsley, Doug A. Edwards:
A Burst-Mode Oriented Back-End for the Balsa Synthesis System. 330-337 - Victor Khomenko, Maciej Koutny, Alexandre Yakovlev:
Detecting State Coding Conflicts in STGs Using Integer Programming. 338-345 - Soha Hassoun, Eduardo H. Calvillo Gámez, Christopher Cromer:
Verifying Clock Schedules in the Presence of Cross Talk. 346-350
Analogue and Mixed-Signal Systems
- Michaël Goffioul, Piet Wambacq, Gerd Vandersteen, Stéphane Donnay:
Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach . 352-356 - Jan Vandenbussche, Erik Lauwers, Koen Uyttenhove, Michiel Steyaert, Georges G. E. Gielen:
Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter. 357-361 - Ricardo Carmona-Galán, Francisco Jiménez-Garrido, Rafael Domínguez-Castro, Servando Espejo-Meana, Ángel Rodríguez-Vázquez:
Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip. 362-366
BIST Diagnosis and DFT
- Amit R. Pandey, Janak H. Patel:
An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs. 368-375 - Ismet Bayraktaroglu, Alex Orailoglu:
Gate Level Fault Diagnosis in Scan-Based BIST. 376-381 - Chunsheng Liu, Krishnendu Chakrabarty, Michael Gössel:
An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment. 382-386 - Sherief Reda, Alex Orailoglu:
Reducing Test Application Time Through Test Data Mutation Encoding. 387-393
Code and Memory Optimization in Co-Design
- Heiko Michel, Alexander Worm, Norbert Wehn, Michael Münch:
Hardware/Software Trade-Offs for Advanced 3G Channel Coding. 396-401 - Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil D. Dutt, Alexandru Nicolau:
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs. 402-408 - Stefan Steinke, Lars Wehmeyer, Bo-Sik Lee, Peter Marwedel:
Assigning Program and Data Objects to Scratchpad for Energy Reduction. 409-415
Network on a Chip
- Giovanni De Micheli, Luca Benini:
Networks on Chip: A New Paradigm for Systems on Chip Design. 418-419 - Joseph Williams, Nevin Heintze, Bryan D. Ackland:
Communication Mechanisms for Parallel DSP Systems on a Chip. 420-422 - Kees Goossens, Paul Wielage, Ad M. G. Peeters, Jef L. van Meerbergen:
Networks on Silicon: Combining Best-Effort and Guaranteed Services. 423-425
Low Power Architectures and Software
- Tanja Van Achteren, Geert Deconinck, Francky Catthoor, Rudy Lauwereins:
Data Reuse Exploration Techniques for Loop-Dominated Application. 428-435 - Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam:
EAC: A Compiler Framework for High-Level Energy Estimation and Optimization. 436-442 - Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau:
Power Savings in Embedded Processors through Decode Filer Cache. 443-448 - Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii:
Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors. 449-453
Nitty Gritty Details of Layout Design
- Murat R. Becer, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj:
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . 456-463 - Goeran Jerke, Jens Lienig:
Hierarchical Current Density Verification for Electromigration Analysis in Arbitrary Shaped Metallization Patterns of Analog Circuits. 464-469 - Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu:
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. 470-475
SoC and System Test
- Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu:
Test Planning and Design Space Exploration in a Core-Based Environment. 478-485 - Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin:
A Hierarchical Test Scheme for System-On-Chip Designs. 486-490 - Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Efficient Wrapper/TAM Co-Optimization for Large SOCs. 491-498 - Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei:
Beyond UML to an End-of-Line Functional Test Engine. 499-503
Modelling and Synthesis of Embedded Systems
- Kai Richter, Rolf Ernst:
Event Model Interfaces for Heterogeneous System Analysis. 506-513 - Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles:
Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems. 514-521 - JoAnn M. Paul, Donald E. Thomas:
A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems. 522-528 - Daniel Ménard, Olivier Sentieys:
Automatic Evaluation of the Accuracy of Fixed-Point Algorithms. 529-535
Panel - Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs
- K. Brock, C. Edwards, R. Lannoo, Ulf Schlichtmann, Antun Domic, Jacques Benkoski, David Overhauser, M. Kliment:
Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs. 538
Reconfigurable Architectures
- Davide Rizzo, Osvaldo Colavin:
A Video Compression Case Study on a Reconfigurable VLIW Architecture. 540-546 - Marcos Sánchez-Élez, Milagros Fernández, Rafael Maestre, Román Hermida, Nader Bagherzadeh, Fadi J. Kurdahi:
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures. 547-552 - Gilles Sassatelli, Lionel Torres, Pascal Benoit, Thierry Gil, Camille Diou, Gaston Cambon, Jérôme Galy:
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications. 553-558 - Jürgen Teich, Markus Köster:
(Self-)reconfigurable Finite State Machines: Theory and Implementation. 559-566
Analogue Modelling, Layout and Sizing
- Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi:
A Linear-Centric Simulation Framework for Parametric Fluctuations. 568-575 - Mohamed Dessouky, DiaaEldin Sayed:
Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio. 576-580 - Robert Schwencker, Frank Schenkel, Michael Pronath, Helmut E. Graeb:
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets. 581-585 - Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Frans Verbeyst:
High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions. 586-590
Test Resource Partitioning for Embedded Cores
- Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian:
Effective Software Self-Test Methodology for Processor Cores. 592-597 - Anshuman Chandra, Krishnendu Chakrabarty:
Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression. 598-603 - Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici:
Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression. 604-611 - Michele Favalli, Cecilia Metra:
Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths. 612-617
System Level Simulation and Modelling
- Sungjoo Yoo, Gabriela Nicolescu, Lovic Gauthier, Ahmed Amine Jerraya:
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design. 620-627 - Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter:
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses. 628-633 - Peng Li, Lawrence T. Pileggi:
A Linear-Centric Modeling Approach to Harmonic Balance Analysis. 634-639 - Paul I. Pénzes, Alain J. Martin:
An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor. 640-647
Deep Submicron Design and Timing Closure
- Ralph H. J. M. Otten, Raul Camposano, Patrick Groeneveld:
Design Automation for Deepsubmicron: Present and Future. 650-657
Reconfigurable SoC - What Will it Look Like?
- J. Bryan Lewis, Ivo Bolsens, Rudy Lauwereins, Chris Wheddon, Bhusan Gupta, Yankin Tanurhan:
Reconfigurable SoC - What Will it Look Like? 660-662
Layout Aware Logic Synthesis
- Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas:
Congestion-Aware Logic Synthesis. 664-671 - Thomas Kutzschebauch, Leon Stok:
Layout Driven Decomposition with Congestion Consideration. 672-676 - Kolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Lukas P. P. P. van Ginneken:
Improving Placement under the Constant Delay Model. 677-682 - Tzyy-Kuen Tien, Tong-Kai Tsai, Shih-Chieh Chang:
Crosstalk Alleviation for Dynamic PLAs. 683-687
Buffering and Tapering
- Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao:
Flip-Flop and Repeater Insertion for Early Interconnect Planning. 690-695 - Wai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Young:
Congestion Estimation with Buffer Planning in Floorplan Design. 696-701 - Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao:
Maze Routing with Buffer Insertion under Transition Time Constraints. 702-707 - Li Ding, Pinaki Mazumder:
Optimal Transistor Tapering for High-Speed CMOS Circuits. 708-713