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ORCID43rd DAC 2006: San Francisco, CA, USA
- Ellen Sentovich:
Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006. ACM 2006, ISBN 1-59593-381-6
Session 1: Panel
- Thomas Hartung, Jim Kupec, Ana Hunter, Brad Paulsen, Felicia James, Nick Yu:
How will the fabless model survive? 1-2
Session 2: special session: why doesn't my system work?
- Doug Josephson:
The good, the bad, and the ugly of silicon debug. 3-6 - Miron Abramovici, Paul Bradley, Kumar N. Dwarakanath, Peter Levin, Gérard Memmi
, Dave Miller:
A reconfigurable design-for-debug infrastructure for SoCs. 7-12 - Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang:
Visibility enhancement for silicon debug. 13-18
Session 3: hierarchical synthesis for mixed-signal designs
- Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann:
A CPPLL hierarchical optimization methodology considering jitter, power and locking time. 19-24 - Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen:
Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard. 25-30 - Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar:
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration. 31-36
Session 4: processor and communication centric SOC design
- Tadaaki Tanimoto, Seiji Yamaguchi, Akio Nakata, Teruo Higashino:
A real time budgeting method for module-level-pipelined bus based system using bus scenarios. 37-42 - Ramkumar Jayaseelan, Haibin Liu, Tulika Mitra:
Exploiting forwarding to improve data bandwidth of instruction-set extensions. 43-48 - Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt:
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies. 49-52 - Xinping Zhu, Wei Qin:
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery. 53-56
Session 5: practical applications of DFM
- Kanak Agarwal, Sani R. Nassif:
Statistical analysis of SRAM cell stability. 57-62 - Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah:
Criticality computation in parameterized statistical timing. 63-68 - Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif:
Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events. 69-72 - Jie Yang, Ethan Cohen, Cyrus Tabery, Norma Rodriguez, Mark Craig:
An up-stream design auto-fix flow for manufacturability enhancement. 73-76
DAC technologist panel
- Gadi Singer, Philippe Magarshack, Dennis Buss, Fu-Chieh Hsu, Ho-Kyu Kang:
"The IC nanometer race -- what will it take to win?". 77-78
Session 7: special session: bridging the system to RTL verification gap
- David Brier, Raj S. Mitra:
Use of C/C++ models for architecture exploration and verification of DSPs. 79-84 - Alistair C. Bruce, M. M. Kamal Hashmi, Andrew Nightingale, Steve Beavis, Nizar Romdhane, Christopher K. Lennard:
Maintaining consistency between systemC and RTL system designs. 85-89 - Stuart Swan:
SystemC transaction level models and RTL verification. 90-92 - Philippe Georgelin, Venkat Krishnaswamy:
Towards a C++-based design methodology facilitating sequential equivalence checking. 93-96
Session 8: leakage, power analysis and optimization
- Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram:
Charge recycling in MTCMOS circuits: concept and analysis. 97-102 - Xin Li, Jiayong Le, Lawrence T. Pileggi:
Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions. 103-108 - Hyung-Ock Kim, Youngsoo Shin, Hyuk Kim, Iksoo Eo:
Physical design methodology of power gating circuits for standard-cell-based design. 109-112 - Kaijian Shi, David Howard:
Challenges in sleep transistor design and implementation in low-power designs. 113-116 - Lei Cheng, Liang Deng, Deming Chen, Martin D. F. Wong:
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. 117-120 - De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh:
Timing driven power gating. 121-124
Session 9: MPSOC design methodologies and applications
- Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev:
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration. 125-130 - Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle:
An automated, reconfigurable, low-power RFID tag. 131-136 - Hyung Gyu Lee, Ümit Y. Ogras, Radu Marculescu, Naehyuck Chang:
Design space exploration and prototyping for on-chip multimedia applications. 137-142 - Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen:
Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs. 143-148
Session 10: statistical timing analysis
- Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir:
Refined statistical static timing analysis through. 149-154 - Jaskirat Singh, Sachin S. Sapatnekar:
Statistical timing analysis with correlated non-gaussian parameters using independent component analysis. 155-160 - Wei-Shen Wang, Vladik Kreinovich, Michael Orshansky:
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty. 161-166 - Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar:
Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools. 167-172 - Ron Wilson, Yervant Zorian:
Decision-making for complex SoCs in consumer electronic products. 173
Panel
- Andrew Yang, Rajit Chandra, Simon Burke, Javier A. DeLaCruz, Sribalan Santhanam, Uming Ko:
Entering the hot zone - can you handle the heat and be cool? 174-175
Session 12: Special Session: reliability challenges for 65NM and beyond
- J. W. McPherson:
Reliability challenges for 45nm and beyond. 176-181 - Zhihong Liu, Bruce McGaughy, James Z. Ma:
Design tools for reliability analysis. 182-187 - Uday Reddy Bandi, Murty Dasaka, Pavan K. Kumar:
Design in reliability for communication designs. 188-192 - Thomas Pompl, Christian Schlünder, Martina Hommel, Heiko Nielen, Jens Schneider:
Practical aspects of reliability analysis for IC designs. 193-198
Session 13: power grid analysis and design
- Sanjay Pant, Eli Chiprout:
Power grid physics and implications for CAD. 199-204 - Hao Yu, Yiyu Shi, Lei He:
Fast analysis of structured power grid by triangularization based structure preserving model order reduction. 205-210 - Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda:
Stochastic variational analysis of large power grids considering intra-die correlations. 211-216 - Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu:
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming. 217-222
Session 14: advances in formal solvers
- Ziv Nevo, Monica Farkash:
Distributed dynamic BDD reordering. 223-228 - Qi Zhu, Nathan Kitchen, Andreas Kuehlmann, Alberto L. Sangiovanni-Vincentelli:
SAT sweeping with local observability don't-cares. 229-234 - Chao Wang, Aarti Gupta, Malay K. Ganai:
Predicate learning and selective theory deduction for a difference logic solver. 235-240 - Vishnu C. Vimjam, Michael S. Hsiao:
Fast illegal state identification for improving SAT-based induction. 241-246
Session 15: gate modeling and model order reduction
- Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout:
A multi-port current source model for multiple-input switching effects in CMOS library cells. 247-252 - Hanif Fatemi, Shahin Nazarian, Massoud Pedram:
Statistical logic cell delay analysis using a current-based model. 253-256 - Ngai Wong, Venkataramanan Balakrishnan:
Multi-shift quadratic alternating direction implicit iteration for high-speed positive-real balanced truncation. 257-260 - N. Wong, C. K. Chu:
A fast passivity test for descriptor systems via structure-preserving transformations of Skew-Hamiltonian/Hamiltonian matrix pencils. 261-266 - Peng Li, Weiping Shi:
Model order reduction of linear networks with massive ports via frequency-dependent port packing. 267-272 - Nic Mokhoff, Yervant Zorian:
Tradeoffs and choices for emerging SoCs in high-end applications. 273
Session 16: special session: MPSOC design tools
- Grant Martin:
Overview of the MPSoC design challenge. 274-279 - Ahmed Amine Jerraya, Aimen Bouchhima, Frédéric Pétrot:
Programming models and HW-SW interfaces abstraction for multi-processor SoC. 280-285 - Peter Flake, Simon J. Davidmann, Frank Schirrmeister:
System-level exploration tools for MPSoC designs. 286-287
Session 17: special session - highlights of ISSCC: multimedia
- Tsu-Ming Liu, Ching-Che Chung, Chen-Yi Lee, Ting-An Lin, Sheng-Zen Wang:
Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications. 288-289 - Jyh-Shin Pan, Hao-Cheng Chen, Bing-Yu Hsieh, Hong-Ching Chen, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan Liu, Lily Huang, Chang-Long Wu, Meng-Hsueh Lin, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Hsiu-Chen Peng, Peng-Chuan Huang, Benjamin Chiu, Alex Ho:
A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications. 290-291 - Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno:
Hierarchical power distribution and power management scheme for a single chip mobile processor. 292-295
Session 18: buffer insertion
- Mandar Waghmode, Zhuo Li, Weiping Shi:
Buffer insertion in large circuits with constructive solution search techniques. 296-301 - Yuantao Peng, Xun Liu:
Low-power repeater insertion with both delay and slew rate constraints. 302-307 - Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze:
Fast algorithms for slew constrained minimum cost buffering. 308-313
Session 19: testing and validation for timing defects
- Vikram Iyengar, Gary Grise, Mark Taylor:
A flexible and scalable methodology for GHz-speed structural test. 314-319 - Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram:
Timing-based delay test for screening small delay defects. 320-325 - Amitava Majumdar, Wei-Yu Chen, Jun Guo:
Hold time validation on silicon and the relevance of hazards in timing analysis. 326-331
Session 20: advanced topics in processor and system verification
- Alon Gluska:
Practical methods in coverage-oriented verification of the merom microprocessor. 332-337 - Kanna Shimizu, Sanjay Gupta, Tatsuya Koyama, Takashi Omizo, Jamee Abdulhafiz, Larry McConville, Todd Swanson:
Verification of the cell broadband engineTM processor. 338-343 - Ilya Wagner, Valeria Bertacco, Todd M. Austin:
Shielding against design flaws with field repairable control logic. 344-347 - Amir Nahir, Avi Ziv, Roy Emek, Tal Keidar, Nir Ronen:
Scheduling-based test-case generation for verification of multimedia SoCs. 348-351
Session 21: software for real-time applications
- Xiangrong Zhou, Peter Petrov:
Rapid and low-cost context-switch through embedded processor customization for real-time and control applications. 352-357 - Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, Ting Chen:
Efficient detection and exploitation of infeasible paths for software timing analysis. 358-363 - Po-Kuan Huang, Soheil Ghiasi:
Leakage-aware intraprogram voltage scaling for embedded processors. 364-369
Session 22: panel
- Anoosh Hosseini, Ashish Parikh, H. T. Chin, Pascal Urard, Emil F. Girczyc, S. Bloch:
Building a standard ESL design and verification methodology: is it just a dream? 370-371
Session 23: invited session
- Andrew B. Kahng:
CAD challenges for leading-edge multimedia designs. 372
Session 24: routing
- Minsik Cho, David Z. Pan:
BoxRouter: a new global router based on box expansion and progressive ILP. 373-378 - Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li:
Steiner network construction for timing critical nets. 379-384 - Yiyu Shi, Paul Mesa, Hao Yu, Lei He:
Circuit simulation based obstacle-aware Steiner routing. 385-388 - Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang:
Timing-driven Steiner trees are (practically) free. 389-392
Session 25: the test bin
- Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi:
Systematic software-based self-test for pipelined processors. 393-398 - Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
A test pattern ordering algorithm for diagnosis with truncated fail data. 399-404 - Ahmad A. Al-Yamani:
DFT for controlled-impedance I/O buffers. 405-410
Session 26: panel
- Sani R. Nassif, Vijay Pitchumani, Norma Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic:
Variation-aware analysis: savior of the nanometer era? 411-412
Session 27: low power and ultra-low voltage design
- Hari Ananthan, Kaushik Roy:
A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS. 413-418 - Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri:
A PLA based asynchronous micropipelining approach for subthreshold circuit design. 419-424 - John Keane, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim:
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. 425-428 - Huaizhi Wu, Martin D. F. Wong, I-Min Liu:
Timing-constrained and voltage-island-aware voltage assignment. 429-432
Session 28: high-level exploration and optimization
- Jason Cong, Zhiru Zhang:
An efficient and versatile scheduling algorithm based on SDC formulation. 433-438 - Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu:
Register binding for clock period minimization. 439-444 - Ajay Kumar Verma, Paolo Ienne:
Towards the automatic exploration of arithmetic-circuit architectures. 445-450 - Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner:
Design space exploration using time and resource duality with the ant colony optimization. 451-454 - Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda:
Rapid estimation of control delay from high-level specifications. 455-458
Session 29: panel design challenges for next-generation multimedia, game and entertainment platforms
- John M. Cohn, Jeong-Taek Kong, Chris Malachowsky, Rich Tobias, Brendan Traw:
Design challenges for next-generation multimedia, game and entertainment platforms. 459
Session 30: CAD for FPGAS
- Padmini Gopalakrishnan, Xin Li, Lawrence T. Pileggi:
Architecture-aware FPGA placement using metric embedding. 460-465 - Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan:
Efficient SAT-based Boolean matching for FPGA technology mapping. 466-471 - Joey Y. Lin, Deming Chen, Jason Cong:
Optimal simultaneous mapping and clustering for FPGA delay optimization. 472-477 - Yu Hu, Yan Lin, Lei He, Tim Tuan:
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. 478-483
Session 31: secure systems
- Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro:
VIRTUS: a new processor virtualization architecture for security-oriented next-generation mobile terminals. 484-489 - Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang:
A network security processor design based on an integrated SOC design and test platform. 490-495 - Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar:
Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. 496-501 - Roshan G. Ragel, Sri Parameswaran:
IMPRES: integrated monitoring for processor reliability and security. 502-505 - Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez:
A parallelized way to provide data encryption and integrity checking on a processor-memory bus. 506-509
Session 32: logic synthesis I
- Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske:
Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. 510-515 - Kuo-Hua Wang:
Exploiting K-Distance Signature for Boolean Matching and G-Symmetry Detection. 516-521 - Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky:
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty. 522-527 - Brian Swahn, Soha Hassoun:
Gate sizing: finFETs vs 32nm bulk MOSFETs. 528-531 - Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton:
DAG-aware AIG rewriting a fresh look at combinational logic synthesis. 532-535
Session 33: low-power, thermal-aware architectures
- Björn Debaillie, Bruno Bougard, Gregory Lenoir, Gerd Vandersteen, Francky Catthoor:
Energy-scalable OFDM transmitter design and control. 536-541 - Rajarshi Mukherjee, Seda Ogrenci Memik:
Systematic temperature sensor allocation and placement for microprocessors. 542-547 - Amit Kumar, Li Shang, Li-Shiuan Peh, Niraj K. Jha:
HybDTM: a coordinated hardware-software approach for dynamic thermal management. 548-553 - Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan:
A systematic method for functional unit power estimation in microprocessors. 554-557 - Felix Bürgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm. 558-561
Session 34: low power system level design
- Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula:
Extending the lifetime of fuel cell based hybrid systems. 562-567 - Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti, Sarma B. K. Vrudhula:
High-level power management of embedded systems with application-specific energy cost functions. 568-573 - Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng:
Communication latency aware low power NoC synthesis. 574-579 - Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu:
Optimality study of resource binding with multi-Vdds. 580-585
Session 35: power-constrained design for multimedia
- Lin Zhong, Bin Wei, Michael J. Sinclair:
SMERT: energy-efficient design of a multimedia messaging system for mobile devices. 586-591