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ORCIDACM Transactions on Design Automation of Electronic Systems, Volume 24
Volume 24, Number 1, January 2019
- Chun-Han Lin
, Chih-Kai Kang, Pi-Cheng Hsiu:
Quality-Enhanced OLED Power Savings on Mobile Devices. 1:1-1:25 - Maral Amir, Frank Vahid, Tony Givargis:
Switching Predictive Control Using Reconfigurable State-Based Model. 2:1-2:21 - Osman Emir Erol, Sule Ozev:
Knowledge- and Simulation-Based Synthesis of Area-Efficient Passive Loop Filter Incremental Zoom-ADC for Built-In Self-Test Applications. 3:1-3:27 - Yukai Chen, Sara Vinco, Enrico Macii, Massimo Poncino:
SystemC-AMS Thermal Modeling for the Co-simulation of Functional and Extra-Functional Properties. 4:1-4:26 - Yang Song, Olivier Alavoine, Bill Lin:
Harvesting Row-Buffer Hits via Orchestrated Last-Level Cache and DRAM Scheduling for Heterogeneous Multicore Systems. 5:1-5:27 - Junchul Choi, Hoeseok Yang, Soonhoi Ha:
Optimization of Fault-Tolerant Mixed-Criticality Multi-Core Systems with Enhanced WCRT Analysis. 6:1-6:26 - Irith Pomeranz:
Boundary-Functional Broadside and Skewed-Load Tests. 7:1-7:20 - Jiajun Li, Guihai Yan, Wenyan Lu, Shijun Gong, Shuhao Jiang, Jingya Wu, Xiaowei Li:
SynergyFlow: An Elastic Accelerator Architecture Supporting Batch Processing of Large-Scale Deep Neural Networks. 8:1-8:27 - Fedor Smirnov, Felix Reimann, Jürgen Teich, Michael Glaß:
Automatic Optimization of the VLAN Partitioning in Automotive Communication Networks. 9:1-9:23 - Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan, Yakir Vizel, Aarti Gupta, Sharad Malik:
Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification. 10:1-10:24 - Xavier Carpent, Norrathep Rattanavipanon, Gene Tsudik:
Remote Attestation via Self-Measurement. 11:1-11:15 - Jingweijia Tan, Kaige Yan:
Efficiently Managing the Impact of Hardware Variability on GPUs' Streaming Processors. 12:1-12:15 - Ilgweon Kang, Fang Qiao, Dongwon Park, Daniel Kane, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham:
Three-dimensional Floorplan Representations by Using Corner Links and Partial Order. 13:1-13:33
Volume 24, Number 2, March 2019
- Yanping Gong, Fengyu Qian, Lei Wang:
Probabilistic Evaluation of Hardware Security Vulnerabilities. 14:1-14:20 - Jianwei Zheng, Chao Lu, Jiefeng Guo, Deming Chen, Donghui Guo:
A Hardware-Efficient Block Matching Algorithm and Its Hardware Design for Variable Block Size Motion Estimation in Ultra-High-Definition Video Encoding. 15:1-15:21 - Mohammad Bakhshalipour, Aydin Faraji, Seyed Armin Vakil-Ghahani, Farid Samandi, Pejman Lotfi-Kamran, Hamid Sarbazi-Azad:
Reducing Writebacks Through In-Cache Displacement. 16:1-16:21 - Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas, Bhargab B. Bhattacharya:
Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip. 17:1-17:29 - Bahareh Pourshirazi, Majed Valad Beigi, Zhichun Zhu, Gokhan Memik:
Writeback-Aware LLC Management for PCM-Based Main Memory Systems. 18:1-18:19 - Shaheer Muhammad, Muhammad Usman Rafique, Shuai Li, Zili Shao, Qixin Wang, Xue Liu:
Reconfigurable Battery Systems: A Survey on Hardware Architecture and Research Challenges. 19:1-19:27 - Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop:
Formal Modeling and Verification of a Victim DRAM Cache. 20:1-20:23 - Ankur Gupta, Juinn-Dar Huang, Shigeru Yamashita, Sudip Roy:
Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device-Based Biochips. 21:1-21:24 - Jinwook Jung, Gi-Joon Nam, Woohyun Chung, Youngsoo Shin:
Integrated Latch Placement and Cloning for Timing Optimization. 22:1-22:17 - Irith Pomeranz:
Incomplete Tests for Undetectable Faults to Improve Test Set Quality. 23:1-23:13 - Daijoon Hyun, Youngsoo Shin:
Integrated Approach of Airgap Insertion for Circuit Timing Optimization. 24:1-24:22 - Taozhong Li, Qin Wang, Yongxin Zhu, Jianfei Jiang, Guanghui He, Jing Jin, Zhigang Mao, Naifeng Jing:
A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations. 25:1-25:22 - Bernard Nongpoh, Rajarshi Ray, Moumita Das, Ansuman Banerjee:
Enhancing Speculative Execution With Selective Approximate Computing. 26:1-26:29
Volume 24, Number 3, June 2019
- Sara Vinco, Nicola Bombieri, Daniele Jahier Pagliari, Franco Fummi, Enrico Macii, Massimo Poncino:
A Cross-level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors. 27:1-27:23 - Deok Keun Oh, Mu Jun Choi, Juho Kim:
Thermal-aware 3D Symmetrical Buffered Clock Tree Synthesis. 28:1-28:22 - Tobias Schwarzer, Joachim Falk, Simone Müller, Martín Letras, Christian Heidorn, Stefan Wildermann, Jürgen Teich:
Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective Optimization. 29:1-29:23 - Chia-Heng Tu, Te-Sheng Lin:
Augmenting Operating Systems with OpenCL Accelerators. 30:1-30:29 - Xiaolin Xu, Fahim Rahman, Bicky Shakya, Apostol Vassilev, Domenic Forte, Mark Tehranipoor:
Electronics Supply Chain Integrity Enabled by Blockchain. 31:1-31:25 - Juan Valencia, Dip Goswami, Kees Goossens:
Comparing Platform-aware Control Design Flows for Composable and Predictable TDM-based Execution Platforms. 32:1-32:26 - Sixing Lu, Roman Lysecky:
Data-driven Anomaly Detection with Timing Features for Embedded Systems. 33:1-33:27 - Sara Ayman Metwalli, Yuko Hara-Azumi:
SSA-AC: Static Significance Analysis for Approximate Computing. 34:1-34:17 - Jucemar Monteiro, Marcelo O. Johann, Laleh Behjat:
An Optimized Cost Flow Algorithm to Spread Cells in Detailed Placement. 35:1-35:16 - Md. Nazmul Islam, Sandip Kundu:
Enabling IC Traceability via Blockchain Pegged to Embedded PUF. 36:1-36:23 - Bo Wan, Xi Li, Bo Zhang, Caixu Zhao, Xianglan Chen, Chao Wang, Xuehai Zhou:
DCW: A Reactive and Predictable Programming Framework for LET-Based Distributed Real-Time Systems. 37:1-37:35
Volume 24, Number 4, July 2019
- Kanad Basu, Samah Mohamed Saeed, Christian Pilato, Mohammed Ashraf, Mohammed Thari Nabeel, Krishnendu Chakrabarty, Ramesh Karri:
CAD-Base: An Attack Vector into the Electronics Supply Chain. 38:1-38:30 - Seyed Ali Rokni, Hassan Ghasemzadeh:
Share-n-Learn: A Framework for Sharing Activity Recognition Models in Wearable Systems With Context-Varying Sensors. 39:1-39:27 - Thomas Zimmermann, Mathias Mora, Sebastian Steinhorst, Daniel Mueller-Gritschneder, Andreas Jossen:
Analysis of Dissipative Losses in Modular Reconfigurable Energy Storage Systems Using SystemC TLM and SystemC-AMS. 40:1-40:33 - Nour Sayed, Longfei Mao, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Compiler-Assisted and Profiling-Based Analysis for Fast and Efficient STT-MRAM On-Chip Cache Design. 41:1-41:25 - Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman:
Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design. 42:1-42:19 - Florin Burcea, Andreas Herrmann, Bing Li, Helmut Graeb:
MEMS-IC Robustness Optimization Considering Electrical and Mechanical Design and Process Parameters. 43:1-43:24 - Engin Afacan, Günhan Dündar, I. Faik Baskaya, Ali Emre Pusane, Mustafa Berke Yelten:
On Chip Reconfigurable CMOS Analog Circuit Design and Automation Against Aging Phenomena: Sense and React. 44:1-44:22 - Yanjun Li, Ender Yilmaz, Pete Sarson, Sule Ozev:
Adaptive Test for RF/Analog Circuit Using Higher Order Correlations among Measurements. 45:1-45:16 - Chengning Wang, Dan Feng, Wei Tong, Jingning Liu, Zheng Li, Jiayi Chang, Yang Zhang, Bing Wu, Jie Xu, Wei Zhao, Yilin Li, Ruoxi Ren:
Cross-point Resistive Memory: Nonideal Properties and Solutions. 46:1-46:37 - Jaeyung Jun, Yoonah Paik, Gyeong Il Min, Seon Wook Kim, Youngsun Han:
Fault Tolerance Technique Offlining Faulty Blocks by Heap Memory Management. 47:1-47:25
Volume 24, Number 5, October 2019
- S. M. Srinivasavarma Vegesna, Ashok Chakravarthy Nara, Sk. Noor Mahammad:
A Novel Rule Mapping on TCAM for Power Efficient Packet Classification. 48:1-48:23 - Hongfei Wang, Kun He:
Improving Test and Diagnosis Efficiency through Ensemble Reduction and Learning. 49:1-49:26 - Burçin Çakir, Sharad Malik:
Revealing Cluster Hierarchy in Gate-level ICs Using Block Diagrams and Cluster Estimates of Circuit Embeddings. 50:1-50:19 - Tengtao Li, Sachin S. Sapatnekar:
Stress-Induced Performance Shifts in 3D DRAMs. 51:1-51:21 - Shounak Chakraborty, Hemangee K. Kapoor:
Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design. 52:1-52:28 - Kyu Hyun Choi, Jaeyung Jun, Minseong Kim, Seon Wook Kim:
Reducing DRAM Refresh Rate Using Retention Time Aware Universal Hashing Redundancy Repair. 53:1-53:31 - Xiangwei Li, Douglas L. Maskell:
Time-Multiplexed FPGA Overlay Architectures: A Survey. 54:1-54:19 - Sri Harsha Gade, M. Meraj Ahmed, Sujay Deb, Amlan Ganguly:
Energy Efficient Chip-to-Chip Wireless Interconnection for Heterogeneous Architectures. 55:1-55:27 - Hisashi Osawa, Yuko Hara-Azumi:
Approximate Data Reuse-based Accelerator Design for Embedded Processor. 56:1-56:25 - Rajkumar K. Raval, Atta Badii:
Investigating the Impact of Image Content on the Energy Efficiency of Hardware-accelerated Digital Spatial Filters. 57:1-57:34 - Ricardo Bonna, Denis Silva Loubach, George Ungureanu, Ingo Sander:
Modeling and Simulation of Dynamic Applications Using Scenario-Aware Dataflow. 58:1-58:29
Volume 24, Number 6, November 2019
- Li Jiang, Zhuoran Song, Haiyue Song, Chengwen Xu, Qiang Xu, Naifeng Jing, Weifeng Zhang, Xiaoyao Liang:
Energy-Efficient and Quality-Assured Approximate Computing Framework Using a Co-Training Method. 59:1-59:25 - Subodha Charles, Alif Ahmed, Ümit Y. Ogras, Prabhat Mishra:
Efficient Cache Reconfiguration Using Machine Learning in NoC-Based Many-Core CMPs. 60:1-60:23 - Youngsoo Song, Daijoon Hyun, Jingon Lee, Jinwook Jung, Youngsoo Shin:
Cut Optimization for Redundant Via Insertion in Self-Aligned Double Patterning. 61:1-61:21 - Dongjin Lee, Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty:
Impact of Electrostatic Coupling on Monolithic 3D-enabled Network on Chip. 62:1-62:22 - Vipin Kumar Kukkala, Sudeep Pasricha, Thomas H. Bradley:
JAMS-SG: A Framework for Jitter-Aware Message Scheduling for Time-Triggered Automotive Networks. 63:1-63:31 - Yashar Asgarieh, Bill Lin:
Smart-Hop Arbitration Request Propagation: Avoiding Quadratic Arbitration Complexity and False Negatives in SMART NoCs. 64:1-64:25 - Kaveh Shamsi, Meng Li, Kenneth Plaks, Saverio Fazzari, David Z. Pan, Yier Jin:
IP Protection and Supply Chain Security through Logic Obfuscation: A Systematic Overview. 65:1-65:36 - Kankan Wang, Xu Jiang, Nan Guan, Di Liu, Weichen Liu, Qingxu Deng:
Real-Time Scheduling of DAG Tasks with Arbitrary Deadlines. 66:1-66:22 - Yung-Chih Chen, Li-Cheng Zheng, Fu-Lian Wong:
Optimization of Threshold Logic Networks with Node Merging and Wire Replacement. 67:1-67:18 - Jin-Tai Yan:
Two-sided Net Untangling with Internal Detours for Single-layer Bus Routing. 68:1-68:23 - Hai Wang, Tao Xiao, Darong Huang, Lang Zhang, Chi Zhang, He Tang, Yuan Yuan:
Runtime Stress Estimation for Three-dimensional IC Reliability Management Using Artificial Neural Network. 69:1-69:29
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