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ORCIDETW 2003: Maastricht, The Netherlands
- 8th European Test Workshop, ETW 2003, Maastricht, The Netherlands, May 25-28, 2003. IEEE Computer Society 2003, ISBN 0-7695-1908-3
- M. J. Geuzebroek, Ad J. van de Goor:
TPI for improving PR fault coverage of Boolean and three-state circuits. 3-8 - Salvador Manich
, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras:
On the selection of efficient arithmetic additive test pattern generators [logic test]. 9-14 - Ozgur Sinanoglu, Alex Orailoglu:
Parity-based output compaction for core-based SOCs [logic testing]. 15-20 - Simone Borri, Magali Hage-Hassan, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Defect-oriented dynamic fault models for embedded-SRAMs. 23-28 - Said Hamdioui, Rob Wadsworth, John Delos Reyes, Ad J. van de Goor:
Importance of dynamic faults for new SRAM technologies. 29-34 - Anuja Sehgal, Aishwarya Dubey, Erik Jan Marinissen, Clemens Wouters, Harald P. E. Vranken, Krishnendu Chakrabarty:
Yield analysis for repairable embedded memories. 35-40 - Octavian Petre, Hans G. Kerkhoff:
Scan test strategy for asynchronous-synchronous interfaces [SoC testing]. 43-48 - Julien Pouget, Erik Larsson, Zebo Peng, Marie-Lise Flottes, Bruno Rouzeyre:
An efficient approach to SoC wrapper design, TAM configuration and test scheduling. 51-56 - Sandeep Kumar Goel, Erik Jan Marinissen:
Control-aware test architecture design for modular SOC testing. 57-62 - Alessandra Fudoli, Alberto Ascagni, Davide Appello, Hans A. R. Manhaeve:
A practical evaluation of IDDQ test strategies for deep submicron production test application. Experiences and targets from the field. 65-70 - Marco Rona, Gunter Krampl, Fritz Raczkowski:
Automating the device interface board modeling for virtual test. 71-76 - Victor Avendaño, Víctor H. Champac, Joan Figueras:
Signal integrity loss in bus lines due to open shielding defects. 79-84 - Daniel Arumí-Delgado, Rosa Rodríguez-Montañés, José Pineda de Gyvez, Guido Gronthoud:
Process-variability aware delay fault testing of ΔVT and weak-open defects. 85-90 - Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker:
Modeling feedback bridging faults with non-zero resistance. 91-96 - Helmut Lang, Bhuwnesh Pande, Heiko Ahrens:
Automating test program generation in STIL - expectations and experiences using IEEE 1450 [standard test interface language]. 99-104 - Eric Liau, Doris Schmitt-Landsiedel:
Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits. 105-110 - Fulvio Corno, Giovanni Squillero, Matteo Sonza Reorda:
Code generation for functional validation of pipelined microprocessors. 113-118 - H. J. Vermaak, Hans G. Kerkhoff:
Enhanced P1500 compliant wrapper suitable for delay fault testing of embedded cores. 121-126 - Marten Seth:
RF ATE equipment benefit from advanced network analyzer technology. 129-131 - Timm Ostermann, Bernd Deutschmann:
Characterization of the EME of integrated circuits with the help of the IEC standard 61967 [electromagnetic emission]. 132-137 - Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On path selection for delay fault testing considering operating conditions [logic IC testing]. 141-146 - Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
Requirements for delay testing of look-up tables in SRAM-based FPGAs. 147-152 - Erik Moerman, Sébastien Bocq, Johan Verfaillie:
Debug architecture for system on chip taking full advantage of the test access port. 155-159
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