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2020 – today
- 2024
- [j81]Tsutomu Sasao:
On Easily Reconstructable Logic Functions. IEICE Trans. Inf. Syst. 107(8): 913-921 (2024) - [j80]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Functional Decomposition of Symmetric Multiple-Valued Functions and Their Compact Representation in Decision Diagrams. IEICE Trans. Inf. Syst. 107(8): 922-929 (2024) - [c162]Tsutomu Sasao:
Approximate Synthesis for Classification Functions. ISMVL 2024: 53-58 - 2023
- [j79]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
On Representation of Maximally Asymmetric Functions Based on Decision Diagrams. FLAP 10(6): 1105-1130 (2023) - [c161]Tsutomu Sasao:
Easily Reconstructable Logic Functions. ISMVL 2023: 12-17 - [c160]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Decomposition-Based Representation of Symmetric Multiple-Valued Functions. ISMVL 2023: 76-81 - [c159]Tsutomu Sasao:
Data Mining Using Multi-Valued Logic Minimization. ISMVL 2023: 105-110 - [c158]Tsutomu Sasao, Anders Holmgren, Patrik Eklund:
A Logical Method to Predict Outcomes After Coronary Artery Bypass Grafting. ISMVL 2023: 202-208 - [i2]Jon T. Butler, Tsutomu Sasao, Shinobu Nagayama:
On the distribution of sensitivities of symmetric Boolean functions. CoRR abs/2306.14401 (2023) - 2022
- [j78]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
A Fast Method for Exactly Optimum Linear Decomposition of Index Generation Functions. J. Multiple Valued Log. Soft Comput. 38(3-4): 387-405 (2022) - [c157]Jon T. Butler, Tsutomu Sasao:
On the Sensitivity of Boolean and Multiple-Valued Symmetric Functions. ISMVL 2022: 125-130 - [c156]Tsutomu Sasao:
LUT Cascade Realization of Threshold Functions and Its Application to Implementation of Ternary Weight Neural Networks. ISMVL 2022: 151-157 - [c155]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
On Decision Diagrams for Maximally Asymmetric Functions. ISMVL 2022: 164-169 - [c154]Tsutomu Sasao:
A Method To Generate Rules From Examples. ISMVL 2022: 176-181 - 2021
- [j77]Tsutomu Sasao, Takashi Matsubara, Katsufumi Tsuji, Yoshiaki Koga:
Realization of Multi-Terminal Universal Interconnection Networks Using Contact Switches. IEICE Trans. Inf. Syst. 104-D(8): 1068-1075 (2021) - [j76]Tsutomu Sasao, Yuto Horikawa, Yukihiro Iguchi:
Classification Functions for Handwritten Digit Recognition. IEICE Trans. Inf. Syst. 104-D(8): 1076-1082 (2021) - [c153]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Improvement in the Quality of Solutions of a Heuristic Linear Decomposer for Index Generation Functions. ISMVL 2021: 13-18 - [c152]Tsutomu Sasao, Jon T. Butler:
Linear Decompositions for Multi-Valued Input Classification Functions. ISMVL 2021: 19-25 - [c151]Tsutomu Sasao, Yuto Horikawa, Yukihiro Iguchi:
A Design Method for Multiclass Classifiers. ISMVL 2021: 148-153 - 2020
- [c150]Jon T. Butler, Tsutomu Sasao, Shinobu Nagayama:
Properties of Multiple-Valued Partition Functions. ISMVL 2020: 82-87 - [c149]Tsutomu Sasao:
On the Minimization of Variables to Represent Partially Defined Classification Functions. ISMVL 2020: 117-123 - [c148]Tsutomu Sasao, Yuto Horikawa, Yukihiro Iguchi:
Handwritten Digit Recognition Based on Classification Functions. ISMVL 2020: 124-129 - [c147]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
On Optimum Linear Decomposition of Symmetric Index Generation Functions. ISMVL 2020: 130-136 - [c146]Tsutomu Sasao, Takashi Matsubara, Katsufumi Tsuji, Yoshiaki Koga:
On a Realization of Multi-terminal Universal Interconnection Networks using Contact Switches. ISMVL 2020: 253-258
2010 – 2019
- 2019
- [b3]Tsutomu Sasao
:
Index Generation Functions. Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers 2019, ISBN 978-3-031-79910-5 - [c145]Radomir S. Stankovic, Tsutomu Sasao, Jaakko T. Astola, Akihiko Yamada:
Remarks on the Design of First Digital Computers in Japan - Contributions of Yasuo Komamiya. EUROCAST (1) 2019: 123-130 - [c144]Jon T. Butler, Tsutomu Sasao:
Realizing all Index Generation Functions by the Row-Shift Method. ISMVL 2019: 138-143 - [c143]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
A Dynamic Programming Based Method for Optimum Linear Decomposition of Index Generation Functions. ISMVL 2019: 144-149 - [c142]Tsutomu Sasao:
On a Minimization of Variables to Represent Sparse Multi-Valued Input Decision Functions. ISMVL 2019: 182-187 - [c141]Jon T. Butler, Tsutomu Sasao:
Maximally Asymmetric Multiple-Valued Functions. ISMVL 2019: 188-193 - 2018
- [j75]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
An Exact Optimization Method using ZDDs for Linear Decomposition of Symmetric Index Generation Functions. FLAP 5(9): 1849-1866 (2018) - [j74]Infall Syafalni
, Tsutomu Sasao, Xiaoqing Wen:
A Method to Detect Bit Flips in a Soft-Error Resilient TCAM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1185-1196 (2018) - [c140]Hiroki Nakahara
, Tsutomu Sasao:
A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector. ISCAS 2018: 1-5 - [c139]Tsutomu Sasao:
On a Memory-Based Realization of Sparse Multiple-Valued Functions. ISMVL 2018: 50-55 - [c138]Jon T. Butler, Tsutomu Sasao:
An Exact Method to Enumerate Decomposition Charts for Index Generation Functions. ISMVL 2018: 138-143 - [c137]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions. ISMVL 2018: 144-149 - [p1]Tsutomu Sasao, Jon T. Butler:
Decomposition of Index Generation Functions Using a Monte Carlo Method. Advanced Logic Synthesis 2018: 209-225 - 2017
- [j73]Tsutomu Sasao:
A Fast Updatable Implementation of Index Generation Functions Using Multiple IGUs. IEICE Trans. Inf. Syst. 100-D(8): 1574-1582 (2017) - [j72]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions. IEICE Trans. Inf. Syst. 100-D(8): 1583-1591 (2017) - [j71]Tsutomu Sasao:
A Linear Decomposition of Index Generation Functions: Optimization Using Autocorrelation Functions. J. Multiple Valued Log. Soft Comput. 28(1): 105-127 (2017) - [c136]Tsutomu Sasao, Kyu Matsuura, Yukihiro Iguchi:
An algorithm to find optimum support-reducing decompositions for index generation functions. DATE 2017: 812-817 - [c135]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions. ISMVL 2017: 161-166 - [c134]Tsutomu Sasao:
Index Generation Functions: Minimization Methods. ISMVL 2017: 197-206 - [c133]Hiroki Nakahara
, Akira Jinguji, Simpei Sato, Tsutomu Sasao:
A Random Forest Using a Multi-valued Decision Diagram on an FPGA. ISMVL 2017: 266-271 - 2016
- [j70]Jon T. Butler, Tsutomu Sasao:
A set partition number system. Australas. J Comb. 65: 152-169 (2016) - [j69]Hiroki Nakahara
, Tsutomu Sasao, Hisashi Iwamoto, Munehiro Matsuura:
LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(1): 73-86 (2016) - [j68]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto:
An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (k). J. Multiple Valued Log. Soft Comput. 26(1-2): 109-123 (2016) - [j67]Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai, Tsutomu Sasao:
An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division. SIGARCH Comput. Archit. News 44(4): 44-49 (2016) - [c132]Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura
:
A memory-based realization of a binarized deep convolutional neural network. FPT 2016: 277-280 - [c131]Hiroki Nakahara
, Tsutomu Sasao, Hiroyuki Nakanishi, Kazumasa Iwai, Tohru Nagao, Naoya Ogawa:
An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope. ISMVL 2016: 60-65 - [c130]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
An Efficient Heuristic for Linear Decomposition of Index Generation Functions. ISMVL 2016: 96-101 - [c129]Tsutomu Sasao:
A Realization of Index Generation Functions Using Multiple IGUs. ISMVL 2016: 113-118 - [c128]Debabani Chowdhury, Debesh K. Das, Bhargab B. Bhattacharya, Tsutomu Sasao:
On the Inadmissible Class of Multiple-Valued Faulty-Functions under Stuck-at Faults. ISMVL 2016: 276-281 - [c127]Infall Syafalni
, Tsutomu Sasao, Xiaoqing Wen:
Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM. ISVLSI 2016: 679-684 - 2015
- [j66]Hiroki Nakahara
, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto, Yasuhiro Terao:
A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units. IEICE Trans. Inf. Syst. 98-D(2): 262-271 (2015) - [j65]Jon T. Butler, Tsutomu Sasao:
High-Speed Hardware Partition Generation. ACM Trans. Reconfigurable Technol. Syst. 7(4): 28:1-28:17 (2015) - [c126]Hiroki Nakahara
, Hideki Yoshida, Shin-ich Shioya, Renji Mikami, Tsutomu Sasao:
A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank. ARC 2015: 267-279 - [c125]Infall Syafalni
, Tsutomu Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase:
A soft-error tolerant TCAM using partial don't-care keys. ETS 2015: 1-2 - [c124]Hiroki Nakahara, Tsutomu Sasao:
A deep convolutional neural network based on nested residue number system. FPL 2015: 1-6 - [c123]Hiroki Nakahara
, Tsutomu Sasao, Hiroyuki Nakanishi, Kazumasa Iwai:
An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD. ISMVL 2015: 97-102 - [c122]Tsutomu Sasao:
A Reduction Method for the Number of Variables to Represent Index Generation Functions: s-Min Method. ISMVL 2015: 164-169 - [c121]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton
, Theodore W. Manikas
:
Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems. ISMVL 2015: 170-175 - 2014
- [b2]Tsutomu Sasao
, Jon T. Butler:
Applications of Zero-Suppressed Decision Diagrams. Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers 2014, ISBN 978-3-031-79869-6, pp. 1-123 - [j64]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton
, Theodore W. Manikas
:
On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems. IEICE Trans. Inf. Syst. 97-D(9): 2234-2242 (2014) - [j63]Hiroki Nakahara
, Tsutomu Sasao, Munehiro Matsuura:
A Packet Classifier Based on Prefetching EVMDD (k) Machines. IEICE Trans. Inf. Syst. 97-D(9): 2243-2252 (2014) - [j62]Infall Syafalni
, Tsutomu Sasao:
Head-Tail Expressions for Interval Functions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(10): 2043-2054 (2014) - [j61]Tsutomu Sasao, Yuta Urano, Yukihiro Iguchi:
A Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions Using Difference Matrix. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2427-2433 (2014) - [j60]Hafiz Md. Hasan Babu, Nazir Saleheen, Lafifa Jamal
, Sheikh Muhammad Sarwar, Tsutomu Sasao:
Approach to design a compact reversible low power binary comparator. IET Comput. Digit. Tech. 8(3): 129-139 (2014) - [j59]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
EVMDD-Based Analysis and Diagnosis Methods of Multi-State Systems with Multi-State Components. J. Multiple Valued Log. Soft Comput. 22(1-2): 59-78 (2014) - [j58]Tsutomu Sasao:
Index Generation Functions: Tutorial. J. Multiple Valued Log. Soft Comput. 23(3-4): 235-263 (2014) - [j57]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Piecewise Arithmetic Expressions of Numeric Functions and Their Application to Design of Numeric Function Generators. J. Multiple Valued Log. Soft Comput. 23(3-4): 293-313 (2014) - [j56]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Heterogeneous Multi-valued Decision Diagram Machine for Encoded Characteristic Function for Non-zero Outputs. J. Multiple Valued Log. Soft Comput. 23(3-4): 365-377 (2014) - [c120]Infall Syafalni
, Tsutomu Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase:
Soft-error tolerant TCAMs for high-reliability packet classifications. APCCAS 2014: 471-474 - [c119]Hiroki Nakahara
, Tsutomu Sasao, Munehiro Matsuura:
An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K). ISMVL 2014: 1-6 - [c118]Tsutomu Sasao, Yuta Urano, Yukihiro Iguchi:
A Lower Bound on the Number of Variables to Represent Incompletely Specified Index Generation Functions. ISMVL 2014: 7-12 - [c117]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton
, Theodore W. Manikas
:
Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams. ISMVL 2014: 190-195 - [c116]Debesh K. Das, Debabani Chowdhury, Bhargab B. Bhattacharya, Tsutomu Sasao:
Inadmissible Class of Boolean Functions under Stuck-at Faults. ISMVL 2014: 237-242 - 2013
- [j55]Infall Syafalni
, Tsutomu Sasao:
On the Numbers of Products in Prefix SOPs for Interval Functions. IEICE Trans. Inf. Syst. 96-D(5): 1086-1094 (2013) - [j54]Hiroki Nakahara
, Tsutomu Sasao, Munehiro Matsuura:
A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition. IEICE Trans. Inf. Syst. 96-D(8): 1667-1675 (2013) - [j53]Tsutomu Sasao:
Multiple-Valued Index Generation Functions: Reduction of Variables by Linear Transformation. J. Multiple Valued Log. Soft Comput. 21(5-6): 541-559 (2013) - [c115]Hiroki Nakahara
, Tsutomu Sasao, Munehiro Matsuura:
An Architecture for IPv6 Lookup Using Parallel Index Generation Units. ARC 2013: 59-71 - [c114]Jon T. Butler, Tsutomu Sasao:
Hardware Index to Set Partition Converter. ARC 2013: 72-83 - [c113]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A packet classifier using LUT cascades based on EVMDDS (k). FPL 2013: 1-6 - [c112]Infall Syafalni
, Tsutomu Sasao:
A TCAM generator for packet classification. ICCD 2013: 322-328 - [c111]Hiroki Nakahara
, Tsutomu Sasao, Munehiro Matsuura:
A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions. ISMVL 2013: 90-95 - [c110]Tsutomu Sasao:
An Application of Autocorrelation Functions to Find Linear Decompositions for Incompletely Specified Index Generation Functions. ISMVL 2013: 96-102 - [c109]Tsutomu Sasao:
Four Decades of Multi-Valued Logic: Lists of Highly Cited Papers. ISMVL 2013: 198-202 - [c108]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Minimization of the Number of Edges in an EVMDD by Variable Grouping for Fast Analysis of Multi-State Systems. ISMVL 2013: 284-289 - [i1]Debesh K. Das, Debabani Chowdhury, Bhargab B. Bhattacharya, Tsutomu Sasao:
Inadmissible Class of Boolean Functions under Stuck-at Faults. CoRR abs/1309.3993 (2013) - 2012
- [j52]Hiroki Nakahara
, Tsutomu Sasao, Munehiro Matsuura:
A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton. IEICE Trans. Inf. Syst. 95-D(2): 364-373 (2012) - [j51]Hiroki Nakahara
, Tsutomu Sasao, Munehiro Matsuura:
A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition. Microprocess. Microsystems 36(8): 644-664 (2012) - [j50]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Comparison of Multi-Valued and Heterogeneous Decision Diagram Machines. J. Multiple Valued Log. Soft Comput. 19(1-3): 203-217 (2012) - [j49]Hiroki Nakahara, Hiroyuki Nakanishi, Tsutomu Sasao:
On a wideband fast fourier transform for a radio telescope. SIGARCH Comput. Archit. News 40(5): 46-51 (2012) - [c107]Hiroki Nakahara
, Tsutomu Sasao, Munehiro Matsuura:
A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU. ARC 2012: 202-214 - [c106]Tsutomu Sasao:
Linear decomposition of index generation functions. ASP-DAC 2012: 781-788 - [c105]Tsutomu Sasao:
Row-shift decompositions for index generation functions. DATE 2012: 1585-1590 - [c104]Hiroki Nakahara
, Hiroyuki Nakanishi, Tsutomu Sasao:
On a Wideband Fast Fourier Transform Using Piecewise Linear Approximations: Application to a Radio Telescope Spectrometer. ICA3PP (1) 2012: 202-217 - [c103]Jon T. Butler, Tsutomu Sasao:
Hardware Index to Permutation Converter. IPDPS Workshops 2012: 431-436 - [c102]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Analysis of Multi-state Systems with Multi-state Components Using EVMDDs. ISMVL 2012: 122-127 - [c101]Hiroki Nakahara
, Tsutomu Sasao, Munehiro Matsuura:
Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition. ISMVL 2012: 148-153 - [c100]Tsutomu Sasao:
Multiple-Valued Input Index Generation Functions: Optimization by Linear Transformation. ISMVL 2012: 185-190 - [c99]Infall Syafalni
, Tsutomu Sasao:
A Fast Head-Tail Expression Generator for TCAM - Application to Packet Classification. ISVLSI 2012: 27-32 - 2011
- [j48]Jon T. Butler, C. L. Frenzen, Njuguna Macaria, Tsutomu Sasao:
A fast segmentation algorithm for piecewise polynomial numeric function generators. J. Comput. Appl. Math. 235(14): 4076-4082 (2011) - [c98]Hiroki Nakahara
, Tsutomu Sasao, Munehiro Matsuura:
A Regular Expression Matching Circuit Based on a Decomposed Automaton. ARC 2011: 16-28 - [c97]Jon T. Butler, Tsutomu Sasao:
Index to Constant Weight Codeword Converter. ARC 2011: 193-205 - [c96]Jon T. Butler, Tsutomu Sasao:
Fast Hardware Computation of x Mod z. IPDPS Workshops 2011: 294-297 - [c95]Tsutomu Sasao:
Index Generation Functions: Recent Developments. ISMVL 2011: 1-9 - [c94]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Numeric Function Generators Using Piecewise Arithmetic Expressions. ISMVL 2011: 16-21 - [c93]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions. ISMVL 2011: 125-130 - 2010
- [j47]Tsutomu Sasao, Hiroki Nakahara
, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler:
A Quaternary Decision Diagram Machine: Optimization of Its Code. IEICE Trans. Inf. Syst. 93-D(8): 2026-2035 (2010) - [j46]Hiroki Nakahara
, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura:
A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation. IEICE Trans. Inf. Syst. 93-D(8): 2048-2058 (2010) - [j45]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams. IEICE Trans. Inf. Syst. 93-D(8): 2059-2067 (2010) - [j44]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators. Inf. Media Technol. 5(2): 412-423 (2010) - [j43]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators. IPSJ Trans. Syst. LSI Des. Methodol. 3: 118-129 (2010) - [j42]C. L. Frenzen, Tsutomu Sasao, Jon T. Butler:
On the number of segments needed in a piecewise linear approximation. J. Comput. Appl. Math. 234(2): 437-446 (2010) - [c92]Tsutomu Sasao:
On the Numbers of Variables to Represent Multi-valued Incompletely Specified Functions. DSD 2010: 420-423 - [c91]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Packet Classifier Using a Parallel Branching Program Machine. DSD 2010: 745-752 - [c90]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs. ISMVL 2010: 223-228 - [c89]Hiroki Nakahara
, Tsutomu Sasao, Munehiro Matsuura:
A Comparison of Architectures for Various Decision Diagram Machines. ISMVL 2010: 229-234 - [c88]Tsutomu Sasao:
On the Number of Products to Represent Interval Functions by SOPs with Four-Valued Variables. ISMVL 2010: 282-287 - [c87]Hiroshi Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A regular expression matching using non-deterministic finite automaton. MEMOCODE 2010: 73-76
2000 – 2009
- 2009
- [b1]Tsutomu Sasao
, Jon T. Butler:
Progress in Applications of Boolean Functions. Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers 2009, ISBN 978-3-031-79811-5 - [j41]Shinobu Nagayama, Tsutomu Sasao:
Complexities of Graph-Based Representations for Elementary Functions. IEEE Trans. Computers 58(1): 106-119 (2009) - [c86]Hiroki Nakahara
, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura:
A Parallel Branching Program Machine for Emulation of Sequential Circuits. ARC 2009: 261-267 - [c85]Tsutomu Sasao, Takaaki Nakamura, Munehiro Matsuura:
Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables. DSD 2009: 765-772 - [c84]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura:
The Parallel Sieve Method for a Virus Scanning Engine. DSD 2009: 809-816 - [c83]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura:
A virus scanning engine using a parallel finite-input memory machine and MPUs. FPL 2009: 635-639 - [c82]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions. ISMVL 2009: 349-355 - [c81]Tsutomu Sasao, Hiroki Nakahara
, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler:
A Quaternary Decision Diagram Machine and the Optimization of its Code. ISMVL 2009: 362-369 - 2008
- [c80]Tsutomu Sasao, Yukihiro Iguchi:
On the Complexity of Error Detection Functions for Redundant Residue Number Systems. DSD 2008: 880-887 - [c79]Shinobu Nagayama, Jon T. Butler, Tsutomu Sasao:
Programmable Numerical Function Generators for Two-Variable Functions. DSD 2008: 891-898 - [c78]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Numerical function generators using bilinear interpolation. FPL 2008: 463-466 - [c77]Tsutomu Sasao:
On the numbers of variables to represent sparse logic functions. ICCAD 2008: 45-51 - [c76]Shinobu Nagayama, Tsutomu Sasao:
Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators. ISMVL 2008: 50-56 - [c75]Tsutomu Sasao:
On the Complexity of Classification Functions. ISMVL 2008: 57-63 - 2007
- [j40]Debatosh Debnath, Tsutomu Sasao:
A New Equivalence Relation of Logic Functions and Its Application in the Design of AND-OR-EXOR Networks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(5): 932-940 (2007) - [j39]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
Design Methods of Radix Converters Using Arithmetic Decompositions. IEICE Trans. Inf. Syst. 90-D(6): 905-914 (2007) - [j38]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2752-2761 (2007) - [j37]Munehiro Matsuura, Tsutomu Sasao:
BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2762-2769 (2007) - [j36]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
Design Methods for Binary to Decimal Converters Using Arithmetic Decompositions. J. Multiple Valued Log. Soft Comput. 13(4-6): 503-520 (2007) - [j35]Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler:
Numerical Function Generators Using LUT Cascades. IEEE Trans. Computers 56(6): 826-838 (2007) - [c74]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Numerical Function Generators Using Edge-Valued Binary Decision Diagrams. ASP-DAC 2007: 535-540 - [c73]Tsutomu Sasao, Munehiro Matsuura:
An Implementation of an Address Generator Using Hash Memories. DSD 2007: 69-76 - [c72]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation. DSD 2007: 280-287 - [c71]Tsutomu Sasao, Hiroki Nakahara:
Implementations of Reconfigurable Logic Arrays on FPGAs. FPT 2007: 217-223 - [c70]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A CAM Emulator Using Look-Up Table Cascades. IPDPS 2007: 1-8 - [c69]Shinobu Nagayama, Tsutomu Sasao:
Representations of Elementary Functions Using Edge-Valued MDDs. ISMVL 2007: 5 - [c68]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--. ISMVL 2007: 32 - [c67]Tsutomu Sasao:
An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays. ISMVL 2007: 40 - 2006
- [j34]Hui Qin, Tsutomu Sasao, Yukihiro Iguchi:
A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA. IEICE Trans. Inf. Syst. 89-D(3): 1139-1147 (2006) - [j33]Debatosh Debnath, Tsutomu Sasao:
Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3443-3450 (2006) - [j32]Hiroki Nakahara
, Tsutomu Sasao, Munehiro Matsuura:
A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3471-3481 (2006) - [j31]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3510-3518 (2006) - [j30]Tsutomu Sasao:
Analysis and synthesis of weighted-sum functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 789-796 (2006) - [c66]Hui Qin, Tsutomu Sasao, Jon T. Butler:
Implementation of LPM Address Generators on FPGAs. ARC 2006: 170-181 - [c65]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Programmable numerical function generators based on quadratic approximation: architecture and synthesis method. ASP-DAC 2006: 378-383 - [c64]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A fast logic simulator using a look up table cascade emulator. ASP-DAC 2006: 466-472 - [c63]Hiroki Nakahara
, Tsutomu Sasao:
A Soft Error Tolerant LUT Cascade Emulator. ATS 2006: 115-124 - [c62]Tsutomu Sasao:
Design Methods for Multiple-Valued Input Address Generators. ISMVL 2006: 1 - [c61]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
On Designs of Radix Converters Using Arithmetic Decompositions. ISMVL 2006: 3 - [c60]Tsutomu Sasao, Jon T. Butler:
Implementation of Multiple-Valued CAM Functions by LUT Cascades. ISMVL 2006: 11 - [c59]Tsutomu Sasao, Shinobu Nagayama:
Representations of Elementary Functions Using Binary Moment Diagrams. ISMVL 2006: 28 - 2005
- [j29]Debatosh Debnath, Tsutomu Sasao:
Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders. IEICE Trans. Inf. Syst. 88-D(7): 1492-1500 (2005) - [j28]Debatosh Debnath, Tsutomu Sasao:
Exact Minimization of FPRMs for Incompletely Specified Functions by Using MTBDDs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3332-3341 (2005) - [j27]Hiroki Nakahara
, Tsutomu Sasao, Munehiro Matsuura:
A Design Algorithm for Sequential Circuits Using LUT Rings. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3342-3350 (2005) - [j26]Shinobu Nagayama, Alan Mishchenko, Tsutomu Sasao, Jon T. Butler:
Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams. J. Multiple Valued Log. Soft Comput. 11(5-6): 437-465 (2005) - [j25]Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura:
Average Path Length of Binary Decision Diagrams. IEEE Trans. Computers 54(9): 1041-1053 (2005) - [j24]Shinobu Nagayama, Tsutomu Sasao:
On the optimization of heterogeneous MDDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1645-1659 (2005) - [c58]Tsutomu Sasao, Munehiro Matsuura:
BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition. DAC 2005: 373-378 - [c57]Tsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki:
On LUT Cascade Realizations of FIR Filters. DSD 2005: 467-475 - [c56]Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler:
Programmable Numerical Function Generators: Architectures and Synthesis Method. FPL 2005: 118-123 - [c55]Hui Qin, Tsutomu Sasao, Yukihiro Iguchi:
An FPGA design of AES encryption circuit with 128-bit keys. ACM Great Lakes Symposium on VLSI 2005: 147-151 - [c54]Yukihiro Iguchi, Tsutomu Sasao:
Hardware to Compute Walsh Coefficients. ISMVL 2005: 75-81 - [c53]Marek A. Perkowski, Tsutomu Sasao, Jong-Hwan Kim, Martin Lukac, Jeff Allen, Stefan Gebauer:
Hahoe KAIST Robot Theatre: Learning Rules of Interactive Robot Behavior as a Multiple-Valued Logic Synthesis Problem. ISMVL 2005: 236-248 - [c52]Tsutomu Sasao:
Radix Converters: Complexity and Implementation by LUT Cascades. ISMVL 2005: 256-263 - 2004
- [j23]Atsumu Iseno, Yukihiro Iguchi, Tsutomu Sasao:
Fault Diagnosis for RAMs Using Walsh Spectrum. IEICE Trans. Inf. Syst. 87-D(3): 592-600 (2004) - [c51]Tsutomu Sasao, Jon T. Butler:
A fast method to derive minimum SOPs for decomposable functions. ASP-DAC 2004: 585-590 - [c50]Debatosh Debnath, Tsutomu Sasao:
Efficient computation of canonical form for Boolean matching in large libraries. ASP-DAC 2004: 591-596 - [c49]Shinobu Nagayama, Tsutomu Sasao:
Minimization of memory size for heterogeneous MDDs. ASP-DAC 2004: 871-874 - [c48]Tsutomu Sasao, Munehiro Matsuura:
A method to decompose multiple-output logic functions. DAC 2004: 428-433 - [c47]Shinobu Nagayama, Tsutomu Sasao:
On the Minimization of Average Path Lengths for Heterogeneous MDDs. ISMVL 2004: 216-222 - [c46]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades. ISMVL 2004: 302-308 - 2003
- [j22]Shinobu Nagayama, Tsutomu Sasao:
Compact Representations of Logic Functions Using Heterogeneous MDDs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3168-3175 (2003) - [c45]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
Evaluation of multiple-output logic functions using decision diagrams. ASP-DAC 2003: 312-315 - [c44]Alan Mishchenko, Tsutomu Sasao:
Large-scale SOP minimization using decomposition and functional properties. DAC 2003: 149-154 - [c43]Tsutomu Sasao:
Cascade Realizations of Two-valued Input Multiple-Valued Output Functions using Decomposition of Group Functions. ISMVL 2003: 125-132 - [c42]Shinobu Nagayama, Tsutomu Sasao:
Compact Representations of Logic Functions using Heterogeneous MDDs. ISMVL 2003: 247-252 - [c41]Jon T. Butler, Tsutomu Sasao:
On the Average Path Length in Decision Diagrams of Multiple-Valued Functions. ISMVL 2003: 383-390 - 2002
- [j21]Munehiro Matsuura, Tsutomu Sasao, Jon T. Butler, Yukihiro Iguchi:
Bi-Partition of Shared Binary Decision Diagrams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2693-2700 (2002) - [c40]Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura:
Representations of Logic Functions Using QRMDDs. ISMVL 2002: 261-269 - [c39]Alan Mishchenko, Tsutomu Sasao:
Encoding of Boolean Functions and its Application to LUT Cascade Synthesis. IWLS 2002: 115-120 - [c38]Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura:
Comparison of Decision Diagrams for Multiple-Output Logic Functions. IWLS 2002: 379-384 - 2001
- [j20]Tsutomu Sasao, Jon T. Butler:
Worst and Best Irredundant Sum-of-Products Expressions. IEEE Trans. Computers 50(9): 935-948 (2001) - [j19]Radomir S. Stankovic, Tsutomu Sasao:
A discussion on the history of research in arithmetic andReed-Muller expressions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9): 1177-1179 (2001) - [c37]Tsutomu Sasao, Jon T. Butler:
On the minimization of SOPs for bi-decomposition functions. ASP-DAC 2001: 219-224 - [c36]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
Realization of Multiple-Output Functions by Reconfigurable Cascades. ICCD 2001: 388-393 - [c35]Tsutomu Sasao:
Compact SOP Representations for Multiple-Output Functions: An Encoding Method Using Multiple-Valued Logic. ISMVL 2001: 207-212 - 2000
- [c34]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno:
A hardware simulation engine based on decision diagrams (short paper). ASP-DAC 2000: 73-76 - [c33]Debatosh Debnath, Tsutomu Sasao:
Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions. ASP-DAC 2000: 247-252 - [c32]Tsutomu Sasao, Ken-ichi Kurimoto:
Three parameters to find functional decompositions. ASP-DAC 2000: 259-264 - [c31]Tsutomu Sasao:
On the Number of Dependent Variables for Incompletely Specified Multiple-Valued Functions. ISMVL 2000: 91-100 - [c30]Hafiz Md. Hasan Babu, Tsutomu Sasao:
Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams. ISMVL 2000: 147-152 - [c29]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
Implementation of Multiple-Output Functions Using PQMDDs. ISMVL 2000: 199-205 - [c28]Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy:
Selection of potentially testable path delay faults for test generation. ITC 2000: 376-384
1990 – 1999
- 1999
- [c27]Yukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, Atsumu Iseno:
Realization of Regular Ternary Logic Functions. ASP-DAC 1999: 331- - [c26]Debatosh Debnath, Tsutomu Sasao:
Fast Boolean Matching Under Permutation Using Representative. ASP-DAC 1999: 359-362 - [c25]Tsutomu Sasao:
Totally Undecomposable Functions: Applications to Efficient Multiple-Valued Decompositions. ISMVL 1999: 59-65 - [c24]Debatosh Debnath, Tsutomu Sasao:
Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates. ISMVL 1999: 99-104 - [c23]Hafiz Md. Hasan Babu, Tsutomu Sasao:
Shared Multiple-Valued Decision Diagrams for Multiple-Output Functions. ISMVL 1999: 166-172 - 1998
- [c22]Debatosh Debnath, Tsutomu Sasao:
A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks. ASP-DAC 1998: 69-74 - [c21]Radomir S. Stankovic, Tsutomu Sasao:
Decision Diagrams for Discrete Functions: Classification and Unified Interpretation. ASP-DAC 1998: 439-446 - [c20]Hafiz Md. Hasan Babu, Tsutomu Sasao:
Design of Multiple-Output Networks using Time Domain Multiplexing and Shared Multi-Terminal Multiple-Valued Decision Diagrams. ISMVL 1998: 45-51 - [c19]Jon T. Butler, Tsutomu Sasao:
On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels. ISMVL 1998: 83-88 - 1997
- [j18]Jon T. Butler, David S. Herscovici, Tsutomu Sasao, Robert J. Barton III:
Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions. IEEE Trans. Computers 46(4): 491-494 (1997) - [j17]Tsutomu Sasao:
Easily Testable Realizations for Generalized Reed-Muller Expressions. IEEE Trans. Computers 46(6): 709-716 (1997) - [c18]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
On properties of Kleene TDDs. ASP-DAC 1997: 473-476 - [c17]Debatosh Debnath, Tsutomu Sasao:
An optimization of AND-OR-EXOR three-level networks. ASP-DAC 1997: 545-550 - [c16]Seiji Kajihara, Tsutomu Sasao:
On the Adders with Minimum Tests. Asian Test Symposium 1997: 10-15 - [c15]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
On Decomposition of Kleene TDDs. Asian Test Symposium 1997: 234- - [c14]Tsutomu Sasao, Jon T. Butler:
Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions. ISMVL 1997: 55-60 - [c13]Tsutomu Sasao:
Ternary Decision Diagrams: Survey. ISMVL 1997: 241-252 - 1996
- [j16]Norio Koda, Tsutomu Sasao:
A simplification method for AND-EXOR expressions for multiple-output functions. Syst. Comput. Jpn. 27(9): 1-11 (1996) - [c12]Jon T. Butler, J. L. Nowlin, Tsutomu Sasao:
Planarity in ROMDD's of Multiple-Valued Symmetric Functions. ISMVL 1996: 236-241 - [c11]Tsutomu Sasao, Jon T. Butler:
A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams. ISMVL 1996: 248-254 - 1995
- [c10]Debatosh Debnath, Tsutomu Sasao:
GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions. ASP-DAC 1995 - [c9]Tsutomu Sasao, Jon T. Butler:
Planar Multiple-Valued Decision Diagrams. ISMVL 1995: 28-35 - 1994
- [c8]Radomir S. Stankovic, Milena Stankovic, Claudio Moraga, Tsutomu Sasao:
Calculation of Reed-Muller-Fourier Coefficients of Multiple-Valued Functions through Multiple-Place Decision Diagrams. ISMVL 1994: 82-88 - [c7]Tsutomu Sasao, Jon T. Butler:
A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion. ISMVL 1994: 97-106 - [c6]Jon T. Butler, Tsutomu Sasao:
Multiple-Valued Combinational Circuits with Feedback. ISMVL 1994: 342-347 - 1993
- [j15]Daniel Brand, Tsutomu Sasao:
Minimization of AND-EXOR Expressions Using Rewrite Rules. IEEE Trans. Computers 42(5): 568-576 (1993) - [j14]Tsutomu Sasao:
EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5): 621-632 (1993) - 1992
- [j13]Norio Koda, Tsutomu Sasao:
Four-variable AND-EXOR minimum expressions and their properties. Syst. Comput. Jpn. 23(10): 27-41 (1992) - [c5]Tsutomu Sasao:
Optimization of Multiple-Valued AND-EXOR Expressions Using Multiple-Place Decision Diagrams. ISMVL 1992: 451-458 - 1991
- [j12]Tsutomu Sasao:
Bounds on the Average Number of Products in the Minimum Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions. IEEE Trans. Computers 40(5): 645-651 (1991) - [c4]Tsutomu Sasao:
A Transformation of Multiple-Valued Input Two-Valued Output Functions and its Application to Simplification of Exclusive-or Sum-of-Products Expressions. ISMVL 1991: 270-279 - 1990
- [c3]Tsutomu Sasao:
EXMIN: A Simplification Algorithm for Exclusive-OR-Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions. ISMVL 1990: 128-135
1980 – 1989
- 1989
- [j11]Tsutomu Sasao:
On the Optimal Design of Multiple-Valued PLA's. IEEE Trans. Computers 38(4): 582-592 (1989) - 1988
- [j10]Tsutomu Sasao:
Multiple-Valued Logic and Optimization of Programmable Logic Arrays. Computer 21(4): 71-80 (1988) - 1986
- [c2]Tsutomu Sasao:
MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators. DAC 1986: 86-93 - 1985
- [j9]Tsutomu Sasao:
An Algorithm to Derive the Complement of a Binary Function with Multiple-Valued Inputs. IEEE Trans. Computers 34(2): 131-140 (1985) - 1984
- [j8]Tsutomu Sasao:
Input Variable Assignment and Output Phase Optimization of PLA's. IEEE Trans. Computers 33(10): 879-894 (1984) - 1981
- [j7]Tsutomu Sasao:
Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays. IEEE Trans. Computers 30(9): 635-643 (1981)
1970 – 1979
- 1979
- [j6]Tsutomu Sasao, Kozo Kinoshita:
On the Number of Fanout-Free Functions and Unate Cascade Functions. IEEE Trans. Computers 28(1): 66-72 (1979) - [j5]Tsutomu Sasao, Kozo Kinoshita:
Conservative Logic Elements and Their Universality. IEEE Trans. Computers 28(9): 682-685 (1979) - 1978
- [j4]Tsutomu Sasao, Kozo Kinoshita:
Cascade Realization of 3-Input 3-Output Conservative Logic Circuits. IEEE Trans. Computers 27(3): 214-221 (1978) - [j3]Tsutomu Sasao, Kozo Kinoshita:
Realization of Minimum Circuits with Two-Input Conservative Logic Elements. IEEE Trans. Computers 27(8): 749-752 (1978) - [c1]Tsutomu Sasao:
An application of multiple-valued logic to a design of programmable logic arrays. MVL 1978: 65-72 - 1976
- [j2]Kozo Kinoshita, Tsutomu Sasao, Jun Matsuda:
On Magnetic Bubble Logic Circuits. IEEE Trans. Computers 25(3): 247-253 (1976) - 1975
- [j1]Hideo Fujiwara, Yoich Nagao, Tsutomu Sasao, Kozo Kinoshita:
Easily Testable Sequential Machines with Extra Inputs. IEEE Trans. Computers 24(8): 821-826 (1975)
Coauthor Index

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