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ORCIDIEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 19
Volume 19, Number 1, January 2011
- Myint Wai Phyu, Kangkang Fu, Wang Ling Goh, Kiat Seng Yeo
:
Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops. 1-9
- Alexandru Andrei, Petru Eles, Olivera Jovanovic, Marcus T. Schmitz, Jens Ogniewski, Zebo Peng:
Quasi-Static Voltage Scaling for Energy Minimization With Time Constraints. 10-23 - Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang:
SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage. 24-32 - Cheng-Hung Lin, Shih-Chieh Chang:
Efficient Pattern Matching Algorithm for Memory Architecture. 33-41 - Marco D. Santambrogio, Renato Stefanelli:
A New Compact SD2 Positive Integer Triangular Array Division Circuit. 42-51 - Jiun-Ping Wang, Shiann-Rong Kuang, Shish-Chang Liang:
High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications. 52-60 - Joonhee Lee, Sunghyun Park, SeongHwan Cho:
A 470-µW 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider With an In-Phase Dual-Input Injection Scheme. 61-70 - Ian Kuon, Jonathan Rose:
Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design. 71-84 - Mehran Mozaffari Kermani, Arash Reyhani-Masoleh:
A Lightweight High-Performance Fault Detection Scheme for the Advanced Encryption Standard Using Composite Fields. 85-91 - Shahin Nazarian, Hanif Fatemi, Massoud Pedram:
Accurate Timing and Noise Analysis of Combinational and Sequential Logic Cells Using Current Source Modeling. 92-103 - Jason Nemeth, Rui Min, Wen-Ben Jone, Yiming Hu:
Location Cache Design and Performance Analysis for Chip Multiprocessors. 104-117 - Chao Shi, Man Kay Law, Amine Bermak:
A Novel Asynchronous Pixel for an Energy Harvesting CMOS Image Sensor. 118-129 - Claude Thibeault, Yassine Hariri:
CDelta IDDQ : Improving Current-Based Testing and Diagnosis Through Modified Test Pattern Generation. 130-141 - Irith Pomeranz, Sudhakar M. Reddy:
Fixed-State Tests for Delay Faults in Scan Designs. 142-146 - Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating. 146-151 - Sherif A. Tawfik, Volkan Kursun:
Multi-Threshold Voltage FinFET Sequential Circuits. 151-156 - Shau-Yu Cheng, Chueh-An Tsai, Terng-Yin Hsu:
Channel Estimator and Aliasing Canceller for Equalizing and Decoding Non-Cyclic Prefixed Single-Carrier Block Transmission via MIMO-OFDM Modem. 156-160 - Minki Cho, Jason Schlessman, Wayne H. Wolf, Saibal Mukhopadhyay:
Reconfigurable SRAM Architecture With Spatial Voltage Scaling for Low Power Mobile Multimedia Applications. 161-165 - Hsuan-Jung Hsu, Shi-Yu Huang:
A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme. 165-170
Volume 19, Number 2, February 2011
- Niraj K. Jha:
Editorial Announcing a New Editor-in-Chief. 173-174 - Tien-Yu Lo, Chung-Chih Hung:
A 1 GHz Equiripple Low-Pass Filter With a High-Speed Automatic Tuning Scheme. 175-181 - Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry:
Analytical Soft Error Models Accounting for Die-to-Die and Within-Die Variations in Sub-Threshold SRAM Cells. 182-195 - Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo, Jeremy Yung Shern Low:
Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM. 196-204 - Jongyoon Jung, Taewhan Kim:
Scheduling and Resource Binding Algorithm Considering Timing Variation. 205-216 - Hariharan Sankaran, Srinivas Katkoori:
Simultaneous Scheduling, Allocation, Binding, Re-Ordering, and Encoding for Crosstalk Pattern Minimization During High-Level Synthesis. 217-226 - Jun Seomun, Youngsoo Shin:
Design and Optimization of Power-Gated Circuits With Autonomous Data Retention. 227-236 - Hao Xu, Ranga Vemuri, Wen-Ben Jone:
Dynamic Characteristics of Power Gating During Mode Transition. 237-249 - Yao Guo, Pritish Narayanan, Mahmoud A. Bennaser, Saurabh Chheda, Csaba Andras Moritz:
Energy-Efficient Hardware Data Prefetching. 250-263 - Jae-sun Seo, Himanshu Kaul, Ram Krishnamurthy, Dennis Sylvester, David T. Blaauw:
A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect. 264-273 - Judith Liu-Jimenez, Raul Sánchez-Reillo, Belen Fernandez-Saavedra:
Iris Biometrics for Embedded Systems. 274-282 - Ping Chen, Andy Ye:
The Effect of Multi-Bit Correlation on the Design of Field-Programmable Gate Array Routing Resources. 283-294 - Rakesh Gnana David Jeyasingh, Navakanta Bhat, Bharadwaj S. Amrutur:
Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique. 295-304 - Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu:
Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding. 305-318 - Ramachandra Achar, Michel S. Nakhla, Harjot S. Dhindsa, Arvind R. Sridhar, Douglas Paul, Natalie Nakhla:
Parallel and Scalable Transient Simulator for Power Grids via Waveform Relaxation (PTS-PWR). 319-332 - Irith Pomeranz, Sudhakar M. Reddy:
Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits. 333-337 - Shu-Yi Wong, Chunhong Chen, Q. M. Jonathan Wu:
Low Power Chien Search for BCH Decoder Using RT-Level Power Management. 338-341 - Sourajeet Roy, Anestis Dounavis:
Efficient Delay and Crosstalk Modeling of RLC Interconnects Using Delay Algebraic Equations. 342-346
Volume 19, Number 3, March 2011
- Yehea I. Ismail:
Editorial. 349-368 - Kenneth S. Stevens, Pankaj Golani, Peter A. Beerel:
Energy and Performance Models for Synchronous and Asynchronous Communication. 369-382 - Kevin Brownell, Ali Durlov Khan, Gu-Yeon Wei, David M. Brooks:
Automating Design of Voltage Interpolation to Address Process Variations. 383-396 - Stojan Z. Denic, Bane V. Vasic, Charalambos D. Charalambous, Jifeng Chen, Janet Meiling Wang:
Information Theoretic Modeling and Analysis for Global Interconnects With Process Variations. 397-410 - Xiaoke Qin, Chetan Muthry, Prabhat Mishra:
Decoding-Aware Compression of FPGA Bitstreams. 411-419 - Costas Argyrides, Dhiraj K. Pradhan, Taskin Koçak:
Matrix Codes for Reliable and Cost Efficient Memory Chips. 420-428 - Sotirios Xydis, George Economakos, Dimitrios Soudris, Kiamal Z. Pekmestzi:
High Performance and Area Efficient Flexible DSP Datapath Synthesis. 429-442 - Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack:
FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis. 443-456 - Aida Todri, Malgorzata Marek-Sadowska:
Reliability Analysis and Optimization of Power-Gated ICs. 457-468 - Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits. 469-482 - Wei Xu, Hongbin Sun, Xiaobin Wang, Yiran Chen, Tong Zhang:
Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM). 483-493 - Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim:
Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits. 494-498 - Adam B. Kinsman, Nicola Nicolici:
A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding. 499-503 - Sheng-Chuan Liang, Hao-Chiao Hong:
A Digitally Testable Sigma -Delta Modulator Using the Decorrelating Design-for-Digital-Testability. 503-507 - Yiyu Shi, Jinjun Xiong, Howard Chen, Lei He:
Runtime Resonance Noise Reduction with Current Prediction Enabled Frequency Actuator. 508-512 - Francisco J. Jaime, M. A. Sánchez, Javier Hormigo, Julio Villalba, Emilio L. Zapata:
High-Speed Algorithms and Architectures for Range Reduction Computation. 512-516 - Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee:
Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores. 516-520 - Ling Zhang, Yulei Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng:
On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals. 520-524
Volume 19, Number 4, April 2011
- Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim:
A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache. 525-537 - Shoushun Chen, Amine Bermak, Yan Wang:
A CMOS Image Sensor With On-Chip Image Compression Based on Predictive Boundary Adaptation and Memoryless QTD Algorithm. 538-547 - Xuebin Wu, Zhiyuan Yan:
Efficient CODEC Designs for Crosstalk Avoidance Codes Based on Numeral Systems. 548-558 - Ehab Anis Daoud, Nicola Nicolici:
Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation. 559-570 - Fu-Ching Yang, Yi-Ting Lin, Chung-Fu Kao, Ing-Jer Huang:
An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC. 571-584 - Tsung-Hsien Lin, Chao-Ching Chi, Wei-Hao Chiu, Yu-Hsiang Huang:
A Synchronous 50% Duty-Cycle Clock Generator in 0.35- μ m CMOS. 585-591 - Shih-Yuan Kao, Shen-Iuan Liu:
A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression. 592-602 - Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits. 603-614 - Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang:
Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques. 615-628 - Yuejian Wu, Sandy Thomson, Dale Mutcher, Eric Hall:
Built-In Functional Tests for Silicon Validation and System Integration of Telecom SoC Designs. 629-637 - Qiang Zhou, Jin Shi, Bin Liu, Yici Cai:
Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs. 638-646 - Nauman H. Khan, Syed M. Alam, Soha Hassoun:
Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies. 647-658 - Chun-Yu Hsieh, Hong-Wei Huang, Ke-Horng Chen:
A 1-V, 16.9 ppm/ $^{\circ}$ C, 250 nA Switched-Capacitor CMOS Voltage Reference. 659-667 - Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt:
A Multi-Granularity Power Modeling Methodology for Embedded Processors. 668-681 - Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang:
Modeling and Synthesis of Asynchronous Pipelines. 682-695 - Inwook Kong, Earl E. Swartzlander Jr.:
A Goldschmidt Division Method With Faster Than Quadratic Convergence. 696-700 - Jaehyouk Choi, Stephen T. Kim, Woonyun Kim, Kwan-Woo Kim, Kyutae Lim, Joy Laskar:
A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor. 701-705 - Hsieh-Hung Hsieh, Huan-Sheng Chen, Ping-Hsi Hung, Liang-Hung Lu:
Experimental 5-GHz RF Frontends for Ultra-Low-Voltage and Ultra-Low-Power Operations. 705-709 - Yuan-Ho Chen, Tsin-Yuan Chang, Chung-Yi Li:
High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree. 709-714 - Anita Kumari, Sanjukta Bhanja:
Landauer Clocking for Magnetic Cellular Automata (MCA) Arrays. 714-717 - Mariano Aguirre-Hernandez, Mónico Linares Aranda:
CMOS Full-Adders for Energy-Efficient Arithmetic Applications. 718-721
Volume 19, Number 5, May 2011
- Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies. 725-736 - Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit. 737-750 - Massimo Alioto:
Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard Cells. 751-762 - Hailong Jiao, Volkan Kursun:
Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits. 763-773 - Renatas Jakushokas, Eby G. Friedman:
Multi-Layer Interdigitated Power Distribution Networks. 774-786 - John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim:
An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization. 787-795 - Server Kasap, Khaled Benkrid:
High Performance Phylogenetic Analysis With Maximum Parsimony on Reconfigurable Hardware. 796-808 - Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay:
A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective. 809-817 - Woohyung Chun, Sungroh Yoon, Sangjin Hong:
Energy-Aware Interconnect Resource Reduction Through Buffer Access Manipulation for Data-Centric Applications. 818-831 - Jintae Kim, S. Limotyrakis, Chih-Kong Ken Yang:
Multilevel Power Optimization of Pipelined A/D Converters. 832-845 - Jingye Xu, Masud H. Chowdhury:
Fast Waveform Estimation (FWE) for Timing Analysis. 846-856 - Xin Chen, Jun Yang, Longxing Shi:
A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique. 857-868 - Rajiv V. Joshi, Rouwaida Kanj, Vinod Ramadurai:
A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design. 869-882 - Mohammad Sharifkhani, Ehsan Rahiminejad, Shah M. Jahinuzzaman, Manoj Sachdev:
A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs. 883-894 - Markus Myllylä, Joseph R. Cavallaro, Markku J. Juntti:
Architecture Design and Implementation of the Metric First List Sphere Detector Algorithm. 895-899 - Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi:
A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors. 900-904 - Ren-Jie Lee, Hung-Ming Chen:
Efficient Package Pin-Out Planning With System Interconnects Optimization for Package-Board Codesign. 904-909 - Jiajing Wang, A. Hoefler, Benton H. Calhoun:
An Enhanced Canary-Based System With BIST for SRAM Standby Power Reduction. 909-914 - Peiyi Zhao, Jason McNeely, Weidong Kuang, Nan Wang, Zhongfeng Wang:
Design of Sequential Elements for Low Power Clocking System. 914-918 - Koustav Bhattacharya, N. Ranganathan:
Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits. 918-923
Volume 19, Number 6, June 2011
- H.-C. Kuo, L.-C. Wu, H.-T. Huang, S.-T. Hsu, Y.-L. Lin:
A Low-Power High-Performance H.264/AVC Intra-Frame Encoder for 1080pHD Video. 925-938 - C.-W. Lin, M. C.-T. Chao, Y.-S. Huang:
A Novel Pixel Design for AM-OLED Displays Using Nanocrystalline Silicon TFTs. 939-952 - Arindam Basu, Paul E. Hasler:
A Fully Integrated Architecture for Fast and Accurate Programming of Floating Gates Over Six Decades of Current. 953-962 - Satendra Kumar Maurya, Lawrence T. Clark:
A Dynamic Longest Prefix Matching Content Addressable Memory for IP Routing. 963-972 - Jeffrey G. Mueller, Resve A. Saleh:
Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die Variations. 973-986 - Yun Ye, Frank Liu, Min Chen, Sani R. Nassif, Yu Cao:
Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness. 987-996 - M. Wang, Zili Shao, Jingling Xue:
On Reducing Hidden Redundant Memory Accesses for DSP Applications. 997-1010 - Jia Zhao, Sailaja Madduri, Ramakrishna Vadlamani, Wayne P. Burleson, Russell Tessier:
A Dedicated Monitoring Infrastructure for Multicore Processors. 1011-1022 - Saleh Abdel-Hafeez, Ann Gordon-Ross:
A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic. 1023-1033 - Christos Kyrkou, Theocharis Theocharides:
A Flexible Parallel Hardware Architecture for AdaBoost-Based Real-Time Object Detection. 1034-1047 - Markus Koester, Wayne Luk, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert:
Design Optimizations for Tiled Partially Reconfigurable Systems. 1048-1061 - Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi:
EGRA: A Coarse Grained Reconfigurable Architectural Template. 1062-1074 - Jonathan Rosenfeld, Eby G. Friedman:
A Distributed Filter Within a Switching Converter for Application to 3-D Integrated Circuits. 1075-1085 - Muhammad E. S. Elrabaa:
Robust Two-Phase RZ Asynchronous SoC Interconnects. 1086-1089 - Dimitris Magos, Ioannis Voyiatzis, Steffen Tarnick:
An Accumulator - Based Test-Per-Clock Scheme. 1090-1094 - Irith Pomeranz, Sudhakar M. Reddy:
On Functional Broadside Tests With Functional Propagation Conditions. 1094-1098 - Sangmin Kim, Gerald E. Sobelman, Hanho Lee:
A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes. 1099-1103 - Irith Pomeranz, Sudhakar M. Reddy:
Broadside and Functional Broadside Tests for Partial-Scan Circuits. 1104-1108 - Irith Pomeranz, Sudhakar M. Reddy:
Static Test Data Volume Reduction Using Complementation or Modulo- M Addition. 1108-1112 - Duo Sheng, Ching-Che Chung, Chen-Yi Lee:
A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications. 1113-1117 - Jing-Hu Li, Xing-Bao Zhang, Ming-Yan Yu:
A 1.2-V Piecewise Curvature-Corrected Bandgap Reference in 0.5 μ m CMOS Process. 1118-1122
Volume 19, Number 7, July 2011
- Hyun Woo Choi, Alfred V. Gomes, Abhijit Chatterjee:
Signal Acquisition of High-Speed Periodic Signals Using Incoherent Sub-Sampling and Back-End Signal Reconstruction Algorithms. 1125-1135 - Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers. 1136-1146