10th VLSI Design 1997: Hyderabad, India

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Session 1: Monday Keynote Address

Session 2: Physical Design

Session 3: Synthesis

Session 4: Delay Test and Timing

Session 5: High-Level Synthesis

Session 6: HW-SW Codesign

Session 7: Low-Power Design

Session 8: Parallel Exhibitor Presentations

Session 9: Verification

Session 10: VLSI Systems

Session 11: Testability Enhancement

Session 12: Banquet Keynote

Session 13: Tuesday Keynote Address

Session 14: Asynchronous Design

Session 15: Diagnosis

Session 16: Test and Fault Modeling

Session 17: Mixed-Signal Design

Session 18: Architecture

Session 9: ATPG and Fault Simulation

Session 20: Synthesis and CAD

Session 21: Design and Implementation

Session 22: Test and DFT

Session 23: Panel Discussion: The Future of the Indian Information Technology Industry - A CEO's Roundtable

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