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IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 23
Volume 23, Number 1, January 2015
- Krishnendu Chakrabarty:
Editorial. 1-17 - Yu-Hsuan Lee, Cheng-Wei Pan:
Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications. 18-29 - Mohammed Shoaib, Niraj K. Jha, Naveen Verma:
Signal Processing With Direct Computations on Compressively Sensed Data. 30-43 - Georgi I. Radulov, Patrick J. Quinn, Arthur H. M. van Roermund:
A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme. 44-53 - Hemasundar Mohan Geddada, Chang-Joon Park, Hyung-Joon Jeon, José Silva-Martínez, Aydin Ilker Karsilayan, Douglas Garrity:
Design Techniques to Improve Blocker Tolerance of Continuous-Time ΔΣ ADCs. 54-67 - Giovanni Causapruno, Gianvito Urgese, Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni:
Protein Alignment Systolic Array Throughput Optimization. 68-77 - I-Chyn Wey, Chien-Chang Peng, Feng-Yu Liao:
Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block. 78-87 - Szu-Chi Chung, Jing-Yu Wu, Hsing-Ping Fu, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee:
Efficient Hardware Architecture of ηT Pairing Accelerator Over Characteristic Three. 88-97 - Horng-Yuan Shih, Chun-Fan Chen, Yu-Chuan Chang, Yu-Wei Hu:
An Ultralow Power Multirate FSK Demodulator With Digital-Assisted Calibrated Delay-Line Based Phase Shifter for High-Speed Biomedical Zero-IF Receivers. 98-106 - Weifeng Sun, Caixia Han, Miao Yang, Shen Xu, Shengli Lu:
A Ripple Control Dual-Mode Single-Inductor Dual-Output Buck Converter With Fast Transient Response. 107-117 - Di-An Li, Malgorzata Marek-Sadowska, Sani R. Nassif:
A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures. 118-130 - Mohammad Abdur Rouf, Soontae Kim:
Low-Cost Control Flow Protection via Available Redundancies in the Microprocessor Pipeline. 131-141 - Yici Cai, Chao Deng, Qiang Zhou, Hailong Yao, Feifei Niu, Cliff N. Sze:
Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion. 142-155 - Mahdi Nikdast, Jiang Xu, Luan H. K. Duong, Xiaowen Wu, Zhehui Wang, Xuan Wang, Zhe Wang:
Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint. 156-169 - Zhongqi Li, Amer Qouneh, Madhura Joshi, Wangyuan Zhang, Xin Fu, Tao Li:
Aurora: A Cross-Layer Solution for Thermally Resilient Photonic Network-on-Chip. 170-183 - Meng-Hung Shen, Po-Chiun Huang:
A Wide-Range Multiport LC-Ladder Oscillator and Its Applications to a 1.2-10.1 GHz PLL. 184-188 - Manuel de la Guia Solaz, Richard Conway:
Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing. 189-193 - Wen-rui Zhu, Haigang Yang, Tongqiang Gao, Fei Liu, Tao Yin, Dandan Zhang, Hongfeng Zhang:
A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler. 194-197 - Hyung-Joon Jeon, José Silva-Martínez, Sebastian Hoyos:
A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain. 198-202 - Yuan-Ho Chen:
An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability. 203-207 - Himanshu Markandeya, Pedro P. Irazoqui, Kaushik Roy:
Low-Energy Two-Stage Algorithm for High Efficacy Epileptic Seizure Detection. 208-212 - Mohammed Ziaur Rahman, Lindsay Kleeman, Mohammad Ashfak Habib:
Recursive Approach to the Design of a Parallel Self-Timed Adder. 213-217
Volume 23, Number 2, February 2015
- Jienan Chen, Jianhao Hu, Shuyang Lee, Gerald E. Sobelman:
Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems. 221-229 - Chung-Hsien Chang, Bo-Wei Chen, Shi-Huang Chen, Jhing-Fa Wang, Yu-Hao Chiu:
Low-Complexity Hardware Design for Fast Solving LSPs With Coordinated Polynomial Solution. 230-243 - Chih-Lin Chen, Deng-Shian Wang, Jie-Jyun Li, Chua-Chin Wang:
A Voltage Monitoring IC With HV Multiplexer and HV Transceiver for Battery Management Systems. 244-253 - Jeongkyu Hong, Jesung Kim, Soontae Kim:
Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories. 254-265 - Xuan Wang, Jiang Xu, Wei Zhang, Xiaowen Wu, Yaoyao Ye, Zhehui Wang, Mahdi Nikdast, Zhe Wang:
Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC. 266-279 - Xiaofei Wang, Qianying Tang, Pulkit Jain, Dong Jiao, Chris H. Kim:
The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications. 280-291 - James Sebastian Guido, Alexandre Yakovlev:
Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging. 292-305 - Diogo Brito, Taimur Gibran Rabuske, Jorge R. Fernandes, Paulo F. Flores, José Monteiro:
Quaternary Logic Lookup Table in Standard CMOS. 306-316 - Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty, Sung Kyu Lim:
Scan Test of Die Logic in 3-D ICs Using TSV Probing. 317-330 - Afsaneh Nassery, Srinath Byregowda, Sule Ozev, Marian Verhelst, Mustapha Slamani:
Built-In Self-Test of Transmitter I/Q Mismatch and Nonlinearity Using Self-Mixing Envelope Detector. 331-341 - Aritra Banerjee, Abhijit Chatterjee:
Signature Driven Hierarchical Post-Manufacture Tuning of RF Systems for Performance and Power. 342-355 - Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS. 356-368 - Dean Michael Ancajas, Kshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy:
Wearout Resilience in NoCs Through an Aging Aware Adaptive Routing Algorithm. 369-373 - Azadeh Alsadat Emrani Zarandi, Amir Sabbagh Molahosseini, Mehdi Hosseinzadeh, Saeid Sorouri, Samuel Antão, Leonel Sousa:
Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations. 374-378 - Minghe Xu, Zhenpeng Bian, Ruohe Yao:
Fast Sign Detection Algorithm for the RNS Moduli Set 2n+1-1, 2n-1, 2n. 379-383 - Zhen Gao, Pedro Reviriego, Wen Pan, Zhan Xu, Ming Zhao, Jing Wang, Juan Antonio Maestro:
Fault Tolerant Parallel Filters Based on Error Correction Codes. 384-387 - Marco Lanuzza, Pasquale Corsonello, Stefania Perri:
Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs. 388-391 - Amr M. A. Hussien, Rahul Amin, Ahmed M. Eltawil, Jim Martin:
Energy Aware Mapping for Reconfigurable Wireless MPSoCs. 392-396 - Zao Liu, Sheldon X.-D. Tan, Xin Huang, Hai Wang:
Task Migrations for Distributed Thermal Management Considering Transient Effects. 397-401 - Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung:
Z-TCAM: An SRAM-based Architecture for TCAM. 402-406 - Christelle Hobeika, Claude Thibeault, Jean-François Boland:
Functional Constraint Extraction From Register Transfer Level for ATPG. 407-412
Volume 23, Number 3, March 2015
- Jung-Hyun Park, Heechai Kang, Dong-Hoon Jung, Kyungho Ryu, Seong-Ook Jung:
Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs. 413-421 - Yuki Okamoto, Takashi Nakagawa, Takeshi Aoki, Masataka Ikeda, Munehiro Kozuma, Takeshi Osada, Yoshiyuki Kurokawa, Takayuki Ikeda, Naoto Yamade, Yutaka Okazaki, Hidekazu Miyairi, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki:
A Boosting Pass Gate With Improved Switching Characteristics and No Overdriving for Programmable Routing Switch Based on Crystalline In-Ga-Zn-O Technology. 422-434 - Martin Omaña, Daniele Rossi, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Asifur Rahman, Simon Tam:
Low-Cost On-Chip Clock Jitter Measurement Scheme. 435-443 - Xuan-Dien Do, Huy-Hieu Nguyen, Seok-Kyun Han, Dong Sam Ha, Sang-Gug Lee:
A Self-Powered High-Efficiency Rectifier With Automatic Resetting of Transducer Capacitance in Piezoelectric Energy Harvesting Systems. 444-453 - Soydan Redif, Server Kasap:
Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications. 454-465 - Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan:
Diagnosis and Layout Aware (DLA) Scan Chain Stitching. 466-479 - Xuexin Liu, Hao Yu, Sheldon X.-D. Tan:
A GPU-Accelerated Parallel Shooting Algorithm for Analysis of Radio Frequency and Microwave Integrated Circuits. 480-492 - Ying Wang, Yinhe Han, Lei Zhang, Binzhang Fu, Cheng Liu, Huawei Li, Xiaowei Li:
Economizing TSV Resources in 3-D Network-on-Chip Design. 493-506 - Dimitrios Rodopoulos, Antonis Papanikolaou, Francky Catthoor, Dimitrios Soudris:
Demonstrating HW-SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane. 507-519 - Seunghan Lee, Kyungsu Kang, Chong-Min Kyung:
Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache. 520-533 - Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj, Ajay N. Bhoj, Matthew M. Ziegler, Phil Oldiges, Pranita Kerber, Robert Wong, Terence Hook, Sudesh Saroop, Carl Radens, Chun-Chen Yeh:
Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction. 534-543 - Ing-Chao Lin, Yu-Hung Cho, Yi-Ming Yang:
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic. 544-556 - Yung-Hui Chung, Jieh-Tsorng Wu:
A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS. 557-566 - Chia-Yu Yao, Yung-Hsiang Ho, Yi-Yao Chiu, Rong-Jyi Yang:
Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line. 567-574 - Xuexin Liu, Kuangya Zhai, Zao Liu, Kai He, Sheldon X.-D. Tan, Wenjian Yu:
Parallel Thermal Analysis of 3-D Integrated Circuits With Liquid Cooling on CPU-GPU Platforms. 575-579 - Mohamed Tagelsir Mohammadat, Noohul Basheer Zain Ali, Fawnizu Azmadi Hussin, Mark Zwolinski:
Resistive Open Faults Detectability Analysis and Implications for Testing Low Power Nanometric ICs. 580-583 - Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, Marco Ottavi:
A Synergetic Use of Bloom Filters for Error Detection and Correction. 584-587 - Yong-Hun Kim, Young-Ju Kim, Tae-Ho Lee, Lee-Sup Kim:
An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS. 588-592 - Irith Pomeranz:
Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set. 593-597 - Eric P. Kim, Daniel J. Baker, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones:
A 3.6-mW 50-MHz PN Code Acquisition Filter via Statistical Error Compensation in 180-nm CMOS. 598-602 - Pedro Miguens Matutino, Ricardo Chaves, Leonel Sousa:
Arithmetic-Based Binary-to-RNS Converter Modulo {2n±k} for jn-bit Dynamic Range. 603-607
Volume 23, Number 4, April 2015
- Supriya Karmakar, John A. Chandy, Faquir C. Jain:
Unipolar Logic Gates Based on Spatial Wave-Function Switched FETs. 609-618 - Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama:
Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path. 619-630 - Abhishek Ambede, Smitha K. G., A. Prasad Vinod:
Flexible Low Complexity Uniform and Nonuniform Digital Filter Banks With High Frequency Resolution for Multistandard Radios. 631-641 - Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross:
Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks. 642-653 - Jingtong Hu, Mimi Xie, Chen Pan, Chun Jason Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha:
Low Overhead Software Wear Leveling for Hybrid PCM + DRAM Main Memory on Embedded Systems. 654-663 - Guoyue Jiang, Zhaolin Li, Fang Wang, Shaojun Wei:
A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks. 664-677 - Xiaowen Wu, Jiang Xu, Yaoyao Ye, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Zhe Wang:
An Inter/Intra-Chip Optical Network for Manycore Processors. 678-691 - Jun Han, Yang Li, Zhiyi Yu, Xiaoyang Zeng:
A 65 nm Cryptographic Processor for High Speed Pairing Computation. 692-701 - Moshe Avital, Hadar Dagan, Osnat Keren, Alexander Fish:
Randomized Multitopology Logic Against Differential Power Analysis. 702-711 - Hoi Lee, Zhe Hua, Xiwen Zhang:
A Reconfigurable 2×2.5×3×4× SC DC-DC Regulator With Fixed On-Time Control for Transcutaneous Power Transmission. 712-722 - Ruzica Jevtic, Hanh-Phuc Le, Milovan Blagojevic, Stevo Bailey, Krste Asanovic, Elad Alon, Borivoje Nikolic:
Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors. 723-730 - Hao Liang, Wei Zhang, Jiale Huang, Shengqi Yang, Pallav Gupta:
Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure. 731-742 - Daniele Rossi, Martin Omaña, Cecilia Metra, Alessandro Paccagnella:
Impact of Bias Temperature Instability on Soft Error Susceptibility. 743-751 - Heechai Kang, Jisu Kim, Hanwool Jeong, Younghwi Yang, Seong-Ook Jung:
Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory. 752-765 - Ming-Chiuan Su, Shyh-Jye Jou, Wei-Zen Chen:
A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs. 766-770 - Bo Zhao, Huazhong Yang:
Supply-Noise Interactions Among Submodules Inside a Charge-Pump PLL. 771-775 - Fareena Saqib, Dylan Ismari, Charles Lamech, Jim Plusquellic:
Within-Die Delay Variation Measurement and Power Transient Analysis Using REBEL. 776-780 - R. R. Manikandan, Abhishek Kumar, Bharadwaj Amrutur:
A Digital Frequency Multiplication Technique for Energy Efficient Transmitters. 781-785 - Zhentao Xu, Wei Wang, Ning Ning, Wei Meng Lim, Yang Liu, Qi Yu:
A Supply Voltage and Temperature Variation-Tolerant Relaxation Oscillator for Biomedical Systems Based on Dynamic Threshold and Switched Resistors. 786-790 - Jung-Mao Lin, Ching-Yuan Yang, Hsin-Ming Wu:
A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling. 791-795 - Sagar Venkatesh Gubbi, Bharadwaj Amrutur:
All Digital Energy Sensing for Minimum Energy Tracking. 796-800
Volume 23, Number 5, May 2015
- Debasri Saha, Susmita Sur-Kolay:
Watermarking in Hard Intellectual Property for Pre-Fab and Post-Fab Verification. 801-809 - Sujoy Sinha Roy, Junfeng Fan, Ingrid Verbauwhede:
Accelerating Scalar Conversion for Koblitz Curve Cryptoprocessors on Hardware Platforms. 810-818 - Yingjie Lao, Keshab K. Parhi:
Obfuscating DSP Circuits via High-Level Transformations. 819-830 - Yu Zheng, Xinmu Wang, Swarup Bhunia:
SACCI: Scan-Based Characterization Through Clock Phase Sweep for Counterfeit Chip Detection. 831-841 - Jamshaid Sarwar Malik, Ahmed Hemani, Jameel Nawaz Malik, Ben Slimane, Nasirud Din Gohar:
Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI. 842-855 - Yi-Ming Wang, Shih-Nung Wei:
Range Unlimited Delay-Interleaving and -Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit. 856-868 - Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly:
Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips. 869-878 - Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li:
Data Remapping for Static NUCA in Degradable Chip Multiprocessors. 879-892 - Gabriel Luca Nazar, Leonardo Pereira Santos, Luigi Carro:
Fine-Grained Fast Field-Programmable Gate Array Scrubbing. 893-904 - Lijun Wu, Huijia Huang, Kaile Su, Shaowei Cai, Xiaosong Zhang:
An I/O Efficient Model Checking Algorithm for Large-Scale Systems. 905-915 - Shankar Thirunakkarasu, Bertan Bakkaloglu:
Built-in Self-Calibration and Digital-Trim Technique for 14-Bit SAR ADCs Achieving ±1 LSB INL. 916-925 - Luis Henrique de Carvalho Ferreira, Sameer R. Sonkusale:
A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process. 926-934 - Yuh-Shyan Hwang, Yi-Tsen Ku, An Liu, Chia-Hsuan Chen, Jiann-Jong Chen:
A New Efficiency-Improvement Low-Ripple Charge-Pump Boost Converter Using Adaptive Slope Generator With Hysteresis Voltage Comparison Techniques. 935-943 - Yun Yin, Baoyong Chi, Zhigang Sun, Xinwang Zhang, Zhihua Wang:
A 0.1-6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS. 944-957 - Chien-Yu Lu, Ching-Te Chuang, Shyh-Jye Jou, Ming-Hsien Tu, Ya-Ping Wu, Chung-Ping Huang, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao:
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist. 958-962 - Debajit Bhattacharya, Ajay N. Bhoj, Niraj K. Jha:
Design of Efficient Content Addressable Memories in High-Performance FinFET Technology. 963-967 - Pedro Reviriego, Salvatore Pontarelli, Adrian Evans, Juan Antonio Maestro:
A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes. 968-972 - Ze-ke Wang, Xue Liu, Bingsheng He, Feng Yu:
A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT. 973-977 - Yong Chen, Pui-In Mak, Yan Wang:
A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable for 10-Gb/s I/O Links. 978-982 - Ching-Che Chung, Duo Sheng, Wei-Da Ho:
A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator. 983-987 - Young-Ju Kim, Sang-Hye Chung, Lee-Sup Kim:
A Forwarded Clock Receiver Based on Injection-Locked Oscillator With AC-Coupled Clock Multiplication Unit in 0.13~µm CMOS. 988-992
Volume 23, Number 6, June 2015
- Josep Rius:
Supply Noise and Impedance of On-Chip Power Distribution Networks in ICs With Nonuniform Power Consumption and Interblock Decoupling Capacitors. 993-1004 - Somnath Paul, Aswin Raghav Krishna, Wenchao Qian, Robert Karam, Swarup Bhunia:
MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications. 1005-1016 - Ali Mirtar, Sujit Dey, Anand Raghunathan:
Joint Work and Voltage/Frequency Scaling for Quality-Optimized Dynamic Thermal Management. 1017-1030 - Daniele Rossi, Martin Omaña, Daniele Giaffreda, Cecilia Metra:
Modeling and Detection of Hotspot in Shaded Photovoltaic Cells. 1031-1039 - Salomon Beer, Ran Ginosar:
Eleven Ways to Boost Your Synchronizer. 1040-1049 - Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. 1050-1062 - Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
Low-Power Programmable PRPG With Test Compression Capabilities. 1063-1076