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• 
  Manfred Glesner, Ricardo Augusto da Luz Reis, Hans Eveking, Vincent John Mooney III, Leandro Soares Indrusiak, Peter Zipf:
  IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003. Technische Universität Darmstadt, Insitute of Microelectronic Systems 2003, ISBN 3-901882-17-0

Copies of these proceedings may be ordered from:

Technische Universität Darmstadt
Institute of Microelectronic Systems
Karlstr. 15, D-64283 Darmstadt, Germany
vlsi2003@mes.tu-darmstadt.de
http://www.microelectronic.e-technik.tu-darmstadt.de
Phone: +49 6151 165136
Fax: +49 6151 164936

• 
  Werner Weber:
  Ambient Intelligence - Key Technologies in the Communication Age. VLSI-SOC 2003: 1
• 
  Shekhar Borkar:
  Exponential Challenges, Exponential Rewards - The future of Moore's Law. VLSI-SOC 2003: 2
• 
  Andreas Kirschbaum:
  Towards safer cars - Microeletronics in Automotive. VLSI-SOC 2003: 3

• 
  Radu Marculescu:
  Designing Application Specific Networks-On-Chip: Five easy pieces. VLSI-SOC 2003: 5
• 
  Narayanan Vijaykrishnan:
  Energy Efficient and Reliable System Design. VLSI-SOC 2003: 6-9
• 
  Klaus Winkelmann:
  Formal Verification. VLSI-SOC 2003: 10-

• 
  Andreas Hermann, Markus Olbrich, Erich Barke:
  Substrate Modeling and Noise Reduction in Mixed-Signal Circuits. VLSI-SOC 2003: 13-18
• 
  Johanna Tuominen, Pasi Liljeberg, Jouni Isoaho:
  Self-Timed Approach for Reducing On-Chip Switching Noise. VLSI-SOC 2003: 19-24
• 
  João M. S. Silva, Luís Miguel Silveira:
  Dynamic Models for Substrate Coupling in Mixed-Mode Systems. VLSI-SOC 2003: 25-30
• 
  Timm Ostermann, Wolfgang Gut, Christian Bacher, Bernd Deutschmann:
  Measures to Reduce the Electromagnetic Emission of a SoC. VLSI-SOC 2003: 31-

• 
  Philippe Coussy, Adel Baganne, Eric Martin:
  Communication and Timing Constraints Analysis for IP Design and Integration. VLSI-SOC 2003: 38-43
• 
  Thomas Hollstein, Ralf Ludewig, Christoph Mager, Peter Zipf, Manfred Glesner:
  A hierarchical generic approach for on-chip communication, testing and debugging of SoCs. VLSI-SOC 2003: 44-49
• 
  Maciej Borkowski, Juha Häkkinen, Juha Kostamovaara:
  A Sigma-Delta Modulator Development Environment for Fractional-N Frequency Synthesis. VLSI-SOC 2003: 50-54
• 
  Axel G. Braun, Jan B. Freuer, Joachim Gerlach, Wolfgang Rosenstiel:
  Automated Conversion of SystemC Fixed-Point Data Types for Hardware Synthesis. VLSI-SOC 2003: 55-

• 
  Cristian Chitu, Manfred Glesner:
  High Performance of an AES-Rijndael ASIC working in OCB/ECB Modes of Operation. VLSI-SOC 2003: 62-67
• 
  Nicolas Sklavos, Odysseas G. Koufopavlou:
  Architectures and FPGA Implementations of the SCO(-1, -2, -3) Ciphers Family. VLSI-SOC 2003: 68-73
• 
  Christophe Layer:
  High Performance System Architecture of an Associative Computing Engine Optimised for Search Algorithms. VLSI-SOC 2003: 74-

• 
  Nicole Drechsler, Rolf Drechsler:
  Exploration of Sequential Depth by Evolutionary Algorithms. VLSI-SOC 2003: 81-85
• 
  Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani:
  Validation of asynchronous circuit specifications using IF/CADP. VLSI-SOC 2003: 86-91
• 
  Anneliese Amschler Andrews, Andrew O'Fallon, Tom Chen:
  A Rule-Based Software Testing Method for VHDL Models. VLSI-SOC 2003: 92-

• 
  Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny:
  Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects. VLSI-SOC 2003: 99-104
• 
  Marios Kesoulis, Dimitrios Soudris, Christos S. Koukourlis, Adonios Thanailakis:
  Designing Low Power Direct Digital Frequency Synthesizers. VLSI-SOC 2003: 105-110
• 
  José Augusto Miranda Nacif, Flávio Miana de Paula, Harry Foster, Claudionor José Nunes Coelho Jr., Antônio Otávio Fernandes:
  The Chip is Ready. Am I done? On-chip Verification using Assertion Processors. VLSI-SOC 2003: 111-

• 
  Ali Ahmadinia, Jürgen Teich:
  Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead. VLSI-SOC 2003: 118-122
• 
  Young-Su Kwon, Woo-Seung Yang, Chong-Min Kyung:
  Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection. VLSI-SOC 2003: 123-128
• 
  Jürgen Becker, Michael Hübner, Michael Ullmann:
  Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations. VLSI-SOC 2003: 129-

• 
  Giuseppe Bonfini, Cristian Garbossa, Roberto Saletti:
  A Switched Opamp-based 10-b Integrated ADC for Ultra Low-power Applications. VLSI-SOC 2003: 136-141
• 
  Glenn Wolfe, Mengmeng Ding, Ranga Vemuri:
  Adaptive Sampling and Modeling of Analog Circuit Performance Parameters. VLSI-SOC 2003: 142-

• 
  Péter Szántó, Béla Fehér:
  3D rendering using FPGAs. VLSI-SOC 2003: 149-154
• 
  Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Mark Bernd Kulaczewski, Peter Pirsch:
  HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing. VLSI-SOC 2003: 155-160
• 
  Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner:
  Exploring the Capabilities of Reconfigurable Hardware for OFDM-based WLANs. VLSI-SOC 2003: 161-166
• 
  Mihail Petrov, Abdulfattah Mohammad Obeid, Tudor Murgan, Peter Zipf, Jörg Brakensiek, Bernard Ölkrug, Manfred Glesner:
  An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders. VLSI-SOC 2003: 167-

• 
  Alexandre M. Amory, Leandro A. Oliveira, Fernando Gehm Moraes:
  Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip Architectures. VLSI-SOC 2003: 174-179
• 
  Wei Zou, Chris Chu, Sudhakar M. Reddy, Irith Pomeranz:
  Optimizing SOC Test Resources using Dual Sequences. VLSI-SOC 2003: 180-185
• 
  Elham Safi, Reihaneh Saberi, Zohreh Karimi, Zainalabedin Navabi:
  Processor Testing Using an ADL Description and Genetic Algorithms. VLSI-SOC 2003: 186-

• 
  Cristiano Lazzari, Cristiano Viana Domingues, José Luís Almada Güntzel, Ricardo Augusto da Luz Reis:
  A New Macro-cell Generation Strategy for three metal layer CMOS Technologies. VLSI-SOC 2003: 193-197
• 
  Pavel V. Nikitin, Winnie Yam, Chuanjin Richard Shi:
  Parametric Equivalent Circuit Extraction for VLSI Structures. VLSI-SOC 2003: 198-203
• 
  Renato Fernandes Hentschke, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis:
  A study on the performance of fast initial placement algorithms. VLSI-SOC 2003: 204-

• 
  Juha Häkkinen, Maciej Borkowski, Juha Kostamovaara:
  A PLL-Based RF Synthesizer Test System. VLSI-SOC 2003: 211-214
• 
  Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi:
  Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing. VLSI-SOC 2003: 215-220
• 
  Andrea S. Brogna, Franco Bigongiari, Silvia Chiusano, Paolo Prinetto, Roberto Saletti:
  Designing and Testing High Dependable Memories for Aerospace Applications. VLSI-SOC 2003: 221-

• 
  Tapio Ristimäki, Jari Nurmi:
  Reprogrammable Algorithm Accelerator IP Block. VLSI-SOC 2003: 228-232
• 
  Nikolaos Kavvadias, Spiridon Nikolaidis:
  Tradeoffs in the Design Space Exploration of Application-Specific Processors. VLSI-SOC 2003: 233-238
• 
  Antonio Carlos Schneider Beck, Luigi Carro:
  Low Power Java Processor for Embedded Applications. VLSI-SOC 2003: 239-

• 
  Stephan Henzler, Markus Koban, Doris Schmitt-Landsiedel, Jörg Berthold, Georg Georgakos:
  Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes. VLSI-SOC 2003: 246-251
• 
  Adam Golda, Andrzej Kos:
  Static Versus Dynamic Power Losses in CMOS VLSI Systems Considering Temperature. VLSI-SOC 2003: 252-257
• 
  Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis:
  Evaluation Methodology for Single Electron Encoded Threshold Logic Gates. VLSI-SOC 2003: 258-262
• 
  Alan J. Drake, Kevin J. Nowka, Richard B. Brown:
  Evaluation of Dynamic-Threshold Logic for Low-Power VLSI Design in 0.13um PD-SOI. VLSI-SOC 2003: 263-

• 
  Chia-Ming Hsu, Tien-Fu Chen:
  Flexible Heterogeneous Multicore Architectures for Media Processing via Customized Long Instruction Words. VLSI-SOC 2003: 270-275
• 
  Daniel Mesquita, Lionel Torres, Fernando Gehm Moraes, Gilles Sassatelli, Michel Robert:
  Are coarse grain reconfigurable architectures suitable for cryptography? VLSI-SOC 2003: 276-281
• 
  Karim Ben Chehida, Michel Auguin:
  Partitioning Reactive Data Flow Applications On Dynamically Reconfigurable Systems. VLSI-SOC 2003: 282-287
• 
  Jürgen Becker, Alexander Thomas, Maik Scheer:
  Datapath and Compiler Integration of Coarse-grain Reconfigurable XPP-Arrays into Pipelined RISC Processors. VLSI-SOC 2003: 288-

• 
  Tuomas Järvinen, Perttu Salmela, Teemu Sipilä, Jarmo Takala:
  In-Place Storage of Path Metrics in Viterbi Decoders. VLSI-SOC 2003: 295-300
• 
  Juan Manuel García Chamizo, María Teresa Signes Pont, Higinio Mora Mora, Gregorio de Miguel Casado:
  Hough Transform recursive evaluation using Distributed Arithmetic. VLSI-SOC 2003: 301-306
• 
  Eduardo A. C. da Costa, José C. Monteiro, Sergio Bampi:
  Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths. VLSI-SOC 2003: 307-

• 
  Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan:
  Crosstalk Immune Coding from Area and Power Perspective for high performance AMBA based SoC systems. VLSI-SOC 2003: 314-317
• 
  Fernando Gehm Moraes, Aline Mello, Leandro Möller, Luciano Ost, Ney Laert Vilar Calazans:
  A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping. VLSI-SOC 2003: 318-323
• 
  Michael S. McCorquodale, Eric D. Marsman, Robert M. Senger, Fadi H. Gebara, Richard B. Brown:
  Microsystem and SoC Design with UMIPS. VLSI-SOC 2003: 324-

• 
  Valentina Ciriani, Anna Bernasconi, Rolf Drechsler:
  Testability of SPP Three-Level Logic Networks. VLSI-SOC 2003: 331-336
• 
  Ilia Polian, Bernd Becker:
  Reducing ATE Cost in System-on-Chip Test. VLSI-SOC 2003: 337-342
• 
  Maciej Bellos, Xrysovalantis Kavousianos, Dimitris Nikolos, Dimitri Kagaris:
  DV-TSE: Difference Vector Based Test Set Embedding. VLSI-SOC 2003: 343-

• 
  Juan Manuel García Chamizo, Jerónimo Mora Pascual, Higinio Mora Mora, María Teresa Signes Pont:
  Calculation Methodology for Flexible Arithmetic Processing. VLSI-SOC 2003: 350-355
• 
  Radu Dogaru, Cristian Chitu, Manfred Glesner:
  A Versatile Cellular Neural Circuit Based on a Multi-nested Approach: Functional Capabilities and Applications. VLSI-SOC 2003: 356-361
• 
  Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch:
  Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures. VLSI-SOC 2003: 362-

• 
  Shrutin Ulman:
  Delay and Short Circuit Power Estimation for a Submicron CMOS Inverter driving a CRC-PI Interconnect Load. VLSI-SOC 2003: 369-374
• 
  Martin Margala, Quentin Diduck, Eric Moule:
  1.8V 0.18µm CMOS Novel Successive Approximation ADC. VLSI-SOC 2003: 375-379
• 
  Martin Margala, John C. Liobe, Quentin Diduck:
  Deep-Submicron CMOS Design Methodology for High-Performance Low-Power Analog-to-Digital Converters. VLSI-SOC 2003: 380-385
• 
  Martin Margala, Magdy A. El-Moursy, Ali El-Moursy, Junmou Zhang, Wendi Beth Heinzelman:
  1-V ADPCM Processor for Low-Power Wireless Applications. VLSI-SOC 2003: 386-393
• 
  Ehsan Atoofian, Zainalabedin Navabi:
  A Low Power BIST Architecture for FPGA Look-Up Table Testing. VLSI-SOC 2003: 394-397
• 
  Adão Antônio de Souza Jr., Luigi Carro:
  An All-Digital ADC for Instrumentation within SOCs. VLSI-SOC 2003: 398-403
• 
  Diego Caldas Salengue, João Baptista dos Santos Martins, Cesar Ramos Rodrigues, André Luiz Aita:
  FPGA Implementation of a VVI Temporary Pacemaker Digital Control. VLSI-SOC 2003: 404-409
• 
  Fernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi:
  Applying the GM/ID method in the analysis and design of Miller Amplifier, Comparator and GM-C PASS-B. VLSI-SOC 2003: 410-415
• 
  Hemanth Sampath, Ranga Vemuri:
  MSL: A High-Level Language for Parameterized Analog and Mixed Signal Layout Generators. VLSI-SOC 2003: 416-421
• 
  André Luiz Aita, João Baptista dos Santos Martins, César Augusto Prior, Cesar Ramos Rodrigues:
  Low-Power High-CMRR CMOS Instrumentation Amplifier for Biomedical Applications. VLSI-SOC 2003: 422-425
• 
  Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
  A Genetic Approach To Bus Encoding. VLSI-SOC 2003: 426-431
• 
  Arturo Méndez Patiño, Marcos Martínez Peiró:
  2D-DCT Implementation on FPGA by Polynomial Transformation in Two-Dimensions. VLSI-SOC 2003: 432-438
• 
  Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Petri Liuha:
  FPGA-Based Variable Length Decoders. VLSI-SOC 2003: 437-441
• 
  Stephan Bingemer, Peter Zipf, Manfred Glesner:
  An Integrated Model Bridging the Gap between Technology and Economy. VLSI-SOC 2003: 442-

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