default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDICCD 2004: San Jose, CA, USA
- 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings. IEEE Computer Society 2004, ISBN 0-7695-2231-9
Session 1
Session 1.1 High-Speed and Energy-Efficient Circuit Design
- Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara:
PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks. 6-11 - Srinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag:
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses. 12-17 - Justin Hensley, Anselmo Lastra, Montek Singh:
An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices. 18-25 - Robert D. Kenney, Michael J. Schulte, Mark A. Erle:
A High-Frequency Decimal Multiplier. 26-29 - Magnus Själander
, Henrik Eriksson, Per Larsson-Edefors:
An Efficient Twin-Precision Multiplier. 30-33
Session 1.2 Energy-Efficient Processor Microarchitecture (1)
- Aneesh Aggarwal, Manoj Franklin, Oguz Ergin:
Defining Wakeup Width for Efficient Dynamic Scheduling. 36-41 - Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim:
Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure. 42-47 - Pedro Chaparro, José González, Antonio González:
Thermal-Aware Clustered Microarchitectures. 48-53 - Yu Bai, R. Iris Bahar:
Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm. 54-57
Session 1.3 Scan Design and Test
- Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy:
A Novel Low-Power Scan Design Technique Using Supply Gating. 60-65 - Masayuki Tsukisaka, Masashi Imai, Takashi Nanya:
Asynchronous Scan-Latch controller for Low Area Overhead DFT. 66-71 - Sule Ozev, Alex Orailoglu:
End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths. 72-77 - Ho Fai Ko, Nicola Nicolici:
Functional Illinois Scan Design at RTL. 78-81 - Irith Pomeranz, Sudhakar M. Reddy:
On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan. 82-84
Session 2
Session 2.1 Routing and Floorplanning
- Hasan Arslan, Shantanu Dutt:
A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits. 86-92 - Tianpei Zhang, Sachin S. Sapatnekar:
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. 93-98 - Muhammet Mustafa Ozdal, Martin D. F. Wong:
A Two-Layer Bus Routing Algorithm for High-Speed Boards. 99-105 - Martin D. F. Wong:
Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers. 106-110
Session 2.2 Formal Verification Embedded Tutorial
- Chao Wang, Gary D. Hachtel, Fabio Somenzi:
Fine-Grain Abstraction and Sequential Don't Cares for Large Scale Model Checking. 112-118 - Miroslav N. Velev:
Comparative Study of Strategies for Formal Verification of High-Level Processors. 119-124
Session 2.3 Signal Integrity and Leakage
- Srivathsan Krishnamohan, Nihar R. Mahapatra:
A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits. 126-131 - Jihong Ren, Mark R. Greenstreet:
A Signal Integrity Test Bed for PCB Buses. 132-137 - Saumil Shah, Kanak Agarwal, Dennis Sylvester:
A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters. 138-143 - John C. Lach, Jason Brandon, Kevin Skadron:
A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs. 144-150
Session 3
Session 3.1 Special Session on High-Performance On-Chip Communication.
- Davide Pandini, Cristiano Forzan, Livio Baldi:
Design Methodologies and Architecture Solutions for High-Performance Interconnects. 152-159 - Mario R. Casu, Luca Macchiarulo:
On-Chip Transparent Wire Pipelining. 160-167 - Radu Marculescu, Diana Marculescu, Larry T. Pileggi:
Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems. 168-173 - Gérard Mas, Philippe Martin:
Network-on-Chip: The Intelligence is in The Wire. 174-177
Session 3.2 Test Generation and Characterization
- Jinkyu Lee, Nur A. Touba:
Low Power Test Data Compression Based on LFSR Reseeding. 180-185 - Jui-Jer Huang, Jiun-Lang Huang:
An Infrastructure IP for On-Chip Clock Jitter Measurement. 186-191 - Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Diagnosis of Hold Time Defects. 192-199 - Baris Arslan, Ozgur Sinanoglu, Alex Orailoglu:
Extending the Applicability of Parallel-Serial Scan Designs. 200-203 - Roy Emek, Itai Jaeger, Yoav Katz, Yehuda Naveh:
Quality Improvement Methods for System-Level Stimuli Generation. 204-206
Session 3.3 Physically-Aware Design Tools
- Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma:
XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs. 208-215 - Ruiming Chen, Hai Zhou:
A Flexible Data Structure for Efficient Buffer Insertion. 216-221 - Madhubanti Mukherjee, Ranga Vemuri:
Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems. 222-227 - Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar:
Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits. 228-233
Session 4
Session 4.1 Energy-Efficient Processor Microarchitecture (2)
- Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang:
Best of Both Latency and Throughput. 236-243 - Nikil Mehta, Brian Singer, R. Iris Bahar, Michael Leuchtenburg, Richard S. Weiss:
Fetch Halting on Critical Load Misses. 244-249 - Grigorios Magklis, José González, Antonio González:
Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2. 250-255
Session 4.2 Power and Timing Optimization
- Feng Gao, John P. Hayes:
Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction. 258-264 - Kai Wang, Malgorzata Marek-Sadowska:
Potential Slack Budgeting with Clock Skew Optimization. 265-271 - Murari Mani, Michael Orshansky:
A New Statistical Optimization Algorithm for Gate Sizing. 272-277
Session 4.3 Novel Processor Design
- Mark A. Franklin, Roger D. Chamberlain, Michael Henrichs, E. F. Berkley Shands, Jason White:
An Architecture for Fast Processing of Large Unstructured Data Sets. 280-287 - Roland E. Wunderlich, James C. Hoe:
In-System FPGA Prototyping of an Itanium Microarchitecture. 288-294 - Chun-Ho Kim, Lee-Sup Kim:
Adaptive Selection of an Index in a Texture Cache. 295-300
Session 5
Session 5.1 Emerging Technologies Special Session
- Michael T. Niemier, Ramprasad Ravichandran, Peter M. Kogge:
Using Circuits and Systems-Level Research to Drive Nanotechnology. 302-309 - Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka:
FPGA Emulation of Quantum Circuits. 310-315 - Bryan Black, Donald Nelson, Clair Webb, Nick Samra:
3D Processing Technology and Its Impact on iA32 Microprocessors. 316-318
Session 5.2 Cache Memory Design
- Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutmann:
Cache Array Architecture Optimization at Deep Submicron Technologies. 320-325 - Joshua L. Kihm, Daniel A. Connors:
Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling. 326-331 - Alexander V. Veidenbaum, Dan Nicolaescu:
Low Energy, Highly-Associative Cache Design for Embedded Processors. 332-335
Session 6
Session 6.1 Layout-Driven Circuit Optimization
- Yajun Ran, Malgorzata Marek-Sadowska:
The Magic of a Via-Configurable Regular Fabric. 338-343 - Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan:
A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network. 344-349 - Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz:
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. 350-353 - Dongku Kang, Hunsoo Choo, Kaushik Roy:
Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed. 354-357
Session 6.2 Instruction-Level Parallelism (1)
- Srikanth T. Srinivasan, Haitham Akkary, Tom Holman, Konrad Lai:
A Minimal Dual-Core Speculative Multi-Threading Architecture. 360-367 - Rama Sangireddy, Arun K. Somani:
Exploiting Quiescent States in Register Lifetime. 368-374 - Yau Chin, John Sheu, David M. Brooks:
Evaluating Techniques for Exploiting Instruction Slack. 375-378
Session 6.3 Power Estimation and Minimization
- Siddharth Garg, Siddharth Tata, Ravishankar Arunachalam:
Static Transition Probability Analysis Under Uncertainty. 380-386 - Donald Chai, Andreas Kuehlmann:
Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation. 387-392 - Mirko Loghi, Luca Benini, Massimo Poncino:
Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor. 393-396 - Zhaohui Huang, Peixin Zhong:
An Architectural Power Estimator for Analog-to-Digital Converters. 397-400
Session 7
Session 7.1 Formal Verification Techniques
- Nikhil Kikkeri, Peter-Michael Seidel:
Formal Hardware Verification based on Signal Correlation Properties. 402-408 - Kelvin Ng, Alan J. Hu, Jin Yang:
Generating Monitor Circuits for Simulation-Friendly GSTE Assertion Graphs. 409-416 - Chen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, Jing-Yang Jou:
Graph Automorphism-Based Algorithm for Determining Symmetric Inputs. 417-419
Session 7.2 Networks on Chips
- Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod:
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures. 422-429 - Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin:
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. 430-437 - Chan-Eun Rhee, Han-You Jeong, Soonhoi Ha:
Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures. 438-443
Session 7.3 Novel Processor Architecture
- Liang Han, Jie Chen, Chaoxian Zhou, Ying Li, Xin Zhang, Zhibi Liu, Xiaoyun Wei, Baofeng Li:
An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing. 446-451 - A. Murat Fiskiran, Ruby B. Lee:
Runtime Execution Monitoring (REM) to Detect and Prevent Malicious Code Execution. 452-457 - Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra:
Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study. 458-463
Session 8
Session 8.1 Instruction-Level Parallelism (2)
- Feng Shi, Sobeeh Almukhaizim, Pey-Chang Lin, Yiorgos Makris:
Compiler-Based Frame Formation for Static Optimization. 466-471 - Sriram Nadathur, Akhilesh Tyagi:
IPC Driven Dynamic Associative Cache Architecture for Low Energy. 472-479 - Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kanad Ghose:
Increasing Processor Performance Through Early Register Release. 480-487
Session 8.2 Topics in Synthesis and Co-Simulation
- Hu Huang, Joseph B. Bernstein, Martin Peckerar, Ji Luo:
Combined Channel Segmentation and Buffer Insertion for Routability and Performance Improvement of Field. 490-495 - Franco Fummi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino:
Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures. 496-501 - Jinwen Xi, Peixin Zhong:
Hardware/Software Co-Modeling of SAT Solver Based on Distributed Computing Elements using SystemC. 502-504 - Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou:
Coping with The Variability of Combinational Logic Delays. 505-508
Session 8.3 Low-Power Architecture
- Vassos Soteriou, Li-Shiuan Peh:
Design-Space Exploration of Power-Aware On/Off Interconnection Networks. 510-517 - Yao Guo, Saurabh Chheda, Israel Koren, C. Mani Krishna, Csaba Andras Moritz:
Energy Characterization of Hardware-Based Data Prefetching. 518-523 - Hee-Kwan Son, Sang-Geun Oh:
Design and Implementation of Scalable Low-Power Montgomery Multiplier. 524-531
Session 9
Session 9.1 Test Generation
- Scott Ollivierre, Adam B. Kinsman, Nicola Nicolici:
Compressed Embedded Diagnosis of Logic Cores. 534-539 - Pallav Gupta, Rui Zhang, Niraj K. Jha:
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks. 540-543 - Hung-Yau Lin, Hong-Zu Chou, Fu-Min Yeh, Ing-Yi Chen, Sy-Yen Kuo:
An Efficient Algorithm for Reconfiguring Shared Spare RRAM. 544-546
Session 9.2 Network Routing
- Hashem Hashemi Najaf-abadi, Hamid Sarbazi-Azad:
An Accurate Combinatorial Model for Performance Prediction of Deterministic Wormhole Routing in Torus Multicomputer Systems. 548-553 - Raymond W. Baldwin, Enrico Ng:
Technique to Eliminate Sorting in IP Packet Forwarding Devices. 554-559
Session 9.3 Placement and Floorplanning
- Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang:
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. 562-567 - Meng-Chen Wu, Yao-Wen Chang:
Placement with Alignment and Performance Constraints Using the B*-Tree Representation. 568-571 - Hai Zhou, Jia Wang:
ACG-Adjacent Constraint Graph for General Floorplans. 572-575
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-09 23:36 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
