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2020 – today
- 2025
[j86]Mehdi Baradaran Tahoori
, Seyedeh Maryam Ghasemi, Yervant Zorian:
Silicon Lifecycle Management (SLM): Requirements, Trends, and Opportunities. IEEE Des. Test 42(1): 28-38 (2025)- [j85]Sridhar Muthrasanallur, Yervant Zorian:
A Test, Debug, and Silicon Lifecycle Management Architecture for a UCIe-Based Open Chiplet Ecosystem. IEEE Micro 45(1): 67-74 (2025) - 2024
- [j84]Mehdi Baradaran Tahoori, Yervant Zorian:
Special Issue on Silicon Lifecycle Management. IEEE Des. Test 41(4): 5-6 (2024) - [j83]Mahta Mayahinia, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Karen Amirkhanyan, Artur Ghukasyan, Gurgen Harutyunyan, Yervant Zorian:
Testing for Electromigration in Sub-5-nm FinFET Memories. IEEE Des. Test 41(6): 54-61 (2024) - [j82]Irith Pomeranz, Yervant Zorian:
Functionally Possible Path Delay Faults With High Functional Switching Activity. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 2159-2163 (2024) - [c184]Karen Amirkhanyan, A. Babayan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
An Approach for Increasing Memory Repair Efficiency. EWDTS 2024: 1-6 - [c183]Karen Amirkhanyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian:
Repair of Resistive Open Defects on Word-Lines and Bit-Lines of SRAMs. EWDTS 2024: 1-6 - [c182]Fabian Vargas, Vache Galstyan, Gurgen Harutyunyan, Yervant Zorian:
On-Chip Sensor to Monitor Aging Evolution in FinFET-Based Memories. IOLTS 2024: 1-6 - [c181]Zhe Zhang, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian:
Testing for aging in advanced SRAM: From front end of the line transistors to back end of the line interconnects. ITC 2024: 46-50 - [c180]Zhe Zhang, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian:
Addressing the Combined Effect of Transistor and Interconnect Aging in SRAM towards Silicon Lifecycle Management. VTS 2024: 1-5 - 2023
- [c179]Mahta Mayahinia, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian:
On-chip Electromigration Sensor for Silicon Lifecycle Management of Nanoscale VLSI. ETS 2023: 1-4 - [c178]Costas Argyrides, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian:
Utilizing ECC Analytics to Improve Memory Lifecycle Management. ITC 2023: 383-387 - [c177]Kranthi Kandula, Ramalingam Kolisetti, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian:
SLM Subsystem for Automotive SoC: Case Study on Path Margin Monitor. ITC 2023: 388-392 - [c176]Yervant Zorian:
Silicon Lifecycle Management: Trends, Challenges and Solutions : Tutorial 2. ITC-Asia 2023: 1 - [c175]Artur Ghukasyan, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian:
Overcoming Embedded Memory Test & Repair Challenges in the Gate-All-Around Era. VTS 2023: 1-4 - [c174]Fei Su, Xiankun Robert Jin, Nilanjan Mukherjee, Yervant Zorian:
Innovation Practices Track: Silicon Lifecycle Management Challenges and Opportunities. VTS 2023: 1 - 2022
- [c173]Costas Argyrides, Vilas Sridharan, Hayk Danoyan, Gurgen Harutyunyan, Yervant Zorian:
A Novel Protection Technique for Embedded Memories with Optimized PPA. ITC 2022: 642-645 - [c172]Minqiang Peng, Youfa Wu, Jialiang Li, Alex Yu, Grigor Tshagharyan, Costas Argyrides, Vilas Sridharan, Gurgen Harutyunyan, Yervant Zorian, Nilanjan Mukherjee:
Innovative Practices Track: What's Next for Automotive: Where and How to Improve Field Test and Enhance SoC Safety. VTS 2022: 1 - 2021
- [c171]Yu Huang, David Francis, Yervant Zorian, Nilanjan Mukherjee:
Automotive Test and Reliability. ITC-Asia 2021: 1 - 2020
- [j81]Gurgen Harutyunyan, Suren Martirosyan, Samvel K. Shoukourian, Yervant Zorian:
Memory Physical Aware Multi-Level Fault Diagnosis Flow. IEEE Trans. Emerg. Top. Comput. 8(3): 700-711 (2020) - [c170]M. Casarsa, Gurgen Harutyunyan, Yervant Zorian:
Test and Diagnosis Solution for Functional Safety. ITC 2020: 1-5
2010 – 2019
- 2019
- [j80]Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian:
Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(3): 562-575 (2019) - [c169]Gabriele Boschi, Donato Luongo, Duccio Lazzarotti, Hanna Shaheen, Hayk T. Grigoryan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian:
Memory FIT Rate Mitigation Technique for Automotive SoCs. ITC 2019: 1-6 - [c168]Kuen-Jong Lee, Shi-Yu Huang, Huawei Li, Tomoo Inoue, Yervant Zorian:
International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia. ITC 2019: 1-4 - [c167]Yervant Zorian, Vladimir Hahanov, Svetlana Chumachenko, Eugenia Litvinova:
17th IEEE East-West Design and Test Symposium. ITC 2019: 1-4 - [c166]Yervant Zorian:
Trends & Challenges in Today's Automotive SOCs. MECO 2019: 1 - [c165]S. Bandyopadhyay, J. Mekkoth, Marc Hutner, Hayk T. Grigoryan, Arun Kumar, Samvel K. Shoukourian, Grigor Tshagharyan, Yervant Zorian, Gabriele Boschi, Duccio Lazzarotti, Donato Luongo, Hanna Shaheen, Gurgen Harutyunyan:
Innovative Practices on In-System Test and Reliability of Memories. VTS 2019: 1 - 2018
- [j79]Hans-Joachim Wunderlich, Yervant Zorian:
Guest Editor's Introduction. IEEE Des. Test 35(3): 5-6 (2018) - [j78]Yervant Zorian:
The 10th China Test Conference. IEEE Des. Test 35(6): 96-97 (2018) - [c164]Hayk T. Grigoryan, Samvel K. Shoukourian, Gurgen Harutyunyan, Yervant Zorian, Costas Argyrides:
Advanced ECC-Based FIT Rate Mitigation Technique for Automotive SoCs. ITC 2018: 1-6 - [c163]Tal Kogan, Yehonatan Abotbol, Gabriele Boschi, Gurgen Harutyunyan, N. Martirosyan, Yervant Zorian:
Advanced Uniformed Test Approach For Automotive SoCs. ITC 2018: 1-10 - [c162]Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Hayk T. Grigoryan, Gurgen Harutyunyan, Yervant Zorian:
Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM. ITC 2018: 1-10 - [c161]Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian, Anteneh Gebregiorgis, Mohammad Saber Golanbari, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications. ITC 2018: 1-10 - [c160]Art Schaldenbrand, Yervant Zorian, Stephen Sunter, Peter Sarson:
IP session on ISO26262 EDA. VTS 2018: 1 - 2017
- [j77]Erik Jan Marinissen, Yervant Zorian:
Guest Editors' Introduction: Design & Test of a High-Volume 3-D Stacked Graphics Processor With High-Bandwidth Memory. IEEE Des. Test 34(1): 6-7 (2017) - [c159]Suren Martirosyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian:
An efficient testing methodology for embedded flash memories. EWDTS 2017: 1-4 - [c158]D. Sargsyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian:
Automated flow for test pattern creation for IPs in SoC. EWDTS 2017: 1-4 - [c157]Grigor Tshagharyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian:
Experimental study on Hamming and Hsiao codes in the context of embedded applications. EWDTS 2017: 1-4 - [c156]Christophe Eychenne, Yervant Zorian:
An effective functional safety infrastructure for system-on-chips. IOLTS 2017: 63-66 - [c155]Hanna Shaheen, Gabriele Boschi, Gurgen Harutyunyan, Yervant Zorian:
Advanced ECC solution for automotive SoCs. IOLTS 2017: 71-73 - [c154]Tal Kogan, Yehonatan Abotbol, Gabriele Boschi, Gurgen Harutyunyan, I. Kroul, Hanna Shaheen, Yervant Zorian:
Advanced functional safety mechanisms for embedded memories and IPs in automotive SoCs. ITC 2017: 1-6 - [c153]Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian:
An effective functional safety solution for automotive systems-on-chip. ITC 2017: 1-10 - [c152]Yervant Zorian:
Tutorial I: Topic: Automotive test strategies. ITC-Asia 2017: ix-xi - [c151]Yervant Zorian:
Keynotes: Robustness challenges in the internet of things. VLSI-SoC 2017: 1-5 - 2016
- [c150]Erik Jan Marinissen, Yervant Zorian, Mario Konijnenburg, Chih-Tsun Huang, Ping-Hsuan Hsieh, Peter Cockburn, Jeroen Delvaux, Vladimir Rozic, Bohan Yang, Dave Singelée, Ingrid Verbauwhede, Cedric Mayor, Robert Van Rijsinge, Cocoy Reyes:
IoT: Source of test challenges. ETS 2016: 1-10 - [c149]Grigor Tshagharyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian:
Securing test infrastructure of system-on-chips. EWDTS 2016: 1-4 - [c148]Mohamed Abid, Yervant Zorian:
Welcome to the IDT 2016. IDT 2016: x - 2015
- [c147]L. Martirosyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian:
A power based memory BIST grouping methodology. EWDTS 2015: 1-4 - [c146]Vrezh Sargsyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Avetik Yessayan:
An efficient approach for memory repair by reducing the number of spares. EWDTS 2015: 1-4 - [c145]Grigor Tshagharyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian:
Overview study on fault modeling and test methodology development for FinFET-based memories. EWDTS 2015: 1-4 - [c144]Yervant Zorian:
Keynote 3: "Ensuring robustness in today's IoT era". IDT 2015: 1 - [c143]Jacob A. Abraham, Ravishankar K. Iyer, Dimitris Gizopoulos, Dan Alexandrescu, Yervant Zorian:
The future of fault tolerant computing. IOLTS 2015: 108-109 - [c142]Gurgen Harutunyan, Yervant Zorian:
An effective embedded test & diagnosis solution for external memories. IOLTS 2015: 168-170 - [c141]Víctor H. Champac, Yervant Zorian, Letícia Maria Bolzani Pöhls, Vishwani D. Agrawal:
Message from the LATS2015 Chairs. LATS 2015: 1 - [c140]Gurgen Harutyunyan, Grigor Tshagharyan, Yervant Zorian:
Impact of parameter variations on FinFET faults. VTS 2015: 1-4 - [e3]Nelson Baloian, Yervant Zorian, Perouz Taslakian, Samvel K. Shoukourian:
Collaboration and Technology - 21st International Conference, CRIWG 2015, Yerevan, Armenia, September 22-25, 2015, Proceedings. Lecture Notes in Computer Science 9334, Springer 2015, ISBN 978-3-319-22746-7 [contents] - 2014
- [j76]Yervant Zorian, Soha Hassoun:
Guest Editors' Introduction: Highlights of the 50th DAC. IEEE Des. Test 31(2): 6-8 (2014) - [c139]Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
Extending fault periodicity table for testing faults in memories under 20nm. EWDTS 2014: 1-4 - [c138]Yervant Zorian:
Design, test & repair methodology for FinFET-based memories. ITC 2014: 1 - [c137]Gurgen Harutyunyan, Grigor Tshagharyan, Valery A. Vardanian, Yervant Zorian:
Fault modeling and test algorithm creation strategy for FinFET-based memories. VTS 2014: 1-6 - [c136]Alodeep Sanyal, Yanjing Li, Yervant Zorian:
Special session 12C: Young professionals in test - Town meeting. VTS 2014: 1 - 2013
- [c135]K. Amirkhanyan, A. Davtyan, Gurgen Harutyunyan, T. Melkumyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
Application of defect injection flow for fault validation in memories. EWDTS 2013: 1-4 - [c134]Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
Impact of process variations on read failures in SRAMs. EWDTS 2013: 1-4 - [c133]T. Melkumyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
An efficient fault diagnosis and localization algorithm for Successive-Approximation Analog to Digital Converters. EWDTS 2013: 1-4 - [c132]W. Prates, Letícia Maria Veiras Bolzani, Gurgen Harutyunyan, A. Davtyan, Fabian Vargas, Yervant Zorian:
Integrating embedded test infrastructure in SRAM cores to detect aging. IOLTS 2013: 25-30 - [c131]Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
An effective solution for building memory BIST infrastructure based on fault periodicity. VTS 2013: 1-6 - [c130]Alodeep Sanyal, Yervant Zorian:
Special session 12C: Town-hall meeting "young professionals in test". VTS 2013: 1 - 2012
- [j75]P. Glenn Gulak, Rajesh Gupta, Gianluca Setti, Yervant Zorian:
Message From the Steering Committee. IEEE Des. Test Comput. 29(1): 5 (2012) - [j74]Erik Jan Marinissen, Yervant Zorian:
Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits. J. Electron. Test. 28(1): 13-14 (2012) - [j73]Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(6): 941-949 (2012) - [c129]Yervant Zorian:
Addressing Test Challenges in Advanced Technology Nodes. Asian Test Symposium 2012: 6 - [c128]Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky:
Design for test and reliability in ultimate CMOS. DATE 2012: 677-682 - 2011
- [j72]Gurgen Harutunyan, Aram Hakhumyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
Symmetry Measure for Memory Test and Its Application in BIST Optimization. J. Electron. Test. 27(6): 753-766 (2011) - [j71]Víctor H. Champac, Fernanda Gusmão de Lima Kastensmidt, Letícia Maria Veiras Bolzani Poehls, Fabian Vargas, Yervant Zorian:
12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011. J. Low Power Electron. 7(4): 529-530 (2011) - [c127]K. Darbinyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
A Robust Solution for Embedded Memory Test and Repair. Asian Test Symposium 2011: 461-462 - [c126]Hayk T. Grigoryan, Gurgen Harutunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
Generic BIST architecture for testing of content addressable memories. IOLTS 2011: 86-91 - [e2]Vladimir Hahanov, Yervant Zorian:
9th East-West Design & Test Symposium, EWDTS 2011, Sevastopol, Ukraine, September 9-12, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1957-8 [contents] - 2010
- [c125]H. Avetisyan, Gurgen Harutyunyan, Valery A. Vardanian, Yervant Zorian:
An efficient March test for detection of all two-operation dynamic faults from subclass Sav. EWDTS 2010: 310-313 - [c124]Yervant Zorian:
Test and reliability concerns for 3D-ICs. IOLTS 2010: 219 - [e1]Yervant Zorian, Imtinan Elahi, André Ivanov, Ashraf Salem:
5th International Design and Test Workshop, IDT 2010, Abu Dhabi, UAE, 14-15 December 2010. IEEE 2010, ISBN 978-1-61284-291-2 [contents]
2000 – 2009
- 2009
- [j70]Erik Jan Marinissen, Yervant Zorian:
Guest Editors' Introduction: The Status of IEEE Std 1500. IEEE Des. Test Comput. 26(1): 6-7 (2009) - [j69]Erik Jan Marinissen, Yervant Zorian:
IEEE Std 1500 Enables Modular SoC Testing. IEEE Des. Test Comput. 26(1): 8-17 (2009) - [j68]Yervant Zorian:
Guest Editor's Introduction: Examples of Management Decision Criteria. IEEE Des. Test Comput. 26(2): 6-7 (2009) - [j67]Erik Jan Marinissen, Yervant Zorian:
Guest Editors' Introduction: The Status of IEEE Std 1500 - Part 2. IEEE Des. Test Comput. 26(3): 4 (2009) - [c123]Mark Redford, Joseph Sawicki, Prasad Subramaniam, Cliff Hou, Yervant Zorian, Kimon Michaels:
DFM: don't care or competitive weapon? DAC 2009: 296-297 - [c122]Yervant Zorian:
Panel Session - Vertical integration versus disaggregation. DATE 2009: 602 - [c121]Erik Jan Marinissen, Yervant Zorian:
Testing 3D chips containing through-silicon vias. ITC 2009: 1-11 - 2008
- [j66]Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian:
IEEE Standard 1500 Compliance Verification for Embedded Cores. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 397-407 (2008) - [c120]Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian:
An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories. VTS 2008: 95-100 - 2007
- [j65]Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian:
Minimal March Tests for Detection of Dynamic Faults in Random Access Memories. J. Electron. Test. 23(1): 55-74 (2007) - [c119]Yasuharu Kohiyama, C. P. Ravikumar, Yasuo Sato, Laung-Terng Wang, Yervant Zorian:
Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides. ATS 2007: 207 - [c118]Srikanth Venkataraman, Ruchir Puri, Steve Griffith, Ankush Oberai, Robert Madge, Greg Yeric, Walter Ng, Yervant Zorian:
Making Manufacturing Work For You. DAC 2007: 107-108 - [c117]Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian:
A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories. DDECS 2007: 145-148 - 2006
- [j64]Bruce C. Kim, Yervant Zorian:
Guest Editors' Introduction: Big Innovations in Small Packages. IEEE Des. Test Comput. 23(3): 186-187 (2006) - [c116]Ron Wilson, Yervant Zorian:
Decision-making for complex SoCs in consumer electronic products. DAC 2006: 173 - [c115]Nic Mokhoff, Yervant Zorian:
Tradeoffs and choices for emerging SoCs in high-end applications. DAC 2006: 273 - [c114]Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian:
Minimal March-Based Fault Location Algorithm with Partial Diagnosis for all Static Faults in Random Access Memories. DDECS 2006: 262-267 - [c113]Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian:
Minimal March Tests for Dynamic Faults in Random Access Memories. ETS 2006: 43-48 - [c112]Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian:
Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories. VTS 2006: 120-127 - [c111]Yervant Zorian, Dennis Wassung:
Session Abstract. VTS 2006: 154-155 - [c110]Yervant Zorian, Bruce C. Kim:
Session Abstract. VTS 2006: 334-335 - 2005
- [j63]Yervant Zorian:
Nanoscale Design & Test Challenges. Computer 38(2): 36-39 (2005) - [j62]Juan Antonio Carballo, Yervant Zorian, Raul Camposano, Andrzej J. Strojwas, John Kibarian, Dennis Wassung, Alex Alexanian, Steve Wigley, Neil Kelly:
Guest Editors' Introduction: DFM Drives Changes in Design Flow. IEEE Des. Test Comput. 22(3): 200-205 (2005) - [c109]Yervant Zorian, Juan Antonio Carballo:
T1: Design for Manufacturability. Asian Test Symposium 2005 - [c108]Dennis Wassung, Yervant Zorian, Magdy S. Abadir, Mark Bapst, Colin Harris:
Choosing flows and methodologies for SoC design. DAC 2005: 167 - [c107]Nic Mokhoff, Yervant Zorian, Kamalesh N. Ruparel, Hao Nham, Francesco Pessolano, Kee Sup Kim:
How to determine the necessity for emerging solutions. DAC 2005: 274-275 - [c106]Yervant Zorian, Bill Frerichs, Dennis Wassung, Jim Ensel, Guri Stark, Mike Gianfagna, Kamalesh N. Ruparel:
Semiconductor Industry Disaggregation vs Reaggregation: Who Will be the Shark? DATE 2005: 572 - [c105]Erik Jan Marinissen, Betty Prince, Doris Keitel-Schulz, Yervant Zorian:
Challenges in Embedded Memory Design and Test. DATE 2005: 722-727 - [c104]Yervant Zorian, Valery A. Vardanian, K. Aleksanyan, K. Amirkhanyan:
Impact of Soft Error Challenge on SoC Design. IOLTS 2005: 63-68 - [c103]Régis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert:
On-Line Testing for Secure Implementations: Design and Validation. IOLTS 2005: 211 - [c102]Yervant Zorian:
Today's SOC test challenges. ITC 2005: 2 - [c101]Yervant Zorian, Avetik Yessayan:
IEEE 1500 utilization in SOC design and test. ITC 2005: 10 - [c100]Yervant Zorian:
Optimizing SoC Manufacturability. VLSI Design 2005: 37-38 - [c99]Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian:
Minimal March Tests for Unlinked Static Faults in Random Access Memories. VTS 2005: 53-59 - [c98]Baosheng Wang, Yuejian Wu, Josh Yang, André Ivanov, Yervant Zorian:
SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms. VTS 2005: 66-71 - 2004
- [j61]Don Edenfeld, Andrew B. Kahng, Mike Rodgers, Yervant Zorian:
2003 Technology Roadmap for Semiconductors. Computer 37(1): 47-56 (2004) - [j60]Yervant Zorian, Dimitris Gizopoulos, Cary Vandenberg, Philippe Magarshack:
Guest Editors' Introduction: Design for Yield and Reliability. IEEE Des. Test Comput. 21(3): 177-182 (2004) - [j59]Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure. IEEE Des. Test Comput. 21(3): 200-207 (2004) - [j58]Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian:
Design & Test Education in Asia. IEEE Des. Test Comput. 21(4): 331-338 (2004) - [j57]Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian:
Distributed Diagnosis of Interconnections in SoC and MCM Designs. J. Electron. Test. 20(3): 291-307 (2004) - [j56]Irith Pomeranz, Yervant Zorian:
Fault isolation for nonisolated blocks. IEEE Trans. Very Large Scale Integr. Syst. 12(12): 1385-1388 (2004) - [c97]Yervant Zorian:
Investment vs. Yield Relationship for Memories in SOC. ITC 2004: 1444 - [c96]N. Derhacobian, Valery A. Vardanian, Yervant Zorian:
Embedded Memory Reliability: The SER Challenge. MTDT 2004: 104-110 - [c95]Baosheng Wang, Josh Yang, James Cicalo, André Ivanov, Yervant Zorian:
Reducing Embedded SRAM Test Time under Redundancy Constraints. VTS 2004: 237-242 - [c94]Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
A Methodology for Design and Evaluation of Redundancy Allocation Algorithms. VTS 2004: 249-260 - 2003
- [j55]Yervant Zorian:
Guest Editor's Introduction: Advances in Infrastructure IP. IEEE Des. Test Comput. 20(3): 49- (2003) - [j54]Yervant Zorian, Samvel K. Shoukourian:
Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield. IEEE Des. Test Comput. 20(3): 58-66 (2003) - [j53]Yervant Zorian:
IEEE CASS becomes D&T Copublisher. IEEE Des. Test Comput. 20(3): 108- (2003) - [j52]Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian:
A Hierarchical Infrastructure for SoC Test Management. IEEE Des. Test Comput. 20(4): 32-39 (2003) - [j51]Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian:
Instruction-Based Self-Testing of Processor Cores. J. Electron. Test. 19(2): 103-112 (2003) - [j50]Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian:
Easily Testable Cellular Carry Lookahead Adders. J. Electron. Test. 19(3): 285-298 (2003) - [c93]Yervant Zorian:
Leveraging Infrastructure IP for SoC Yield. Asian Test Symposium 2003: 3-5 - [c92]Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
Low-Cost Software-Based Self-Testing of RISC Processor Cores. DATE 2003: 10714-10719 - [c91]Nektarios Kranitis, George Xenoulis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian:
Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores. ITC 2003: 431-440 - [c90]Francisco DaSilva, Yervant Zorian, Lee Whetsel, Karim Arabi, Rohit Kapur:
Overview of the IEEE P1500 Standard. ITC 2003: 988-997 - [c89]Yervant Zorian:
Yield Threats and Inadequacy of One-time Test. ITC 2003: 1284 - [c88]Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian:
A Test Interface for Built-In Test of Non-Isolated Scanned Cores. VTS 2003: 371-378 - 2002
- [j49]Alan Allan, Don Edenfeld, William H. Joyner Jr., Andrew B. Kahng, Mike Rodgers, Yervant Zorian:
2001 Technology Roadmap for Semiconductors. Computer 35(1): 42-53 (2002) - [j48]Erik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian:
On IEEE P1500's Standard for Embedded Core Test. J. Electron. Test. 18(4-5): 365-383 (2002) - [c87]Yervant Zorian:
Embedding infrastructure IP for SOC yield improvement. DAC 2002: 709-712 - [c86]Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian:
Effective Software Self-Test Methodology for Processor Cores. DATE 2002: 592-597 - [c85]Irith Pomeranz, Yervant Zorian:
Fault Isolation Using Tests for Non-Isolated Blocks. DATE 2002: 1123 - [c84]Michel Renovell, Penelope Faure, Paolo Prinetto, Yervant Zorian:
Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA. DELTA 2002: 297-301 - [c83]Valery A. Vardanian, Yervant Zorian:
A March-Based Fault Location Algorithm for Static Random Access Memories. IOLTW 2002: 256-261 - [c82]Yervant Zorian:
Embedded Memory Test and Repair: Infrastructure IP for SOC Yield. ITC 2002: 340-349 - [c81]Valery A. Vardanian, Yervant Zorian:
A March-Based Fault Location Algorithm for Static Random Access Memories. MTDT 2002: 62-67 - [c80]Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian:
Instruction-Based Self-Testing of Processor Cores. VTS 2002: 223-228 - 2001
- [j47]Yervant Zorian:
Huge Storage Capacity. IEEE Des. Test Comput. 18(3): 1- (2001) - [j46]Yervant Zorian:
Error-Free Products. IEEE Des. Test Comput. 18(4): 2- (2001) - [j45]Yervant Zorian:
EIC Message. IEEE Des. Test Comput. 18(5): 1- (2001) - [j44]Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis, Yervant Zorian:
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. J. Electron. Test. 17(2): 97-107 (2001) - [j43]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. J. Electron. Test. 17(3-4): 283-290 (2001) - [j42]Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian:
Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures. IEEE Trans. Computers 50(10): 1007-1019 (2001) - [j41]Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian:
Switching activity generation with automated BIST synthesis forperformance testing of interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9): 1143-1158 (2001) - [c79]Yervant Zorian, Paolo Prinetto, João Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, Octávio Páscoa Dias, Jorge Semião, Peter Muhmenthaler, W. Radermacher:
Embedded tutorial: TRP: integrating embedded test and ATE. DATE 2001: 34-37 - [c78]Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Yervant Zorian:
Deterministic software-based self-testing of embedded processor cores. DATE 2001: 92-96 - [c77]Yervant Zorian:
System-on-Chip: Embedded Test Strategies. ISQED 2001: 7 - [c76]Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. ISQED 2001: 343-349 - [c75]Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC 2001: 924-931 - [c74]Erik Jan Marinissen, Yervant Zorian:
Testing Embedded Core-Based System Chips. LATW 2001: 2 - [c73]Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
An Approach for Evaluation of Redunancy Analysis Algorithms. MTDT 2001: 51- - [c72]Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian:
Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. VTS 2001: 15-21 - 2000
- [j40]Yervant Zorian:
Flexibility and Programmability. IEEE Des. Test Comput. 17(1): 3- (2000) - [j39]Yervant Zorian:
Embedded in this issue. IEEE Des. Test Comput. 17(2): 5-6 (2000) - [j38]Yervant Zorian:
Wider Coverage. IEEE Des. Test Comput. 17(3): 6- (2000) - [j37]Nektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Mihalis Psarakis, Yervant Zorian:
Power-/Energy Efficient BIST Schemes for Processor Data Paths. IEEE Des. Test Comput. 17(4): 15-28 (2000) - [j36]Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian:
A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures. J. Electron. Test. 16(3): 179-184 (2000) - [j35]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. J. Electron. Test. 16(3): 289-299 (2000) - [j34]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Testing the Local Interconnect Resources of SRAM-Based FPGA's. J. Electron. Test. 16(5): 513-520 (2000) - [j33]Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays. IEEE Trans. Computers 49(10): 1083-1099 (2000) - [c71]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Asian Test Symposium 2000: 323-328 - [c70]Tsin-Yuan Chang, Yervant Zorian:
SoC Testing and P1500 Standard. Asian Test Symposium 2000: 492 - [c69]Yervant Zorian, Erik Jan Marinissen:
System chip test: how will it impact your design? DAC 2000: 136-141 - [c68]Yervant Zorian, Michael Nicolaidis, Peter Muhmenthaler, David Y. Lepejian, Chris W. H. Strolenberg, Kees Veelenturf:
Tutorial Statement. DATE 2000: 66 - [c67]Yervant Zorian:
Yield Improvement and Repair Trade-Off for Large Embedded Memories. DATE 2000: 69-70 - [c66]Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian:
Effective Low Power BIST for Datapaths. DATE 2000: 757 - [c65]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
Analyzing the test generation problem for an application-oriented test of FPGAs. ETW 2000: 75-80 - [c64]Yervant Zorian, Sujit Dey, Mike Rodgers:
Test of Future System-on-Chips. ICCAD 2000: 392-398 - [c63]Yervant Zorian:
Embedded-Quality for Test. ISQED 2000: 211-212 - [c62]Yervant Zorian, Erik Jan Marinissen, Rohit Kapur:
On using IEEE P1500 SECT for test plug-n-play. ITC 2000: 770-777 - [c61]Michel Renovell, Yervant Zorian:
Different experiments in test generation for XILINX FPGAs. ITC 2000: 854-862 - [c60]Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Fabio Ricciato, Maurizio Spadari, Yervant Zorian:
HD2BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs. ITC 2000: 892-901 - [c59]Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel:
Wrapper design for embedded core test. ITC 2000: 911-920 - [c58]Mihalis Psarakis, Nektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
Deterministic Built-In Self -Test for Shifters, Adders and ALUs in Datapaths. LATW 2000: 98-103 - [c57]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Test Configuration Generation for FPGA Logic Cells. LATW 2000: 202-208 - [c56]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits. SBCCI 2000: 3-8 - [c55]Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian:
Low Power/Energy BIST Scheme for Datapaths. VTS 2000: 23-28
1990 – 1999
- 1999
- [j32]Erik Jan Marinissen, Yervant Zorian:
Challenges in testing core-based system ICs. IEEE Commun. Mag. 37(6): 104-109 (1999) - [j31]Yervant Zorian, Erik Jan Marinissen, Sujit Dey:
Testing Embedded-Core-Based System Chips. Computer 32(6): 52-60 (1999) - [j30]Yervant Zorian:
Focus on DRAMs. IEEE Des. Test Comput. 16(1): 1- (1999) - [j29]Yervant Zorian:
D&T Expands. IEEE Des. Test Comput. 16(3): 6-7 (1999) - [j28]Yervant Zorian:
Integration Continues. IEEE Des. Test Comput. 16(4): 1- (1999) - [j27]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-Based FPGAs: Testing the Embedded RAM Modules. J. Electron. Test. 14(1-2): 159-167 (1999) - [j26]Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
An Effective Built-In Self-Test Scheme for Parallel Multipliers. IEEE Trans. Computers 48(9): 936-950 (1999) - [c54]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Minimizing the Number of Test Configurations for Different FPGA Families. Asian Test Symposium 1999: 363-368 - [c53]Antonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian:
An Effective BIST Architecture for Fast Multiplier Cores. DATE 1999: 117-121 - [c52]Michael Nicolaidis, Yervant Zorian:
Scaling Deeper to Submicron: On-Line Testing to the Rescue. DATE 1999: 432- - [c51]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. DATE 1999: 618-622 - [c50]Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian:
A high-level EDA environment for the automatic insertion of HD-BIST structures. ETW 1999: 2-6 - [c49]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study. ETW 1999: 146-151 - [c48]Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel:
Towards a standard for embedded core test: an example. ITC 1999: 616-627 - [c47]Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian:
HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs. ITC 1999: 1038-1044 - [c46]Irith Pomeranz, Yervant Zorian:
Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic. VTS 1999: 41-48 - [c45]Mihalis Psarakis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian:
An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers. VTS 1999: 252-259 - 1998
- [j25]Yervant Zorian:
D&T: 15th Year in Service. IEEE Des. Test Comput. 15(1): 1- (1998) - [j24]Dilip K. Bhavsar, Yervant Zorian:
ITC 97 Panel Sessions. IEEE Des. Test Comput. 15(1): 7, 91 (1998) - [j23]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Testing the Interconnect of RAM-Based FPGAs. IEEE Des. Test Comput. 15(1): 45-50 (1998) - [j22]Meh-Ron Amerian, William D. Atwell Jr., Ian Burgess, Gary D. Fleeman, David Y. Lepejian, T. W. Williams, Farzad Zarrinfar, Yervant Zorian:
A D&T Roundtable: Testing Mixed Logic and DRAM Chips. IEEE Des. Test Comput. 15(2): 86-92 (1998) - [j21]Yervant Zorian:
Once Again, a Super Issue. IEEE Des. Test Comput. 15(3): 3- (1998) - [j20]Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
Effective Built-In Self-Test for Booth Multipliers. IEEE Des. Test Comput. 15(3): 105-111 (1998) - [j19]Yervant Zorian:
Challenges and Options. IEEE Des. Test Comput. 15(4): 3- (1998) - [j18]Michael Nicolaidis, Yervant Zorian:
On-Line Testing for VLSI - A Compendium of Approaches. J. Electron. Test. 12(1-2): 7-20 (1998) - [j17]Ricardo de Oliveira Duarte, Michael Nicolaidis, Hakim Bederr, Yervant Zorian:
Efficient Totally Self-Checking Shifter Design. J. Electron. Test. 12(1-2): 29-39 (1998) - [c44]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. Asian Test Symposium 1998: 266-271 - [c43]Yervant Zorian:
System-Chip Test Strategies (Tutorial). DAC 1998: 752-757 - [c42]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
RAM-Based FPGA's: A Test Approach for the Configurable Logic. DATE 1998: 82-88 - [c41]Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi:
Novel Technique for Testing FPGAs. DATE 1998: 89-94 - [c40]T. Bogue, Michael Gössel, Helmut Jürgensen, Yervant Zorian:
Built-In Self-Test with an Alternating Output. DATE 1998: 180-184 - [c39]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. FPL 1998: 139-148 - [c38]Sujit Dey, Jacob A. Abraham, Yervant Zorian:
High-level design validation and test. ICCAD 1998: 3 - [c37]Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian:
Synthesis of BIST hardware for performance testing of MCM interconnections. ICCAD 1998: 69-73 - [c36]Yervant Zorian, Erik Jan Marinissen, Sujit Dey:
Testing embedded-core based system chips. ITC 1998: 130-143 - [c35]Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian:
A distributed BIST technique for diagnosis of MCM interconnections. ITC 1998: 214-221 - [c34]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-based FPGA's: testing the LUT/RAM modules. ITC 1998: 1102-1111 - [c33]Ilyoung Kim, Yervant Zorian, Goh Komoriya, Hai Pham, Frank P. Higgins, Jim L. Lewandowski:
Built in self repair for embedded high density SRAM. ITC 1998: 1112-1119 - [c32]Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model. VTS 1998: 152-157 - 1997
- [j16]Yervant Zorian, Rajesh K. Gupta:
Design and Test of Core-Based Systems on Chips. IEEE Des. Test Comput. 14(4): 14- (1997) - [j15]Rajesh K. Gupta, Yervant Zorian:
Introducing Core-Based System Design. IEEE Des. Test Comput. 14(4): 15-25 (1997) - [j14]Yervant Zorian:
Guest Editorial. J. Electron. Test. 10(1-2): 6 (1997) - [j13]Yervant Zorian:
Fundamentals of MCM Testing and Design-for-Testability. J. Electron. Test. 10(1-2): 7-14 (1997) - [j12]Yervant Zorian, Hakim Bederr:
An Effective Multi-Chip BIST Scheme. J. Electron. Test. 10(1-2): 87-95 (1997) - [c31]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. Asian Test Symposium 1997: 254- - [c30]Christian Dufaza, Yervant Zorian:
On the generation of pseudo-deterministic two-patterns test sequence with LFSRs. ED&TC 1997: 69-76 - [c29]Ricardo de Oliveira Duarte, Michael Nicolaidis, Hakim Bederr, Yervant Zorian:
Fault-secure shifter design: results and implementations. ED&TC 1997: 335-341 - [c28]Yervant Zorian:
Test Requirements for Embedded Core-Based Systems and IEEE P1500. ITC 1997: 191-199 - [c27]Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian, Mihalis Psarakis:
An Effective BIST Scheme for Arithmetic Logic Units. ITC 1997: 868-877 - [c26]J. Borel, M. Cecchini, C. Malipeddi, Janusz Rajski, Yervant Zorian:
Systems On Silicon: Design and Test Challenges. VTS 1997: 184-185 - [c25]Michel Renovell, Joan Figueras, Yervant Zorian:
Test of RAM-based FPGA: methodology and application to the interconnect. VTS 1997: 230-237 - [c24]Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian:
Power Dissipation During Testing: Should We Worry About it? VTS 1997: 456-457 - 1996
- [j11]Yervant Zorian, Jan Hlavicka:
Guest Editors' Introduction: East Meets West. IEEE Des. Test Comput. 13(1): 5-7 (1996) - [j10]Kenneth D. Wagner, Yervant Zorian:
EIC Message. IEEE Des. Test Comput. 13(2): 2- (1996) - [j9]Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov:
Panel Summaries. IEEE Des. Test Comput. 13(3): 6, 110-112 (1996) - [j8]Gil Philips, Yervant Zorian, Charles W. Rosenthal, Bozena Kaminska:
Conference Reports. IEEE Des. Test Comput. 13(3): 8, 113-144 (1996) - [j7]André Ivanov, Barry K. Tsuji, Yervant Zorian:
Programmable BIST Space Compactors. IEEE Trans. Computers 45(12): 1393-1404 (1996) - [c23]Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian:
Relay Propagation Scheme for Testing of MCMs on Large Area Substrates. ED&TC 1996: 131-137 - [c22]Yervant Zorian, Hakim Bederr:
Designing Self-Testable Multi-Chip Modules. ED&TC 1996: 181-185 - [c21]Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
An Effective BIST Scheme for Datapaths. ITC 1996: 76-85 - [c20]Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian:
Optimal Multiple Chain Relay Testing Scheme for MCMs on Large Area Substrates. ITC 1996: 818-827 - 1995
- [j6]Sreejit Chakravarty, Ramalingam Sridhar, Shambhu J. Upadhyaya, Yervant Zorian, Gil Philips, Bozena Kaminska, Bernard Courtois:
Conference Reports. IEEE Des. Test Comput. 12(4): 95-97 (1995) - [j5]Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik:
Integration of partial scan and built-in self-test. J. Electron. Test. 7(1-2): 125-137 (1995) - [c19]Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
An effective BIST scheme for carry-save and carry-propagate array multipliers. Asian Test Symposium 1995: 298-302 - [c18]Ad J. van de Goor, Ivo Schanstra, Yervant Zorian:
Functional test for shifting-type FIFOs. ED&TC 1995: 133-138 - [c17]O. Kebichi, Yervant Zorian, Michael Nicolaidis:
Area versus detection latency trade-offs in self-checking memory design. ED&TC 1995: 358-362 - [c16]Yervant Zorian:
Multi-chip module technology. ICNN 1995: 152-157 - [c15]Fabian Vargas, Michael Nicolaidis, Yervant Zorian:
An Approach for Designing Total-Dose Tolerant MCMs Based on Current Monitoring. ITC 1995: 345-354 - [c14]Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
An Effective BIST Scheme for Booth Multipliers. ITC 1995: 824-833 - 1994
- [j4]Ad J. van de Goor, Yervant Zorian:
Effective march algorithms for testing single-order addressed memories. J. Electron. Test. 5(4): 337-345 (1994) - [c13]Ad J. van de Goor, Yervant Zorian, Ivo Schanstra:
Functional Tests for Ring-Address SRAM-type FIFOs. EDAC-ETC-EUROASIC 1994: 666 - [c12]Yervant Zorian, Ad J. van de Goor, Ivo Schanstra:
An Effective BIST Scheme for Ring-Address Type FIFOs. ITC 1994: 378-387 - [c11]Cecil A. Dean, Yervant Zorian:
Do You Practice Safe Tests? What We Found Out About Your Habits. ITC 1994: 887-892 - [c10]Ad J. van de Goor, Ivo Schanstra, Yervant Zorian:
Fault models and tests for Ring Address Type FIFOs. VTS 1994: 300-305 - 1993
- [c9]Yervant Zorian, André Ivanov:
Programmable Space Compaction for BIST. FTCS 1993: 340-349 - [c8]Harold N. Scholz, Duane R. Aadsen, Yervant Zorian:
A Method for Delay Fault Self-Testing of Macrocells. ITC 1993: 253-261 - [c7]Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik:
PSBIST: A Partial-Scan Based Built-In Self-Test Scheme. ITC 1993: 507-516 - [c6]Yervant Zorian:
A distributed BIST control scheme for complex VLSI devices. VTS 1993: 4-9 - 1992
- [j3]Yervant Zorian, André Ivanov:
An Effective BIST Scheme for ROM's. IEEE Trans. Computers 41(5): 646-653 (1992) - [j2]André Ivanov, Yervant Zorian:
Count-based BIST compaction schemes and aliasing probability computation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(6): 768-777 (1992) - [c5]Yervant Zorian:
A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary-Scan. ICCD 1992: 59-66 - 1990
- [j1]Yervant Zorian, Vinod K. Agarwal:
Optimizing error masking in BIST by output data modification. J. Electron. Test. 1(1): 59-71 (1990) - [c4]André Ivanov, Yervant Zorian:
Computing the Error Escape Probability in Count-Based Compaction Schemes. ICCAD 1990: 368-371 - [c3]Yervant Zorian, André Ivanov:
EEODM: An effective BIST scheme for ROMs. ITC 1990: 871-879
1980 – 1989
- 1989
- [c2]Yervant Zorian, Najmi Jarwala:
Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 boundary-scan architecture. ICCD 1989: 580-584 - 1984
- [c1]Yervant Zorian, Vinod K. Agarwal:
Higher Certainty of Error Coverage by Output Data Modification. ITC 1984: 140-147
Coauthor Index
Letícia Maria Veiras Bolzani
aka: Letícia Maria Veiras Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
aka: Letícia Maria Veiras Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
Gurgen Harutunyan
aka: Gurgen Harutyunyan
aka: Gurgen Harutyunyan
[j83] [c182] [c181] [c180] [c179] [c178] [c177] [c175] [c173] [c172] [j81] [c170] [j80] [c169] [c165] [c164] [c163] [c162] [c161] [c159] [c158] [c157] [c155] [c154] [c153] [c149] [c147] [c145] [c142] [c140] [c139] [c137] [c135] [c134] [c133] [c132] [c131] [j73] [j72] [c127] [c126] [c125] [c120] [j65] [c117] [c114] [c113] [c112] [c99]
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