IEEE Transactions on Computers, Volume 43

Volume 43, Number 1, January 1994

Bus Protocols

• 
  Yean-Shiang Leu, David Hung-Chang Du:
  Cycle Compensation Protocol: A Fair Protocol for the Unidirectional Twin-Bus Architecture. 1-12

Graph Theory

• 
  Zevi Miller, Dan Pritikin, Ivan Hal Sudborough:
  Near Embeddings of Hypercubes into Cayley Graphs on the Symmetric Group. 13-22

Hpercubes

• 
  Hsing-Lung Chen, Nian-Feng Tzeng:
  Efficient Resource Placement in Hypercubes Using Multiple-Adjacency Codes. 23-33

Multipliers

• 
  Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi:
  High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits. 34-42

Newton-Raphson Rounding

• 
  Hideyuki Kabuo, Takashi Taniguchi, Akira Miyoshi, Hitoshi Yamashita, Miki Urano, Hisakazu Edamatsu, Shigeo Kuninobu:
  Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation. 43-51

Performance Evaluation

• 
  Mark A. Holliday, Michael Stumm:
  Performance Evaluation of Hierarchical Ring-Based Shared Memory Multiprocessors. 52-67

Residue Arithmetic

• 
  Stanislaw J. Piestrak:
  Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders. 68-77

Residue Number Systems

• 
  Neil M. Wigley, Graham A. Jullien, Daniel Reaume:
  Large Dynamic Range Computations over Small Finite Rings. 78-86

Brief Contributions

• 
  Deng-Jyi Chen, Min-Sheng Lin:
  On Distributed Computing Systems Reliability Analysis Under Program Execution Constraints. 87-97
• 
  Younès Karkouri, El Mostapha Aboulhamid, Eduard Cerny, Alain Verreault:
  Use of Fault Dropping for Multiple Fault Analysis. 98-103
• 
  Keshab K. Parhi, Frank H. Wu, Kalyan Genesan:
  Sequential and Parallel Neural Network Vector Quantizers. 104-109
• 
  Prasant Mohapatra, Chita R. Das, Tse-Yun Feng:
  Performance Analysis of Cluster-Based Multiprocessors. 109-114
• 
  Francisco Corella:
  Automated Verification of Behavioral Equivalence for Microprocessors. 115-117
• 
  K. Vijayan Asari, C. Eswaran:
  An Optimization Technique for the Design of Multiple Valued PLA's. 118-122
• 
  Bapiraju Vinnakota, V. V. Bapeswara Rao:
  Generation of All Reed-Muller Expansions of a Switching Function. 122-124

Comments

• 
  Mario Blaum, Jehoshua Bruck, Ludo M. G. M. Tolhuizen:
  A Note on "A Systematic (12, 8) Code for Correcting Single Errors and Detecting Adjacent Errors". 125
• 
  Syed Masud Mahmud:
  Comments on "Synthetic Traces for Trace-Driven Simulation of Cache Memories". 125-126

Volume 43, Number 2, February 1994

Concurrent Error Detection

• 
  Michael A. Schuette, John Paul Shen:
  Exploiting Instruction-Level Parallelism for Integrated Control-Flow Monitoring. 129-140

Fault Diagnosis

• 
  Mark G. Karpovsky, Lev B. Levitin, Feodor S. Vainstein:
  Diagnosis by Signature Analysis of Test Responses. 141-152

Interconnection Networks

• 
  Youngsong Mun, Hee Yong Youn:
  Performance Analysis of Finite Buffered Multistage Interconnection Networks. 153-162

RSA Computation

• 
  John Burns, Chris J. Mitchell:
  Parameter Selection for Server-Aided RSA Computation Schemes. 163-174

Sensor Networks

• 
  S. Sitharama Iyengar, Doddaballapur Narasimha-Murthy Jayasimha, D. Nadig:
  A Versatile Architecture for the Distributed Sensor Integration Problem. 175-185

Temporal Reasoning

• 
  Walling R. Cyre:
  Conceptual Representation of Waveforms for Temporal Reasoning. 186-200

Test Generation

• 
  Gueesang Lee, Mary Jane Irwin, Robert Michael Owens:
  Polynomial Time Testability of Circuits Generated by Input Decomposition. 201-210

Brief Contributions

• 
  T. V. Lakshman, Victor K. Wei:
  Distributed Computing on Regular Networks with Anonymous Nodes. 211-218
• 
  Shahram Latifi, Manju V. Hegde, Morteza Naraghi-Pour:
  Conditional Connectivity Measures for Large Multiprocessor Systems. 218-222
• 
  Si-Qing Zheng:
  Compressed Tree Machines. 222-225
• 
  Shyue-Win Wei:
  A Systolic Power-Sum Circuit for GF(2^m). 226-229
• 
  Malathi Veeraraghavan, Kishor S. Trivedi:
  A Combinatorial Algorithm for Performance and Reliability Analysis Using Multistate Models. 229-234
• 
  In-Cheol Park, Se-Kyoung Hong, Chong-Min Kyung:
  Two Complementary Approaches for Microcode Bit Optimization. 234-239
• 
  Tein-Yaw Chung, Nita Sharma, Dharma P. Agrawal:
  Cost-Performance Trade-Offs in Manhattan Street Network Versus 2-D Torus. 240-243
• 
  Jianxun Ding, Laxmi N. Bhuyan:
  Finite Buffer Analysis of Multistage Interconnection Networks. 243-247
• 
  Conrad K. Kwok, Biswanath Mukherjee:
  Transparent (Cut-Through) Bridging of CSMA/CD Networks: Performance Analysis and Implementation. 247-253

Comments

• 
  V. Tz. Radoytchevsky, A. Ja. Shalaev:
  Comments on "An O(n^2.5) Fault Identification Algorithm for Diagnosable Systems". 254-255
• 
  A. Shallof, S. Bennett:
  Comments on "Performability Analysis of Distributed Real-Time Systems". 255-256

Volume 43, Number 3, March 1994

Arithmetic Logic Unit Design

• 
  James Phillips, Stamatis Vassiliadis:
  High-Performance 3-1 Interlock Collapsing ALU's. 257-268

Division

• 
  Paolo Montuschi, Luigi Ciminiera:
  Over Redundant Digit Sets and the Design of Digit-by-Digit Division Units. 269-277

Elementary Function Computation

• 
  Weng-Fai Wong, Eiichi Goto:
  Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers. 278-294

Fault Diagnosis

• 
  Laurence E. LaForge, Kaiyuan Huang, Vinod K. Agarwal:
  Almost Sure Diagnosis of Almost Every Good Element. 295-305

Finite-State Machines

• 
  David Lee, Mihalis Yannakakis:
  Testing Finite-State Machines: State Identification and Verification. 306-320

Network Reconfiguration

• 
  Andrew V. Goldberg, Bruce M. Maggs, Serge A. Plotkin:
  A Parallel Algorithm for Reconfiguring a Multibutterfly Network with Faulty Switches. 321-326

Real-Time Systems

• 
  Gopal Agrawal, Biao Chen, Wei Zhao, Sadegh Davari:
  Guaranteeing Synchronous Message Deadlines with the Timed Token Medium Access Control Protocol. 327-339

SMID Networks

• 
  Charles M. Fiduccia, Kevin J. Rappoport:
  Perfect Shifters. IEEE Trans. Computers 43(3): 340-349 (1994)

String Visualization

• 
  Dinesh P. Mehta, Sartaj Sahni:
  Computing Display Conflicts in String Visualization. 350-361

Brief Contributions

• 
  Sulaiman Al-Bassam, Bella Bose:
  Design of Efficient Balanced Codes. 362-365
• 
  Stephen H. Unger:
  Some Additions to "Solution of Switching Equations Based on a Tabular Algebra". 365-367
• 
  Nitin H. Vaidya, Dhiraj K. Pradhan:
  Safe System Level Diagnosis. 367-370
• 
  Gui Liang Feng, T. R. N. Rao, Mahadev S. Kolluru:
  Error Correcting Codes over Z_{2^m} for Algorithm Based Fault Tolerance. 370-374
• 
  Abdullah A. Abonamah, Fadi N. Sibai, N. K. Sharma:
  Conflict Resolution and Fault-Free Path Selection in Multicast-Connected Cube-Based Networks. 374-380

Comments

• 
  Behrooz Parhami:
  Comments on "Evaluation of A + B + K Conditions Without Carry Propagation". 381
• 
  Rajendra S. Katti:
  Comments on "Decomposition of Complex Multipliers Using Polynomial Encoding". 381-383
• 
  Ingo Wegener:
  Comments on "A Characterization of Binary Decision Diagrams". 383-384

Volume 43, Number 4, April 1994

CMOS Synthesis

• 
  Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli:
  Innovative Structures for CMOS Combinational Gates Synthesis. 385-399

Error-Coded Arithmetic

• 
  Jien-Chung Lo:
  Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands. 400-412

Fault-Tolerant Arrays

• 
  John C. Ramirez, Rami G. Melhem:
  Computational Arrays with Flexible Redundancy. 413-430

Performance Modeling

• 
  Pradeep K. Dubey, George B. Adams III, Michael J. Flynn:
  Instruction Window Size Trade-Offs and Characterization of Program Parallelism. 431-442

Spectral Analysis

• 
  Michael J. Corinthios:
  Optimal Parallel and Pipelined Processing Through a New Class of Matrices with Application to Generalized Spectral Analysis. 443-459

State Assignment

• 
  Vitit Kantabutra, Andreas G. Andreou:
  A State Assignment Approach to Asynchronous CMOS Circuit Design. 460-469

Brief Contributions

• 
  Annette Lagman, Walid A. Najjar, Pradip K. Srimani:
  An Analysis of Edge Fault Tolerance in Recursively Decomposable Regular Networks. 470-475
• 
  Shambhu J. Upadhyaya, Bina Ramamurthy:
  Concurrent Process Monitoring with No Reference Signatures. 475-480
• 
  Imrich Chlamtac, András Faragó:
  An Optimal Channel Access Protocol with Multiple Reception Capacity. 480-484
• 
  Shlomo Kipnis:
  Analysis of Asynchronous Binary Arbitration on Digital Transmission-Line Busses. 484-489
• 
  Steven W. Burns, Niraj K. Jha:
  A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme. 490-495
• 
  Shih-Yuang Su, Cheng-Wen Wu:
  Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns. 495-501
• 
  Spencer W. Ng, Richard L. Mattson:
  Uniform Parity Group Distribution in Disk Arrays with Multiple Failures. 501-506

Comments

• 
  Chien-In Henry Chen, Anup Kumar:
  Comments on "Area-Time Optimal Adder Design". 507-512

Volume 43, Number 5, May 1994

Distributed Processing

• 
  Terunao Soneoka, Toshihide Ibaraki:
  Logically Instantaneous Message Passing in Asynchronous Distributed Systems. 513-527

Load Sharing

• 
  Chao-Ju Hou, Kang G. Shin:
  Incorporation of Optimal Timeouts into Distributed Real-Time Load Sharing. 528-547

Shared Queues

• 
  Sundeep Prakash, Yann-Hang Lee, Theodore Johnson:
  A Nonblocking Algorithm for Shared Queues Using Compare-and-Swap. 548-559

Shift Register Sequences

• 
  Douglas W. Clark, Lih-Jyh Weng:
  Maximal and Near-Maximal Shift Register Seqyences: Efficient Event Counters and Easy Discrete Logarithms. 560-568

Testing

• 
  Irith Pomeranz, Sudhakar M. Reddy:
  Application of Homing Sequences to Synchronous Sequential Circuit Testing. 569-580

Wiring Design

• 
  Majid Sarrafzadeh, Dorothea Wagner, Frank Wagner, Karsten Weihe:
  Wiring Knock-Knee Layouts: A Global Approach. 581-589

Brief Contributions

• 
  Sulaiman Al-Bassam, Bella Bose:
  Asymmetric/Unidirectional Error Correcting and Detecting Codes. 590-597
• 
  Vernon L. Chi:
  Salphasic Distribution of Clock Signals for Synchronous Systems. 597-602
• 
  Mallika De, Bhabani P. Sinha:
  Fast Parallel Algorithm for Ternary Multiplication Using Multivalued I²L Technology. 603-607
• 
  Pei-Ji Yang, Sing-Ban Tien, Cauligi S. Raghavendra:
  Embedding of Rings and Meshes onto Faulty Hypercubes Using Free Dimensions. 608-613
• 
  Bing-rung Tsai, Kang G. Shin:
  Assignment of Task Modules in Hypercube Multicomputers with Component Failures for Communication Efficiency. 613-618
• 
  David T. Harper III:
  A Multiaccess Frame Buffer Architecture. 618-622
• 
  Peter Kornerup:
  Digit-Set Conversions: Generalizations and Application. 622-629
• 
  R. Swaminathan, D. Veeramani:
  Decomposition of {0, 1}-Matrices. 629-633
• 
  Alice M. Tokarnia:
  Identifying Minimal Shift Counters: A Search Technique. 633-639

Volume 43, Number 6, June 1994

Algorithm-Based Fault Tolerance

• 
  Dechang Gu, Daniel J. Rosenkrantz, S. S. Ravi:
  Construction of Check Sets for Algorithm-Based Fault Tolerance. 641-650

Cache Management

• 
  Josep Torrellas, Monica S. Lam, John L. Hennessy:
  False Sharing ans Spatial Locality in Multiprocessor Caches. 651-663
• 
  Richard E. Kessler, Mark D. Hill, David A. Wood:
  A Comparison of Trace-Sampling Techniques for Multi-Megabyte Caches. 664-675

Clock Synchronization

• 
  Daniel L. Palumbo:
  The Derivation and Experimental Verification of Clock Synchronization Theory. 676-686

Defect Tolerance

• 
  Claude Thibeault, Yvon Savaria, Jean-Louis Houle:
  A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits. 687-698

Distributed Systems

• 
  Anindo Bagchi, S. Louis Hakimi:
  Information Dissemination in Distributed Systems With Faulty Units. 698-710

Interconnection for VLSI

• 
  D. T. Lee, Chung-Do Yang, C. K. Wong:
  On Bends and Distances of Paths Among Obstacles in Two-Layer Interconnection Model. 711-724

Testing

• 
  Manoj Franklin, Kewal K. Saluja:
  Hypergraph Coloring and Reconfigured RAM Testing. 725-736

VLSI/WSI Reliability Modeling

• 
  Yung-Yuan Chen, Shambhu J. Upadhyaya:
  Modeling the Reliability of a Class of Fault-Tolerant VLSI/WSI Systems Based on Multiple-Level Redundancy. 737-748

Brief Contribution

• 
  Yen-Cheng Chen, Wen-Tsuen Chen:
  Constant Time Sorting on Reconfigurable Meshes. 749-751
• 
  Jean-Michel Muller:
  Some Characterizations of Functions Computable in On-Line Arithmetic. 752-755
• 
  David A. Hoelzeman, Saïd Bettayeb:
  On the Genus of Star Graphs. 755-759
• 
  Dipanwita Roy Chowdhury, Saugata Basu, Idranil Sen Gupta, Parimal Pal Chaudhuri:
  Design of CAECC-Cellular Automata Based Error Correcting Code. 759-764
• 
  Mark A. Heap, M. Ray Mercer:
  Least Upper Bounds an OBDD Sizes. 764-767

Comments

• 
  Cha-Hon Sun, Sheng-De Wang:
  Comments on "Distributed Algorithms for Network Recognition Problems". 768

Volume 43, Number 7, July 1994

Algebraic Path Problem

• 
  Pen-Yuang Chang, Jong-Chuang Tsay:
  A Family of Efficient Regular Arrays for Algebraic Path Problem. 769-777

Asynchronous Networks

• 
  Hosame Abu-Amara, Jahnavi Lokre:
  Election in Asynchronous Complete Networks with Intermittent Link Failures. 778-787

Bus Networks

• 
  Syed Masud Mahmud:
  Performance Analysis of Multilevel Bus Networks for Hierarchical Multiprocessors. 789-805

Hypercube Communication

• 
  Jong Kim, Chita R. Das:
  Hypercube Communication Delay with Wormhole Routing. 806-814

Interconnection Networks

• 
  K. Wendy Tang, Sanjay A. Padubidri:
  Diagonal and Toroidal Mesh Networks. 815-826

Sorting Networks

• 
  Jianli Sun, Eduard Cerny, Jan Gecsei:
  Fault Tolerance in a Class of Sorting Networks. 827-837

Brief Contributions

• 
  Chin-Liang Wang:
  Bit-Level Systolic Array for Fast Exponentiation in GF(2^m). 838-841
• 
  Prithviraj Banerjee, Michael Peercy:
  Design and Evaluation of Hardware Strategies for Reconfiguring Hypercubes and Meshes Under Faults. 841-848
• 
  Sying-Jyan Wang, Niraj K. Jha:
  Algorithm-Based Fault Tolerance for FFT Networks. 849-854
• 
  Youngsong Mun, Hee Yong Youn:
  Performance Modeling and Evaluation of Circuit Switching Using Clos Networks. 854-861

Comments

• 
  Timothy Weller, Bruce E. Hajek:
  Comments on "An Optimal Shortest-Path Routing Policy for Network Computers with Regular Mesh-Connected Topologies". 862-863

Addendum

• 
  Patrick W. Dowd, Kalyani Bogineni, Khaled A. Aly, James A. Perreault:
  Addendum to "Hierarchical Scalable Photonic Architectures for High-Performance Processor Interconnection". 864

Volume 43, Number 8, August 1994

• 
  Jean Vuillemin:
  On Circuits and Numbers. 868-879
• 
  Dhananjay S. Phatak, Israel Koren:
  Hybrid Signed-Digit Number Systems: A Unified Framework for Redundant Number Representations With Bounded Carry Propagation Chains. 880-891
• 
  Peter Kornerup:
  A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms. 892-898
• 
  Dan Zuras:
  More On Squaring and Multiplying Large Integers. 899-908
• 
  Milos D. Ercegovac, Tomás Lang, Paolo Montuschi:
  Very-High Radix Division with Prescaling and Selection by Rounding. 909-918
• 
  Jordi Cortadella, Tomás Lang:
  High-Radix Division and Square-Root with Speculation. 919-931
• 
  Debjit Das Sarma, David W. Matula:
  Measuring the Accuracy of ROM Reciprocal Tables. 932-940
• 
  Nariankadu D. Hemkumar, Joseph R. Cavallaro:
  Redundant and On-Line CORDIC for Unitary Transformations. 941-954
• 
  Jean-Claude Bajard, Sylvanus Kla, Jean-Michel Muller:
  BKM: A New Hardware Algorithm for Complex Elementary Functions. 955-963
• 
  Michael J. Schulte, Earl E. Swartzlander Jr.:
  Hardware Designs for Exactly Rounded Elemantary Functions. 964-973
• 
  David M. Lewis:
  Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit. 974-982
• 
  James Demmel, Xiaoye S. Li:
  Faster Numerical Algorithms via Exception Handling. 983-992

Volume 43, Number 9, September 1994

Context Switching

• 
  Wen-mei W. Hwu, Thomas M. Conte:
  The Susceptibility of Programs to Context Switching. 994-1003

Distributed Memory Multiprocessors

•