DATE 1999: Munich, Germany

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Embedded System Design - The European Technology Driver

Verification of Sequential Circuits

Architectural Issues in Low Power Design

Design Reuse Repository and IP Architecture

High Level Verification

System-Level Power Optimization

Reconfigurability and Other Issues in Embedded System Design

Embedded Core Test Approaches

Use of Combinational Verification

Gate Level Power Estimation and Optimization

Fault Diagnosis Techniques for Analogue Circuits

Resource Sharing in Architectural Synthesis

Mixed Signal Characterization and Test

System Design Methodologies: Modelling, Analysis, Refinement and Synthesis

High Level Test Synthesis

High-Level System Simulation

Analogue Circuit Sizing and Synthesis

VHDL-AMS and HDL Interoperability

Transistor Level Test

Hot Topic - Hardware Synthesis from C/C++ Models

Analogue Modelling and Simulation

Hot Topic - Chip Package Co-Design

Panel: Scaling Towards Nanometer Technologies: Design for Test Challenges

Functional Verification

Bit-Level Logic and Analogue Simulation

Partial and Boundary Scan Test

New Languages for System Specification and Design

Circuit Analysis and Design

Logic Synthesis

IDDX Testing and Defect Modelling

HW/SW Interface Synthesis and Partitioning

Physical Design Issues

Reliability and Symmetry in Architectural Synthesis

Panel - Single Chip or Hybrid System Integration?

Testing Regular Structures and Delay Faults


Modelling of Interconnects

Design Reuse Methodologies for Virtual Components and IP

Embedded Tutorial - Multilanguage System Design


Panel - Java, VHDL-AMS, Ada or C for System Level Specifications?