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ORCIDIEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 22
Volume 22, Number 1, January 2014
- Mustansir Yunus Mukadam, Oscar da Costa Gouveia-Filho, Nicholas Kramer, Xuan Zhang
, Alyssa B. Apsel:
Low-Power, Minimally Invasive Process Compensation Technique for Sub-Micron CMOS Amplifiers. 1-12 - Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas:
Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches. 13-26 - Henry Park, Chih-Kong Ken Yang:
Stability Estimation of a 6T-SRAM Cell Using a Nonlinear Regression. 27-38 - Babak Zamanlooy, Mitra Mirhassani:
Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function. 39-48 - Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee:
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture. 49-61 - Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions. 62-75 - Gang He, Dajiang Zhou, Wei Fei, Zhixiang Chen, Jinjia Zhou, Satoshi Goto:
High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications. 76-89 - Jayita Das, Syed M. Alam, Sanjukta Bhanja:
Nano Magnetic STT-Logic Partitioning for Optimum Performance. 90-98 - Farhad Alibeygi Parsan, Waleed K. Al-Assadi, Scott C. Smith:
Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits. 99-112 - Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li:
ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels. 113-126 - Jing Guo, Liyi Xiao, Zhigang Mao, Qiang Zhao:
Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code. 127-135 - Kai-Chiang Wu, Diana Marculescu:
Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment. 136-145 - Ruben Specogna:
Extraction of VLSI Multiconductor Transmission Line Parameters by Complementarity. 146-154 - Yiding Han, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy:
Exploring High-Throughput Computing Paradigm for Global Routing. 155-167 - Yazhi Huang, Liang Shi, Jianhua Li, Qing'an Li, Chun Jason Xue:
WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture. 168-180 - Jin-Fa Lin:
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through. 181-185 - Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Cosimo Antonio Prete:
Evaluation of Leakage Reduction Alternatives for Deep Submicron Dynamic Nonuniform Cache Architecture Caches. 185-190 - Alex Pappachen James, Linu Rose V. J. Francis, Dinesh Sasi Kumar:
Resistive Threshold Logic. 190-195
Volume 22, Number 2, February 2014
- S. Saqib Khursheed, Kan Shi, Bashir M. Al-Hashimi, Peter R. Wilson, Krishnendu Chakrabarty:
Delay Test for Diagnosis of Power Switches. 197-206 - Yen-Lin Peng, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults. 207-219 - Mohamed Tagelsir Mohammadat, Noohul Basheer Zain Ali, Fawnizu Azmadi Hussin, Mark Zwolinski:
Multivoltage Aware Resistive Open Fault Model. 220-231 - Kashfia Haque, Paul Beckett:
Radiation-Hard Field-Programmable Gate Arrays Configuration Technique Using Silicon on Sapphire. 232-241 - Cédric Killian, Camel Tanougast, Fabrice Monteiro, Abbas Dandache:
Smart Reliable Network-on-Chip. 242-255 - Keheng Huang, Yu Hu, Xiaowei Li:
Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs. 256-269 - Yufu Zhang, Bing Shi, Ankur Srivastava:
Statistical Framework for Designing On-Chip Thermal Sensing Infrastructure in Nanoscale Systems. 270-279 - Vinicius V. A. Camargo, Ben Kaczer, Gilson I. Wirth, Tibor Grasser, Guido Groeseneken:
Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits. 280-285 - Alan Kennedy, Xiaojun Wang:
Ultra-High Throughput Low-Power Packet Classification. 286-299 - Pradip Kumar Sahu, Tapan Shah, Kanchan Manna, Santanu Chattopadhyay:
Application Mapping Onto Mesh-Based Network-on-Chip Using Discrete Particle Swarm Optimization. 300-312 - Cedric Walravens, Wim Dehaene:
Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes. 313-321 - Behzad Zeinali, Tohid Moosazadeh, Mohammad Yavari, Ángel Rodríguez-Vázquez:
Equalization-Based Digital Background Calibration Technique for Pipelined ADCs. 322-333 - Rajath Vasudevamurthy, Pratap Kumar Das, Bharadwaj Amrutur:
Time-Based All-Digital Technique for Analog Built-in Self-Test. 334-342 - Samaneh Babayan Mashhadi, Reza Lotfi:
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator. 343-352 - Shubha Ramakrishnan, Jennifer Hasler:
Vector-Matrix Multiply and Winner-Take-All as an Analog Classifier. 353-361 - Pramod Kumar Meher, Sang Yoon Park:
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay. 362-371 - Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti:
Split-SAR ADCs: Improved Linearity With Power and Speed Optimization. 372-383 - Xuanyao Fong, Yusung Kim, Sri Harsha Choday, Kaushik Roy:
Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells. 384-395 - Jianwei Dai, Menglong Guan, Lei Wang:
Exploiting Early Tag Access for Reducing L1 Data Cache Energy in Embedded Processors. 396-407 - Ghaith Tarawneh, Alex Yakovlev, Terrence S. T. Mak:
Eliminating Synchronization Latency Using Sequenced Latching. 408-419 - Wan-Rone Liou, Mei-Ling Yeh, Ping-Shin Chen, Chun-Chang Tseng, Tang-Yu Huang, Shu-Chia Lin, Cheng-Yu Lin, Chih-Hsiang Sun:
Monolithic Low-EMI CMOS DC-DC Boost Converter for Portable Applications. 420-424 - Taehui Na, Seung-Han Woo, Jisu Kim, Hanwool Jeong, Seong-Ook Jung:
Comparative Study of Various Latch-Type Sense Amplifiers. 425-429 - Shubha Ramakrishnan, Arindam Basu, Leung Kin Chiu, Jennifer Hasler, David V. Anderson, Stephen Brink:
Speech Processing on a Reconfigurable Analog Platform. 430-433 - Cheng-Jyun Li, Tai-Cheng Lee:
2.4-GHz High-Efficiency Adaptive Power. 434-438 - Ahmad Atghiaee, Nasser Masoumi, Payman Zarkesh-Ha, Milad Mehri:
Predictive Application of PIDF and PPC for Interconnects' Crosstalk, TSV, and LER Issues in UDSM ICs and Nano-Systems. 438-443 - Cosmin Popa:
Improved Accuracy Current-Mode Multiplier Circuits With Applications in Analog Signal Processing. 443-447
Volume 22, Number 3, March 2014
- Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel:
Computation on Stochastic Bit Streams Digital Image Processing Case Studies. 449-462 - Yuan-Ho Chen, Jyun-Neng Chen, Tsin-Yuan Chang, Chih-Wen Lu:
High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic. 463-474 - Min-Sheng Kao, Fanta Chen, Yu-Hao Hsu, Jen-Ming Wu:
20-Gb/s CMOS EA/MZ Modulator Driver With Intrinsic Parasitic Feedback Network. 475-483 - Chin-Yao Chang, Kuen-Jong Lee:
On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions. 484-496 - Hari Chauhan, Yongsuk Choi, Marvin Onabajo, In-Seok Jung, Yong-Bin Kim:
Accurate and Efficient On-Chip Spectral Analysis for Built-In Testing and Calibration Approaches. 497-506 - Yu Liu, Kaijie Wu:
Fault-Duration And-Location Aware CED Technique With Runtime Adaptability. 507-515 - Samah Mohamed Saeed, Ozgur Sinanoglu:
Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing. 516-521 - Server Kasap, Soydan Redif:
Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. 522-536 - Mariangela Genovese, Ettore Napoli:
ASIC and FPGA Implementation of the Gaussian Mixture Model Algorithm for Real-Time Segmentation of High Definition Video. 537-547 - Ajay N. Bhoj, Niraj K. Jha:
Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs. 548-561 - Eero Lehtonen, Jussi H. Poikonen, Mika Laiho, Pentti Kanerva:
Large-Scale Memristive Associative Memories. 562-574 - Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Kazuyoshi Okamoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Tetsuya Matsumura, Kazutaka Mori, Kazumasa Yanagisawa:
28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique. 575-584 - Jong-Kwan Woo, Hyunjoong Lee, Hwi-Cheol Kim, Deog-Kyoon Jeong, Suhwan Kim:
1.2 V 10-bit 75 MS/s Pipelined ADC With Phase-Dependent Gain-Transition CDS. 585-592 - Mehdi Saberi, Reza Lotfi:
Segmented Architecture for Successive Approximation Analog-to-Digital Converters. 593-606 - Xiang Hu, Peng Du, Shih-Hung Weng, Chung-Kuan Cheng:
Worst Case Noise Prediction With Nonzero Current Transition Times for Power Grid Planning. 607-620 - Chao-Wen Tzeng, Shi-Yu Huang, Pei-Ying Chao:
Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration. 621-630 - Adrien Le Masle, Wayne Luk:
Mapping Loop Structures Onto Parametrized Hardware Pipelines. 631-640 - Jean-Michel Chabloz, Ahmed Hemani:
Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains. 641-654 - Xiaodong Liu, Gary K. Yeap, Jun Tao, Xuan Zeng:
Integrated Algorithm for 3-D IC Through-Silicon Via Assignment. 655-666 - Chun-Yi Kuo, Chi-Jih Shih, Yi-Chang Lu, James Chien-Mo Li, Krishnendu Chakrabarty:
Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits. 667-674 - Nima Jafarzadeh, Maurizio Palesi, Ahmad Khademzadeh, Ali Afzali-Kusha:
Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip. 675-685 - Shunji Nakata, Hiroki Hanazono, Hiroshi Makino, Hiroki Morimura, Masayuki Miyama, Yoshio Matsuda:
Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage. 686-690 - Palkesh Jain, Frank Cano, Bapana Pudi, N. V. Arvind:
Asymmetric Aging: Introduction and Solution for Power-Managed Mixed-Signal SoCs. 691-695 - Subhadip Kundu, Aniket Jha, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
Framework for Multiple-Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization. 696-700
Volume 22, Number 4, April 2014
- Hyun-Woo Lee, Chulwoo Kim:
Survey and Analysis of Delay-Locked Loops Used in DRAM Interfaces. 701-711 - Kon-Woo Kwon, Sri Harsha Choday, Yusung Kim, Kaushik Roy:
AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture. 712-720 - Hong-Ting Lin, Yi-Lin Chuang, Zong-Han Yang, Tsung-Yi Ho:
Pulsed-Latch Utilization for Clock-Tree Power Optimization. 721-733 - Mingjing Chen, Alex Orailoglu:
Examining Timing Path Robustness Under Wide-Bandwidth Power Supply Noise Through Multi-Functional-Cycle Delay Test. 734-746 - Abhishek A. Sinkar, Hamid Reza Ghasemi, Michael J. Schulte, Ulya R. Karpuzcu, Nam Sung Kim:
Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors. 747-758 - Xiaoxiao Zhang, Farid Boussaïd, Amine Bermak:
32 Bit ×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler. 759-770 - Shmuel Wimer, Israel Koren:
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating. 771-778 - Irith Pomeranz:
Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences. 779-791 - Irith Pomeranz:
Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks. 792-802 - Hyoyoung Shin, Youngkyu Park, Gihwa Lee, Jungsik Park, Sungho Kang:
Interleaving Test Algorithm for Subthreshold Leakage-Current Defects in DRAM Considering the Equal Bit Line Stress. 803-812 - Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors. 813-823 - Jing Ye, Yu Hu, Xiaowei Li, Wu-Tung Cheng, Yu Huang, Huaxing Tang:
Diagnose Failures Caused by Multiple Locations at a Time. 824-837 - Pankaj Golani, Peter A. Beerel:
Area-Efficient Asynchronous Multilevel Single-Track Pipeline Template. 838-849 - Eddie Hung, Steven J. E. Wilton:
Incremental Trace-Buffer Insertion for FPGA Debug. 850-863 - Jason Cong, Bingjun Xiao:
FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects. 864-877 - Cory E. Merkel, Dhireesha Kudithipudi:
Temperature Sensing RRAM Architecture for 3-D ICs. 878-887 - Syed Ahmed Aamir, Pavel Angelov, J. Jacob Wikner:
1.2-V Analog Interface for a 300-MSps HD Video Digitizer in Core 65-nm CMOS. 888-898 - Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi:
Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis. 899-912 - Guoyu Wang, Hongsheng Zhang, Mingying Lu, Chao Zhang, Tao Jiang, Guangyu Guo:
Low-Cost Low-Power ASIC Solution for Both DAB+ and DAB Audio Decoding. 913-921 - Safar Hatami, Mohamed Helaoui, Fadhel M. Ghannouchi, Massoud Pedram:
Single-Bit Pseudoparallel Processing Low-Oversampling Delta-Sigma Modulator Suitable for SDR Wireless Transmitters. 922-931 - Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos:
Fast Design Optimization Through Simple Kriging Metamodeling: A Sense Amplifier Case Study. 932-937 - Shih-Hung Weng, Yulei Zhang, James F. Buckwalter, Chung-Kuan Cheng:
Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects. 938-942 - Jesús Aguado Ruiz, Antonio J. López-Martín, Javier López-Lemus, Jaime Ramírez-Angulo:
Power Efficient Class AB Op-Amps With High and Symmetrical Slew Rate. 943-947 - Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison. 947-951 - Kaiming Nie, Suying Yao, Jiangtao Xu, Jing Gao:
Thirty Two-Stage CMOS TDI Image Sensor With On-Chip Analog Accumulator. 951-956
Volume 22, Number 5, May 2014
- Yuhao Wang, Hao Yu, Wei Zhang:
Nonvolatile CBRAM-Crossbar-Based 3-D-Integrated Hybrid Memory for Data Retention. 957-970 - Mahmood Khayatzadeh, Yong Lian:
Average-8T Differential-Sensing Subthreshold SRAM With Bit Interleaving and 1k Bits Per Bitline. 971-982 - Yansheng Wang, Leibo Liu, Shouyi Yin, Min Zhu, Peng Cao, Jun Yang, Shaojun Wei:
On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time. 983-994 - Mehran Mozaffari Kermani, Reza Azarderakhsh, Chiou-Yng Lee, Siavash Bayat Sarmadi:
Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over GF(2m). 995-1003 - Jonghong Kim, Wonyong Sung:
Rate-0.96 LDPC Decoding VLSI for Soft-Decision Error Correction of NAND Flash Memory. 1004-1015 - Xuehui Zhang, Mohammad Tehranipoor:
Design of On-Chip Lightweight Sensors for Effective Detection of Recycled ICs. 1016-1029 - Shuo Wang, Mohammad Tehranipoor:
Light-Weight On-Chip Structure for Measuring Timing Uncertainty Induced by Noise in Integrated Circuits. 1030-1041 - Itamar Levi, Alexander Belenky, Alexander Fish:
Logical Effort for CMOS-Based Dual Mode Logic Gates. 1042-1053 - Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang, Shaojun Wei:
Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method. 1054-1059 - Min-Woo Lee, Ji-Hwan Yoon, Jongsun Park:
Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority. 1060-1068 - Wen-Hsiang Chang, Mango Chia-Tso Chao, Shi-Hao Chen:
Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer. 1069-1081 - Xiaowen Wu, Yaoyao Ye, Jiang Xu, Wei Zhang, Weichen Liu, Mahdi Nikdast, Xuan Wang:
UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors. 1082-1095 - Ching-Che Chung, Duo Sheng, Sung-En Shen:
High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology. 1096-1105 - Saket Gupta, Sachin S. Sapatnekar:
Variation-Aware Variable Latency Design. 1106-1117 - Takashi Kawamoto, Masato Suzuki, Takayuki Noto:
1.9-ps Jitter, 10.0-dBm-EMI Reduction Spread-Spectrum Clock Generator With Autocalibration VCO Technique for Serial-ATA Application. 1118-1126 - Behzad Dehlaghi, Sebastian Magierowski, Leonid Belostotski:
A 12.5-Gb/s On-Chip Oscilloscope to Measure Eye Diagrams and Jitter Histograms of High-Speed Signals. 1127-1137 - Tseng-Chin Luo, Mango Chia-Tso Chao, Huan-Chi Tseng, Masaharu Goto, Philip A. Fisher, Yuan-Yao Chang, Chi-Min Chang, Takayuki Takao, Katsuhito Iwasaki, Cheng Mao Lee:
Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization. 1138-1149 - Chun-Yi Lee, Niraj K. Jha:
FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks. 1150-1163 - Tien-Yu Lo, Chi-Hsiang Lo:
1-V 365-µW 2.5-MHz Channel Selection Filter for 3G Wireless Receiver in 55-nm CMOS. 1164-1169 - Minoo Mirsaeedi, Andres J. Torres, Mohab H. Anis:
Litho-Friendly Decomposition Method for Self-Aligned Triple Patterning. 1170-1174 - Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo:
Area-Delay Efficient Binary Adders in QCA. 1174-1179 - Kejie Huang, Ning Ning, Yong Lian:
Optimization Scheme to Minimize Reference Resistance Distribution of Spin-Transfer-Torque MRAM. 1179-1182 - Youngjoo Lee, Hoyoung Yoo, Injae Yoo, In-Cheol Park:
High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives. 1183-1187