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ORCID30th Asian Test Symposium 2021: Ehime, Japan
- 30th IEEE Asian Test Symposium, ATS 2021, Matsuyama, Ehime, Japan, November 22-25, 2021. IEEE 2021, ISBN 978-1-6654-4051-6
- Ning Lin, Xiaoming Chen, Chunwei Xia, Jing Ye, Xiaowei Li:
ChaoPIM: A PIM-based Protection Framework for DNN Accelerators Using Chaotic Encryption. 1-6 - Qizhen Xu, Liwei Chen, Gang Shi:
Twine Stack: A Hybrid Mechanism Achieving Less Cost for Return Address Protection. 7-12 - Hung-Yao Chi, Kuen-Jong Lee, Tzu-Chun Jao:
Lightweight Hardware-Based Memory Protection Mechanism on IoT Processors. 13-18 - Shogo Katayama, Yudai Abe, Anna Kuwana, Koji Asami, Masahiro Ishida, Ryuya Ohta, Haruo Kobayashi:
Application of Residue Sampling to RF/AMS Device Testing. 19-24 - Michihiro Shintani
, Mamoru Ishizaka, Michiko Inoue:
Robust Fault-Tolerant Design Based on Checksum and On-Line Testing for Memristor Neural Network. 25-30 - Warin Sootkaneung, Sasithorn Chookaew, Suppachai Howimanporn:
Temperature-Aware Evaluation and Mitigation of Logic Soft Errors Under Circuit Variations. 31-36 - Itsuki Fujita, Yoshikazu Nagamura, Masayuki Arai, Satoshi Fukumoto:
Note on CapsNet-Based Wafer Map Defect Pattern Classification. 37-42 - Yunying Ye, Shan Li, Haihua Shen, Huawei Li, Xiaowei Li:
SeGa: A Trojan Detection Method Combined With Gate Semantics. 43-48 - Yu Tang, Le Zhao, Wei Yuan, Xu Wang:
CausalTester: Measuring the Consistency of Replicated Services via Causality Semantics. 49-54 - Mousum Handique, Jantindra Kumar Deka, Santosh Biswas:
Detection of Stuck-at and Bridging Fault in Reversible Circuits using an Augmented Circuit. 55-60 - Arne Grünhagen, Julien Branlard, Annika Eichler, Gianluca Martino, Görschwin Fey, Marina Tropmann-Frick:
Fault Analysis of the Beam Acceleration Control System at the European XFEL using Data Mining. 61-66 - Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
A Novel Compaction Approach for SBST Test Programs. 67-72 - Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Tobias Faller, Tobias Paxian, Bernd Becker, Matteo Sonza Reorda:
Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor. 73-78 - Felipe Almeida, Levent Aksoy, Jaan Raik, Samuel Pagliarini:
Side-Channel Attacks on Triple Modular Redundancy Schemes. 79-84 - Alireza Mahzoon, Rolf Drechsler:
Polynomial Formal Verification of Prefix Adders. 85-90 - William Souza da Cruz, Raphael Andreoni Camponogara Viera, Jean-Max Dutertre, Jean-Baptiste Rigaud, Guillaume Hubert:
Further Analysis of Laser-induced IR-drop. 91-96 - Yen Tran, Toshihiro Nomura, Mohamed Salim Cherchali, Claire Tassin, Yann Deval, Cristell Maneux:
Investigation of 0.18μm CMOS Sensitivity to BTI and HCI Mechanisms under Extreme Thermal Stress Conditions. 97-102 - Xijiang Lin, Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz:
On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation. 103-108 - Irith Pomeranz:
Positive and Negative Extra Clocking of LFSR Seeds for Reduced Numbers of Stored Tests. 109-114 - Zhendong Wang, Rujia Wang, Zihang Jiang, Xulong Tang, Shouyi Yin, Yang Hu:
Towards a Secure Integrated Heterogeneous Platform via Cooperative CPU/GPU Encryption. 115-120 - Hideyuki Ichihara, Kazunori Yukihiro, Tomoo Inoue:
A Design of Approximate Voting Schemes for Fail-Operational Systems. 121-126 - Stefan Holst, Lim Bumun, Xiaoqing Wen:
GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators. 127-132 - Dun-An Yang, Jing-Jia Liou, Harry H. Chen:
Analyzing Transient Faults and Functional Error Rates of a RISC-V Core: A Case Study. 133-138 - Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Gaku Ogihara, Daisuke Iimori, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
High Precision Measurement of Sub-Nano Ampere Current in ATE Environment. 139-140 - Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima:
A Power Reduction Method for Scan Testing in Ultra-Low Power Designs. 141
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