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ORCIDIEEE Transactions on Very Large Scale Integration Systems, Volume 25
Volume 25, Number 1, January 2017
- Krishnendu Chakrabarty
, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. 1-20 - Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso:
Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces. 21-34 - Muhammad Umar Karim Khan, Asim Khan, Chong-Min Kyung:
EBSCam: Background Subtraction for Ubiquitous Computing. 35-47 - Azadeh Alsadat Emrani Zarandi, Amir Sabbagh Molahosseini, Leonel Sousa, Mehdi Hosseinzadeh:
An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form {2k, 2P-1}. 48-59 - Enyi Yao, Arindam Basu:
VLSI Extreme Learning Machine: A Design Space Exploration. 60-74 - Saeid Gorgin, Ghassem Jaberipur:
Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication. 75-86 - Jun Lin, Zhiyuan Yan, Zhongfeng Wang:
Efficient Soft Cancelation Decoder Architectures for Polar Codes. 87-99 - Jon J. Pimentel, Brent Bohnenstiehl, Bevan M. Baas:
Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs. 100-113 - Poki Chen, Ya-Yun Hsiao, Yi-Su Chung, Wei Xiang Tsai, Jhih-Min Lin:
A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging. 114-124 - Munehiro Kozuma, Yuki Okamoto, Takashi Nakagawa, Takeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Yoshinori Ieda, Naoto Yamade, Hidekazu Miyairi, Makoto Ikeda, Masahiro Fujita, Shunpei Yamazaki:
Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch. 125-138 - Bo-Cheng Charles Lai, Jiun-Liang Lin:
Efficient Designs of Multiported Memory on FPGA. 139-150 - Marco Rabozzi, Gianluca Carlo Durelli, Antonio Miele, John Lillis, Marco Domenico Santambrogio:
Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation. 151-164 - Zia Uddin Ahamed Khan, Mohammed Benaissa:
High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA. 165-176 - Wenchao Qian, Christopher Babecki, Robert Karam, Somnath Paul, Swarup Bhunia:
ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware. 177-188 - Joao Pedro Cerqueira, Mingoo Seok:
Temporarily Fine-Grained Sleep Technique for Near- and Subthreshold Parallel Architectures. 189-197 - Alireza Mahzoon, Bijan Alizadeh:
OptiFEX: A Framework for Exploring Area-Efficient Floating Point Expressions on FPGAs With Optimized Exponent/Mantissa Widths. 198-209 - Erfan Azarkhish, Christoph Pfister, Davide Rossi, Igor Loi, Luca Benini:
Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube. 210-223 - Ahmad T. Sheikh, Aiman H. El-Maleh, Muhammad E. S. Elrabaa, Sadiq M. Sait:
A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy. 224-237 - Martin Omaña, Daniele Rossi, Filippo Fuzzi, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche:
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. 238-246 - Mohsen Raji, Behnam Ghavami:
Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations. 247-260 - Mina A. Farhan, Michel S. Nakhla, Emad Gad, Ramachandra Achar:
Parallel High-Order Envelope-Following Method for Fast Transient Analysis of Highly Oscillatory Circuits. 261-270 - Seongbo Shim, Woohyun Chung, Youngsoo Shin:
Lithography Defect Probability and Its Application to Physical Design Optimization. 271-285 - Albert Ciprut, Eby G. Friedman:
Modeling Size Limitations of Resistive Crossbar Array With Cell Selectors. 286-293 - Marvin Damschen, Lars Bauer, Jörg Henkel:
Timing Analysis of Tasks on Runtime Reconfigurable Processors. 294-307 - Saikat Mondal, Sang-Bock Cho, Bruce C. Kim:
Modeling and Crosstalk Evaluation of 3-D TSV-Based Inductor With Ground TSV Shielding. 308-318 - Xiaoliang Dai, Niraj K. Jha:
Improving Convergence and Simulation Time of Quantum Hydrodynamic Simulation: Application to Extraction of Best 10-nm FinFET Parameter Values. 319-329 - Edoardo Fusella, Alessandro Cilardo:
H2ONoC: A Hybrid Optical-Electronic NoC Based on Hybrid Topology. 330-343 - Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Chulwoo Kim:
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique. 344-353 - Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations. 354-363 - Arshad Hussain, Sai-Weng Sin, Chi-Hang Chan, Ben Seng-Pan U, Franco Maloberti, Rui Paulo Martins:
Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications. 364-374 - Mario Garrido, Miguel Angel Sánchez, María Luisa López Vallejo, Jesús Grajal:
A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices. 375-379 - Taeho Lee, Yong-Hun Kim, Lee-Sup Kim:
A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network. 380-384 - Mohammed Zackriya V, Harish M. Kittur:
Content Addressable Memory - Early Predict and Terminate Precharge of Match-Line. 385-387 - Archit Joshi, Mukul Sarkar:
Nonlinearity Estimation for Compensation of Phase Interpolator in Bang-Bang CDRs. 388-392
Volume 25, Number 2, February 2017
- Reza Zendegani, Mehdi Kamal, Milad Bahadori, Ali Afzali-Kusha, Massoud Pedram:
RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing. 393-401 - Kwen-Siong Chong, Weng-Geng Ho, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang:
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template. 402-415 - Srikar Bhagavatula, Byunghoo Jung:
Variation Resilient Power Sensor With an 80-ns Response Time for Fine-Grained Power Management. 416-426 - Amir M. Rahmani, Mohammad Hashem Haghbayan, Antonio Miele, Pasi Liljeberg, Axel Jantsch, Hannu Tenhunen:
Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon Era. 427-440 - Shoaleh Hashemi Namin, Huapeng Wu, Majid Ahmadi:
Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique. 441-449 - Sundarrajan Rangachari, Jaiganesh Balakrishnan, Nitin Chandrachoodan:
Scenario-Aware Dynamic Power Reduction Using Bias Addition. 450-461 - Arnab Raha, Swagath Venkataramani, Vijay Raghunathan, Anand Raghunathan:
Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations. 462-475 - Hooman Farkhani, Mohammad Tohidi, Ali Peiravi, Jens Kargaard Madsen, Farshad Moradi:
STT-RAM Energy Reduction Using Self-Referenced Differential Write Termination Technique. 476-487 - Chien-Chung Ho, Yu-Ping Liu, Yuan-Hao Chang, Tei-Wei Kuo:
Antiwear Leveling Design for SSDs With Hybrid ECC Capability. 488-501 - Robert Giterman, Lior Atias, Adam Teman:
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications. 502-509 - Chihiro Matsui, Asuka Arakawa, Chao Sun, Ken Takeuchi:
Write Order-Based Garbage Collection Scheme for an LBA Scrambler Integrated SSD. 510-519 - Naifeng Jing, Shunning Jiang, Shuang Chen, Jingjie Zhang, Li Jiang, Chao Li, Xiaoyao Liang:
Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU. 520-533 - Nishit Ashok Kapadia, Sudeep Pasricha:
A Runtime Framework for Robust Application Scheduling With Adaptive Parallelism in the Dark-Silicon Era. 534-546 - Reiley Jeyapaul, Roberto Flores, Alfonso Ávila, Aviral Shrivastava:
Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability. 547-555 - Zhonghai Lu, Yuan Yao:
Dynamic Traffic Regulation in NoC-Based Systems. 556-569 - Kamran Rahmani, Sandip Ray, Prabhat Mishra:
Postsilicon Trace Signal Selection Using Machine Learning Techniques. 570-580 - Shao-Yun Fang, Kuo-Hao Wu:
Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing. 581-593 - Artjom Grudnitsky, Lars Bauer, Jörg Henkel:
Efficient Partial Online Synthesis of Special Instructions for Reconfigurable Processors. 594-607 - Itamar Levi, Alexander Fish, Osnat Keren:
CPA Secured Data-Dependent Delay-Assignment Methodology. 608-620 - I-Jen Chao, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang, Hsin-Wen Ting:
Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing. 621-634 - Massoud Tohidian, Iman Madadi, Robert Bogdan Staszewski:
A Fully Integrated Discrete-Time Superheterodyne Receiver. 635-647 - Isaak Yang, Sung Hoon Jung, Kwang-Hyun Cho:
Self-Repairing Digital System Based on State Attractor Convergence Inspired by the Recovery Process of a Living Cell. 648-659 - Randy W. Mann, William McMahon, Yoann Mamy Randriamihaja, Yuncheng Song, Ajay Anand Kallianpur, Sheng Xie, Akhilesh Gautam, Joseph Versaggi, Biju Parameshwaran, Chad E. Weintraub:
Bias-Induced Healing of $V_{\text {min}}$ Failures in Advanced SRAM Arrays. 660-669 - Zhan-Hui Li, Tao-Tao Zhu, Zhi-Jian Chen, Jian-Yi Meng, Xiaoyan Xiang, Xiaolang Yan:
Eliminating Timing Errors Through Collaborative Design to Maximize the Throughput. 670-682 - Yingnan Cui, Wei Zhang, Bingsheng He:
A Variation-Aware Adaptive Fuzzy Control System for Thermal Management of Microprocessors. 683-695 - Michael Cheah, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei:
A 100-mA, 99.11% Current Efficiency, 2-mVpp Ripple Digitally Controlled LDO With Active Ripple Suppression. 696-704 - Ata Khorami, Mohammad Sharifkhani:
An Efficient Fast Switching Procedure for Stepwise Capacitor Chargers. 705-713 - Jian-Bin Zhou, Dajiang Zhou, Shihao Wang, Shuping Zhang, Takeshi Yoshimura, Satoshi Goto:
A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding. 714-724 - Pingxiuqi Chen, Shaik Nazeem Basha, Mehran Mozaffari Kermani, Reza Azarderakhsh, Jiafeng Xie:
FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over $GF(2^{m})$ and Their Applications in Trinomial Multipliers. 725-734 - Chiou-Yng Lee, Pramod Kumar Meher, Chia-Chen Fan, Shyan-Ming Yuan:
Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition. 735-746 - Zhiheng Wang, Ryan N. Goh, Kia Bazargan, Arnd Scheel, Naman Saraf:
Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map. 747-759 - Moon Gi Seok, Tag Gon Kim, Chang Beom Choi, Daejin Park:
An HLA-Based Distributed Cosimulation Framework in Mixed-Signal System-on-Chip Design. 760-764 - Leonardo Rezende Juracy, Matheus Trevisan Moreira, Felipe Augusto Kuentzer, Alexandre de Morais Amory:
Optimized Design of an LSSD Scan Cell. 765-768 - Hailang Wang, Emre Salman:
Closed-Form Expressions for I/O Simultaneous Switching Noise Revisited. 769-773 - Derui Kong, Dongwon Seo, Sang Min Lee:
Analysis and Reduction of Nonidealities in Stacked-Transistor Current Sources. 774-778 - Ji-Hoon Park, Hyun-Seung Seo, Bai-Sun Kong:
Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application. 779-782 - Chung-Shiang Wu, Hui-Hsuan Lee, Po-Hung Chen, Wei Hwang:
Digital Buck Converter With Switching Loss Reduction Scheme for Light Load Efficiency Enhancement. 783-787 - Kihwan Seong, Won-Cheol Lee, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
All-Synthesizable Current-Mode Transmitter Driver for USB2.0 Interface. 788-792
Volume 25, Number 3, March 2017
- Jungwoo Park, Jongmin Lee, Soontae Kim:
A Way-Filtering-Based Dynamic Logical-Associative Cache Architecture for Low-Energy Consumption. 793-805 - Mengshuo Wang, Changhao Yan, Xin Li, Dian Zhou, Xuan Zeng:
High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis. 806-819 - Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang:
A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements. 820-832 - Menglong Guan, Lei Wang:
Improving DRAM Performance in 3-D ICs via Temperature Aware Refresh. 833-843 - Jooyoung Kim, Woosung Lee, Keewon Cho, Sungho Kang:
Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares. 844-856 - Alejandro Valero, Negar Miralaei, Salvador Petit, Julio Sahuquillo, Timothy M. Jones:
On Microarchitectural Mechanisms for Cache Wearout Reduction. 857-871 - Yang Xu, Xinwang Zhang, Zhihua Wang, Baoyong Chi:
A Flexible Continuous-Time Δ Σ ADC With Programmable Bandwidth Supporting Low-Pass and Complex Bandpass Architectures. 872-880 - Je-Kwang Cho:
A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma-Delta Modulator Using Dynamically Biased Op Amp Sharing. 881-893 - Babak Zamanlooy, Mitra Mirhassani:
An Analog CVNS-Based Sigmoid Neuron for Precise Neurochips. 894-906 - Qing Dong, Kaiyuan Yang, Laura Fick, David Fick, David T. Blaauw, Dennis Sylvester:
Low-Power and Compact Analog-to-Digital Converter Using Spintronic Racetrack Memory Devices. 907-918 - Nashiru Alhassan, Zekun Zhou, Edgar Sánchez-Sinencio:
An All-MOSFET Sub-1-V Voltage Reference With a - 51 -dB PSR up to 60 MHz. 919-928 - Zhao Zhang, Liyuan Liu, Peng Feng, Nanjian Wu:
A 2.4-3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique. 929-941 - Dong Xiang, Xiaoqing Wen, Laung-Terng Wang:
Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding. 942-953 - Saba Amanollahi, Ghassem Jaberipur:
Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems. 954-961 - Hsiang-Jen Tsai, Keng-Hao Yang, Yin-Chi Peng, Chien-Chen Lin, Ya-Han Tsao, Meng-Fan Chang, Tien-Fu Chen:
Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology. 962-973 - Swaminathan Narayanaswamy, Matthias Kauer, Sebastian Steinhorst, Martin Lukasiewycz, Samarjit Chakraborty:
Modular Active Charge Balancing for Scalable Battery Packs. 974-987 - David Cavalheiro, Francesc Moll, Stanimir Stoyanov Valtchev:
Insights Into Tunnel FET-Based Charge Pumps and Rectifiers for Energy Harvesting Applications. 988-997 - Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama:
A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling. 998-1011 - Nezam Rohbani, Mojtaba Ebrahimi, Seyed Ghassem Miremadi, Mehdi Baradaran Tahoori:
Bias Temperature Instability Mitigation via Adaptive Cache Size Management. 1012-1022 - Myat Thu Linn Aung, Takefumi Yoshikawa, Chuan Seng Tan, Tony Tae-Hyoung Kim:
Yield Enhancement of Face-to-Face Cu-Cu Bonding With Dual-Mode Transceivers in 3DICs. 1023-1031 - Wei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok:
In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations. 1032-1043 - Immanuel Raja, Vishal Khatri, Zaira Zahir, Gaurab Banerjee:
A 0.1-2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS. 1044-1053 - Riadul Islam, Matthew R. Guthaus:
CMCS: Current-Mode Clock Synthesis. 1054-1062 - Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas:
Delay Analysis for Current Mode Threshold Logic Gate Designs. 1063-1071 - Ayesha Khalid, Goutam Paul, Anupam Chattopadhyay:
RC4-AccSuite: A Hardware Acceleration Suite for RC4-Like Stream Ciphers. 1072-1084 - Fatemeh Tehranipoor, Nima Karimian, Wei Yan, John A. Chandy:
DRAM-Based Intrinsic Physically Unclonable Functions for System-Level Security and Authentication. 1085-1097 - Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui:
High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder. 1098-1111 - Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Chen Wang:
Trimodal Scan-Based Test Paradigm. 1112-1125 - Karthi Duraisamy, Yuankun Xue, Paul Bogdan, Partha Pratim Pande:
Multicast-Aware High-Performance Wireless Network-on-Chip Architectures. 1126-1139 - Cong Hao, Jianmo Ni, Nan Wang, Takeshi Yoshimura:
Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis. 1140-1153 - S. Rasool Hosseini, Mehdi Saberi, Reza Lotfi:
A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications. 1154-1158 - Guanghui Hu, Jin Sha, Zhongfeng Wang:
High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations. 1159-1163 - Fengjuan Wang, Ningmei Yu:
An Ultracompact Butterworth Low-Pass Filter Based on Coaxial Through-Silicon Vias. 1164-1167 - Dezhi Xing, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, Rui Paulo Martins:
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching. 1168-1172 - Doron Gluzer, Shmuel Wimer:
Probability-Driven Multibit Flip-Flop Integration With Clock Gating. 1173-1177 - Jaewon Jang, Minho Cheong, Jin-Ho Ahn, Sung Kyu Lim, Sungho Kang:
Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation. 1178-1182 - Tae Woo Oh, Hanwool Jeong, Kyoman Kang, Juhyun Park, Younghwi Yang, Seong-Ook Jung:
Power-Gated 9T SRAM Cell for Low-Energy Operation. 1183-1187 - Bin Zhang, Jizhong Zhao:
Hardware Implementation for Real-Time Haze Removal. 1188-1192
Volume 25, Number 4, April 2017
- Naeem Maroof, Bai-Sun Kong:
10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage. 1193-1203 - Raf Appeltans, Praveen Raghavan, Gouri Sankar Kar, Arnaud Furnémont, Liesbet Van der Perre, Wim Dehaene:
A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less. 1204-1214