default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID45th DAC 2008: Anaheim, CA, USA
- Limor Fix:
Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008. ACM 2008, ISBN 978-1-60558-115-6
iDesign I
- Steve Golson, Pete Churchill:
Flow engineering for physical implementation: theory and practice. 1
Special session: enabling concurrency in EDA
- Michael Garland:
Sparse matrix computations on manycore GPU's. 2-6 - Tim Mattson, Michael Wrinn:
Parallel programming: can we PLEASE get it right this time? 7-11 - Bryan Catanzaro, Kurt Keutzer, Bor-Yiing Su:
Parallelizing CAD: a timely research agenda for EDA. 12-17
CAD for FPGA
- Tomasz S. Czajkowski, Stephen Dean Brown:
Functionally linear decomposition and synthesis of logic circuits for FPGAs. 18-23 - Yu Hu, Victor Shih, Rupak Majumdar, Lei He:
FPGA area reduction by multi-output function based sequential resynthesis. 24-29 - Tien-Yuan Hsu, Ting-Chi Wang:
A generalized network flow based algorithm for power-aware FPGA memory mapping. 30-33 - Kenneth Eguro, Scott Hauck:
Enhancing timing-driven FPGA placement for pipelined netlists. 34-37
Analog performance modeling and synthesis
- Xin Li, Hongzhou Liu:
Statistical regression for efficient high-dimensional modeling of analog and mixed-signal performance variations. 38-43 - Angan Das, Ranga Vemuri:
Topology synthesis of analog circuits based on adaptively generated building blocks. 44-49 - Mark Po-Hung Lin, Shyh-Chang Lin:
Analog placement based on hierarchical module clustering. 50-55
Novel techniques in embedded processor design
- Lars Bauer, Muhammad Shafique, Jörg Henkel:
Run-time instruction set selection in a transmutable embedded processor. 56-61 - Yee Jern Chong, Sri Parameswaran
:
Rapid application specific floating-point unit generation with bit-alignment. 62-67 - Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum:
Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency. 68-71 - Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski:
C-based design flow: a case study on G.729A for voice over internet protocol (VoIP). 72-75
Panel
- Tiffany Sparks, Pete Weitzner, Luc Burgun, Russell Lefevre, Todd Cutler, Clayton Parker, Vicki Hadfield, Chris Rowen:
Election year: what the electronics industry needs---and can expect---from the incoming administration. 76-77
Special session: student design contest
- Yu-Kun Lin, De-Wei Li, Chia-Chun Lin, Tzu-Yun Kuo, Sian-Jin Wu, Wei-Cheng Tai, Wei-Cheng Chang, Tian-Sheuan Chang:
A 242mW, 10mm21080p H.264/AVC high profile encoder chip. 78-83 - Taeg Sang Cho, Kyeong-Jae Lee, Jing Kong, Anantha P. Chandrakasan:
The design of a low power carbon nanotube chemical sensor system. 84-89 - Chih-Chi Cheng, Chia-Hua Lin, Chung-Te Li, Samuel C. Chang, Liang-Gee Chen:
iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor. 90-95 - Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, Hoi-Jun Yoo:
Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor. 96-101 - Nathaniel Ross Pinckney, Thomas Barr, Michael Dayringer, Matthew McKnett, Nan Jiang, Carl Nygaard, David Money Harris, Joel Stanley, Braden Phillips:
A MIPS R2000 implementation. 102-107 - Jaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy:
Process variation tolerant SRAM array for ultra low voltage applications. 108-113 - Yuen-Hui Chee, Mike Koplow, Michael Mark, Nathan Pletcher, Mike Seeman, Fred L. Burghardt, Dan Steingart, Jan M. Rabaey, Paul K. Wright, Seth Sanders:
PicoCube: a 1 cm3 sensor node powered by harvested energy. 114-119 - Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger:
An 8x8 run-time reconfigurable FPGA embedded in a SoC. 120-125
Panel
- Sachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou:
Reinventing EDA with manycore processors. 126-127
Panel
- Eshel Haritan, Toshihiro Hattori, Hiroyuki Yagi, Pierre G. Paulin, Wayne H. Wolf, Achim Nohl, Drew Wingard, Mike Muller:
Multicore design is the challenge! what is the solution? 128-130
Formal verification technology
- In-Ho Moon:
Compositional verification of retiming and sequential optimizations. 131-136 - Malay K. Ganai, Aarti Gupta:
Tunneling and slicing: towards scalable BMC. 137-142 - Yan Chen, Fei Xie, Jin Yang:
Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation. 143-148 - Paul T. Darga, Karem A. Sakallah, Igor L. Markov:
Faster symmetry discovery using sparsity of symmetries. 149-154
Layout techniques for modern chip designs
- Dipanjan Sengupta, Resve A. Saleh:
Application-driven floorplan-aware voltage island design. 155-160 - Jackey Z. Yan, Chris Chu:
DeFer: deferred decision making enabled fixed-outline floorplanner. 161-166 - Zhe-Wei Jiang, Bor-Yiing Su, Yao-Wen Chang:
Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs. 167-172 - Tao Xu, Krishnendu Chakrabarty:
Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips. 173-178
Application mapping and power efficiency
- Zhen Cao, Brian Foo, Lei He, Mihaela van der Schaar:
Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications. 179-184 - Ranjani Sridharan, Nikhil Gupta, Rabi N. Mahapatra:
Feedback-controlled reliability-aware power management for real-time embedded systems. 185-190 - Michel Goraczko, Jie Liu, Dimitrios Lymberopoulos, Slobodan Matic, Bodhi Priyantha, Feng Zhao:
Energy-optimal software partitioning in heterogeneous multiprocessor embedded systems. 191-196 - Ya-Shuai Lü, Li Shen, Libo Huang, Zhiying Wang, Nong Xiao:
Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques. 197-200 - Rogier Baert, Eddy de Greef, Erik Brockmeyer:
An automatic scratch pad memory management tool and MPEG-4 encoder case study. 201-204
Variation-aware design
- Mohamed H. Abu-Rahma, Kinshuk Chowdhury, Joseph Wang, Zhiqin Chen, Sei Seung Yoon, Mohab Anis:
A methodology for statistical estimation of read access yield in SRAMs. 205-210 - Jieyi Long, Seda Ogrenci Memik:
Automated design of self-adjusting pipelines. 211-216 - Pouria Bastani, Kip Killpack, Li-C. Wang, Eli Chiprout:
Speedpath prediction based on learning from a small set of examples. 217-222 - Yi Wang, Wai-Shing Luk, Xuan Zeng, Jun Tao, Changhao Yan, Jiarong Tong, Wei Cai, Jia Ni:
Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays. 223-226 - Amit Goel, Sarma B. K. Vrudhula:
Statistical waveform and current source based standard cell models for accurate timing analysis. 227-230
iDesign II
- Clifford E. Cummings:
SystemVerilog implicit port enhancements accelerate system design & verification. 231-236 - Kelly D. Larson:
Translation of an existing VMM-based SystemVerilog testbench to OVM. 237
Multi-core simulation, mixed-signal power optimization and nanodevices
- Wei Dong, Peng Li, Xiaoji Ye:
WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines. 238-243 - Brian P. Ginsburg, Anantha P. Chandrakasan:
The mixed signal optimum energy point: voltage and parallelism. 244-249 - Chaitanya Kshirsagar, Mohamed N. El-Zeftawi, Kaustav Banerjee:
Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs. 250-255
Experiences and advances in formal and dynamic verification
- Babu Turumella, Mukesh Sharma:
Assertion-based verification of a 32 thread SPARCTM CMT microprocessor. 256-261 - Onur Guzey, Li-C. Wang, Jeremy R. Levitt, Harry Foster:
Functional test selection based on unsupervised support vector analysis. 262-267 - C. Richard Ho, Michael Theobald, Martin M. Deneroff, Ron O. Dror, Joseph Gagliardo, David E. Shaw:
Early formal verification of conditional coverage points to identify intrinsically hard-to-verify logic. 268-271
Emerging nano/biotechnologies
- Mihir R. Choudhury, Youngki Yoon, Jing Guo, Kartik Mohanram:
Technology exploration for graphene nanoribbon FETs. 272-277 - Jing Li, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy:
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. 278-283 - Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang:
A progressive-ILP based routing algorithm for cross-referencing biochips. 284-289
Cache optimization and embedded systems modeling
- Jürgen Schnerr, Oliver Bringmann, Alexander Viehl, Wolfgang Rosenstiel:
High-performance timing simulation of embedded software. 290-295 - Swarup Mohalik, A. C. Rajeev, Manoj G. Dixit, S. Ramesh, P. Vijay Suman, Paritosh K. Pandya, Shengbing Jiang:
Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts. 296-299 - Vivy Suhendra, Tulika Mitra:
Exploring locking & partitioning for predictable shared caches on multi-cores. 300-303 - Garo Bournoutian, Alex Orailoglu:
Miss reduction in embedded processors through dynamic, power-friendly cache design. 304-309
Panel
- Hiroyuki Yagi, Wolfgang Roesner, Tim Kogel, Eshel Haritan, Hidekazu Tangi, Michael McNamara, Gary Smith, Nikil D. Dutt, Giovanni Mancini:
ESL hand-off: fact or EDA fiction? 310-312
Analytical modeling and simulation of complex processing systems
- Sebastian Herbert, Diana Marculescu:
Characterizing chip-multiprocessor variability-tolerance. 313-318 - Yun Liang, Tulika Mitra:
Cache modeling in probabilistic execution time analysis. 319-324 - Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Multiprocessor performance estimation using hybrid simulation. 325-330 - Chia-Jui Hsu, José Luis Pino, Shuvra S. Bhattacharyya:
Multithreaded simulation for synchronous dataflow graphs. 331-336
Special session: wild and crazy ideas
- Jay B. Brockman, Sheng Li, Peter M. Kogge, Amit Kashyap, Mohammad M. Mojarradi:
Design of a mask-programmable memory/multiplier array using G4-FET technology. 337-338 - M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli:
Programmable logic circuits based on ambipolar CNFET. 339-340 - Daeik D. Kim, Choongyeun Cho, Jonghae Kim:
Analog parallelism in ring-based VCOs. 341-342 - Claudio Favi, Edoardo Charbon:
Techniques for fully integrated intra-/inter-chip optical communication. 343-344 - Min Li, Bruno Bougard, David Novo, Liesbet Van der Perre, Francky Catthoor:
How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach. 345-346 - Puneet Gupta, Andrew B. Kahng:
Bounded-lifetime integrated circuits. 347-348 - Seetharam Narasimhan, Somnath Paul, Swarup Bhunia:
Collective computing based on swarm intelligence. 349-350 - Miodrag Potkonjak, Farinaz Koushanfar:
(Bio)-behavioral CAD. 351-352
Panel
- Juan C. Rey, Andreas Kuehlmann, Jan M. Rabaey, Cormac Conroy, Ted Vucurevich, Ikuya Kawasaki, Tuna B. Tarim:
Next generation wireless-multimedia devices: who is up for the challenge? 353-354
Diagnosis and debug
- Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir:
Statistical diagnosis of unmodeled systematic timing effects. 355-360 - Xiaochun Yu, R. D. (Shawn) Blanton:
Multiple defect diagnosis using no assumptions on failing pattern characteristics. 361-366 - Wing Chiu Tam, Osei Poku, R. D. (Shawn) Blanton:
Precise failure localization using automated layout analysis of diagnosis candidates. 367-372 - Sung-Boem Park, Subhasish Mitra:
IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors. 373-378
Architectural and precision optimization in high-level synthesis
- Bita Gorjiara, Daniel Gajski:
Automatic architecture refinement techniques for customizing processing elements. 379-384 - Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel:
Formal datapath representation and manipulation for implementing DSP transforms. 385-390 - Arash Ahmadi, Mark Zwolinski:
Symbolic noise analysis approach to computational hardware optimization. 391-396 - Yu Pang, Katarzyna Radecka:
Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform. 397-402
Extraction, interconnect and timing
- Khaled R. Heloue, Farid N. Najm:
Parameterized timing analysis with general delay models and arbitrary variation sources. 403-408 - Boyuan Yan, Lingfei Zhou, Sheldon X.-D. Tan, Jie Chen, Bruce McGaughy:
DeMOR: decentralized model order reduction of linear networks with massive ports. 409-414 - Tarek Moselhy, Luca Daniel:
Stochastic integral equation solver for efficient variation-aware interconnect extraction. 415-420 - Ki Jin Han, Madhavan Swaminathan, Ege Engin:
Electric field integral equation combined with cylindrical conduction mode basis functions for electrical modeling of three-dimensional interconnects. 421-424 - Peter Feldmann, Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta:
Driver waveform computation for timing analysis with multiple voltage threshold driver models. 425-428
Architectures for on-chip communication
- Hazem Moussa, Amer Baghdadi, Michel Jézéquel:
Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder. 429-434 - Aydin O. Balkan, Gang Qu, Uzi Vishkin:
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing. 435-440 - Zhen Zhang, Alain Greiner, Sami Taktak:
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip. 441-446 - Woo-Cheol Kwon, Sungjoo Yoo, Sung-Min Hong, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo:
A practical approach of memory access parallelization to exploit multiple off-chip DDR memories. 447-452
Special session: CMOS gate modeling for timing, noise, and power: rapidly changing paradigm
- Peter Feldmann, Soroush Abbaspour:
Towards a more physical approach to gate modeling for timing, noise, and power. 453-455 - Shiva Raja, F. Varadi, Murat R. Becer, Joao Geada:
Transistor level gate modeling for accurate and fast timing, noise, and power analysis. 456-461 - Noel Menezes, Chandramouli V. Kashyap, Chirayu S. Amin:
A "true" electrical cell model for timing, noise, and power grid verification. 462-467 - Igor Keller, King Ho Tam, Vinod Kariat:
Challenges in gate level modeling for delay and SI at 65nm and below. 468-473 - Richard Trihy:
Addressing library creation challenges from recent Liberty extensions. 474-479
Advanced wireless design
- Christian Sauer, Matthias Gries, Hans-Peter Löb:
SystemClick: a domain-specific framework for early exploration using functional performance models. 480-485 - Joon Goo Lee, Dongha Jung, Jiho Chu, Seokjoong Hwang, Jong-Kook Kim, Janam Ku, Seon Wook Kim:
Applying passive RFID system to wireless headphones for extreme low power consumption. 486-491 - Shreyas Sen, Vishwanath Natarajan, Rajarajan Senguttuvan, Abhijit Chatterjee:
Pro-VIZOR: process tunable virtually zero margin low power adaptive RF for wireless systems. 492-497 - Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud:
Automated design of tunable impedance matching networks for reconfigurable wireless applications. 498-503
Manufacturing aware design and design aware manufacturing
- Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan:
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction. 504-509 - Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang:
Predictive formulae for OPC with applications to lithography-friendly routing. 510-515 - Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao:
Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. 516-521 - Siew-Hong Teh, Chun-Huat Heng, Arthur Tay:
Design-process integration for performance-based OPC framework. 522-527
Advances in sequential optimization
- Jia Wang, Hai Zhou:
An efficient incremental algorithm for min-area retiming. 528-533 - Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton:
Scalable min-register retiming under timing and initializability constraints. 534-539 - Michael L. Case, Victor N. Kravets, Alan Mishchenko, Robert K. Brayton:
Merging nodes under sequential observability. 540-545 - Yousra Alkabani, Farinaz Koushanfar:
N-variant IC design: methodology and applications. 546-551
Panel
- Andreas Kuehlmann, Anjan Bose, David E. Corman, Rob A. Rutenbar, Robert M. Manning, Anna Newman:
Verifying really complex systems: on earth and beyond. 552-553
Beyond the die - packaging and die stacking
- Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Hai Li, Yiran Chen:
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. 554-559 - Krishna Bharath, Ege Engin, Madhavan Swaminathan:
Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM. 560-565 - Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong:
Topological routing to maximize routability for package substrate. 566-569 - Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch, George A. Katopis, Daniel M. Dreps, Ernest S. Kuh, Chung-Kuan Cheng:
Low power passive equalizer optimization using tritonic step response. 570-573
Special session: ESL methodologies for platform-based synthesis
- Hristo Nikolov, Mark Thompson, Todor P. Stefanov, Andy D. Pimentel, Simon Polstra, Raj Bose, Claudiu Zissulescu, Ed F. Deprettere:
Daedalus: toward composable multimedia MP-SoC design. 574-579 - Christian Haubelt, Thomas Schlichter, Joachim Keinert, Michael Meredith:
SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models. 580-585 - Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Daniel Gajski, Atsushi Nakamura, Dai Araki, Yuuji Nishihara:
Specify-explore-refine (SER): from specification to implementation. 586-591
Special session: wireless: business meets technology
- Risto Savolainen, Tero Rissa:
Standard interfaces in mobile terminals: increasing the efficiency of device design and accelerating innovation. 592 - Matt Nowak, Jose Corleto, Christopher Chun, Riko Radojcic:
Holistic pathfinding: virtual wireless chip design for advanced technology and design exploration. 593
Leakage analysis and optimization
- Tao Li, Wenjun Zhang, Zhiping Yu:
Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and verification. 594-599