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ORCID41st DAC 2004: San Diego, CA, USA
- Sharad Malik, Limor Fix, Andrew B. Kahng:
Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004. ACM 2004, ISBN 1-58113-828-8
Panel
- Robert Dahlberg, Kurt Keutzer, R. Bingham, Aart J. de Geus, Walden C. Rhines:
EDA: this is serious business. 1
Hot Leakage
- Arman Vassighi, Ali Keshavarzi, Siva G. Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De:
Design optimizations for microprocessors at low temperature. 2-5 - Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy:
Leakage in nano-scale technologies: mechanisms, impact and design considerations. 6-11 - Lei He, Weiping Liao, Mircea R. Stan
:
System level leakage reduction considering the interdependence of temperature and leakage. 12-17
Clock Routing and Buffering
- Anand Rajaram, Jiang Hu, Rabi N. Mahapatra:
Reducing clock skew variability via cross links. 18-23 - Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay:
Fast and flexible buffer trees that navigate the physical layout environment. 24-29 - Xun Liu, Yuantao Peng, Marios C. Papaefthymiou:
Practical repeater insertion for low power: what repeater library do we need? 30-35
Tools and Strategies for Dynamic Verification
- Michael L. Behm, John M. Ludden, Yossi Lichtenstein, Michal Rimon, Michael Vinov:
Industrial experience with test generation languages for processor verification. 36-40 - Sigal Asaf, Eitan Marcus, Avi Ziv:
Defining coverage views to improve functional coverage analysis. 41-44 - Young-Su Kwon, Young-Il Kim, Chong-Min Kyung:
Systematic functional coverage metric synthesis from hierarchical temporal event relation graph. 45-48 - Shai Fine, Shmuel Ur, Avi Ziv:
Probabilistic regression suites for functional verification. 49-54
Timing-Driven System Synthesis
- Daniel L. Rosenband, Arvind:
Modular scheduling of guarded atomic actions. 55-60 - Kai Kapp, Viktor K. Sabelfeld:
Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis. 61-66 - Fan Mo, Robert K. Brayton:
A timing-driven module-based chip design flow. 67-70 - Anders Edman, Christer Svensson:
Timing closure through a globally synchronous, timing partitioned design methodology. 71-74
Reliable System-on-a-chip Design in the Nanometer Era
- Shekhar Borkar, Tanay Karnik, Vivek De:
Design and reliability challenges in nanometer technologies. 75 - Naresh R. Shanbhag:
A communication-theoretic design paradigm for reliable SOCs. 76 - Giovanni De Micheli:
Reliable communication in systems on chips. 77 - Todd M. Austin:
Designing robust microarchitectures. 78 - Ravishankar K. Iyer:
Hierarchical application aware error detection and recovery. 79
Panel
- Andreas J. Strojwas, Michael Campbell, Vassilios Gerousis, Jim Hogan, John Kibarian, Marc Levitt, Walter Ng, Dipu Pramanik, Mark Templeton:
When IC yield missed the target, who is at fault? 80
Power Modeling and Optimization for Embedded Systems
- Chun-Gi Lyuh, Taewhan Kim:
Memory access scheduling and binding considering energy minimization in multi-bank memory systems. 81-86 - Jaewon Seo, Taewhan Kim, Ki-Seok Chung:
Profile-based optimal intra-task voltage scheduling for hard real-time applications. 87-92 - Juan Antonio Carballo, Kevin J. Nowka, Seung-Moon Yoo, Ivan Vo, Clay Cranford, V. Robert Norman:
Requirement-based design methods for adaptive communications links. 93-98 - Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Automated energy/performance macromodeling of embedded software. 99-102 - Srinivasa R. Sridhara, Naresh R. Shanbhag:
Coding for system-on-chip networks: a unified framework. 103-106
Performance Evaluation and Run Time Support
- Tobias Schüle, Klaus Schneider:
Abstraction of assembler programs for symbolic worst case execution time analysis. 107-112 - Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane:
Extending the transaction level modeling approach for fast communication architecture exploration. 113-118 - Javier Resano, Daniel Mozos:
Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware. 119-124 - Mahmut T. Kandemir:
LODS: locality-oriented dynamic scheduling for on-chip multiprocessors. 125-128 - Carlo Brandolese, William Fornaciari, Fabio Salice:
An area estimation methodology for FPGA based designs at systemc-level. 129-132
Advances in Analog Circuit and Layout Synthesis
- Johan P. Vanderhaegen, Robert W. Brodersen:
Automated design of operational transconductance amplifiers using reversed geometric programming. 133-138 - Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, Chuanjin Richard Shi:
Correct-by-construction layout-centric retargeting of large analog designs. 139-144 - Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri:
Fast and accurate parasitic capacitance models for layout-aware. 145-150 - Yang Xu, Lawrence T. Pileggi, Stephen P. Boyd:
ORACLE: optimization with recourse of analog circuits including layout extraction. 151-154 - Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley:
A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits. 155-158
Power Grid Design and Analysis Techniques
- Kai Wang, Malgorzata Marek-Sadowska:
Buffer sizing for clock power minimization subject to general skew constraints. 159-164 - Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda:
Optimal placement of power supply pads and pins. 165-170 - Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda:
A stochastic approach To power grid analysis. 171-176 - Su-Wei Wu, Yao-Wen Chang:
Efficient power/ground network analysis for power integrity-driven design methodology. 177-180 - Goeran Jerke, Jens Lienig, Jürgen Scheible:
Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs. 181-184
Panel
- Nitin Deo, Behrooz Zahiri, Ivo Bolsens, Jason Cong, Bhusan Gupta, Philip Lopresti, Christopher B. Reynolds, Chris Rowen, Ray Simar:
What happened to ASIC?: Go (recon)figure? 185
Methods for A Priori Feasible Layout Generation
- Li-Da Huang, Martin D. F. Wong:
Optical proximity correction (OPC): friendly maze routing. 186-191 - Narendra V. Shenoy, Jamil Kawa, Raul Camposano:
Design automation for mask programmable fabrics. 192-197 - Yajun Ran, Malgorzata Marek-Sadowska:
On designing via-configurable cell blocks for regular fabrics. 198-203 - V. Kheterpal, Andrzej J. Strojwas, Lawrence T. Pileggi:
Routing architecture exploration for regular fabrics. 204-207 - Hiroaki Yoshida, Kaushik De, Vamsi Boppana:
Accurate pre-layout estimation of standard cell characteristics. 208-211
Abstraction Techniques for Functional Verification
- Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang:
An efficient finite-domain constraint solver for circuits. 212-217 - Zaher S. Andraus, Karem A. Sakallah:
Automatic abstraction and verification of verilog models. 218-223 - Freddy Y. C. Mang, Pei-Hsin Ho:
Abstraction refinement by controllability and cooperativeness analysis. 224-229 - Yuan Lu, Mike Jorda:
Verifying a gigabit ethernet switch using SMV. 230-233 - Hazem I. Shehata, Mark D. Aagaard:
A general decomposition strategy for verifying register renaming. 234-237
Memory and Network Optimization in Embedded Designs
- Francesco Poletti, Paul Marchal, David Atienza, Luca Benini, Francky Catthoor, Jose Manuel Mendias:
An integrated hardware/software approach for run-time scratchpad management. 238-243 - Eduardo Braulio Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo:
Multi-profile based code compression. 244-249 - Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya:
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. 250-255 - Vincent Nollet, Théodore Marescaux, Diederik Verkest, Jean-Yves Mignolet, Serge Vernalde:
Operating-system controlled network on chip. 256-259 - Jingcao Hu, Radu Marculescu:
DyAD: smart routing for networks-on-chip. 260-263
Business Day Session
- Ellen Sentovich, Jaswinder Ahuja, Paul Lippe, Bernie Rosenthal:
Competitive strategies for the electronics industry. 264 - Ellen Sentovich, Raul Camposano, Jim Douglas, Aurangzeb Khan:
Business models in IP, software licensing, and services. 264
The Future of Timing Closure
- David S. Kung:
Timing closure for low-FO4 microprocessor design. 265-266 - Paul K. Rodman:
Forest vs. trees: where's the slack? 267 - Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen:
Efficient timing closure without timing driven placement and routing. 268-273
Panel
- Francine Bacchini, Robert F. Damiano, Bob Bentley, Kurt Baty, Kevin Normoyle, Makoto Ishii, Einat Yogev:
Verification: what works and what doesn't. 274
Design Space Exploration and Scheduling for Embedded Software
- Ravindra Jejurikar, Cristiano Pereira, Rajesh K. Gupta:
Leakage aware dynamic voltage scaling for real-time embedded systems. 275-280 - Lukai Cai, Andreas Gerstlauer, Daniel Gajski:
Retargetable profiling for rapid, early system-level design space exploration. 281-286 - Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Donald E. Thomas, Faraydon Karim:
High level cache simulation for heterogeneous multiprocessors. 287-292
Advances in Accelerated Simulation
- Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong-Min Kyung:
Communication-efficient hardware acceleration for fast functional simulation. 293-298 - Yuichi Nakamura, Kohei Hosokawa, Ichiro Kuroda, Ko Yoshikawa, Takeshi Yoshimura:
A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication. 299-304 - Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David T. Blaauw, Trevor N. Mudge:
Circuit-aware architectural simulation. 305-310
Design for Manufacturing
- Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang:
Toward a methodology for manufacturability-driven design rule exploration. 311-316 - Kevin W. McCullen:
Phase correct routing for alternating phase shift masks. 317-320 - Puneet Gupta, Fook-Luen Heng:
Toward a systematic-variation aware timing methodology. 321-326 - Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester:
Selective gate-length biasing for cost-effective runtime leakage control. 327-330
Statistical Timing Analysis
- Chandramouli Visweswariah, K. Ravindran, Kerim Kalafala, Steven G. Walker, S. Narayan:
First-order incremental block-based statistical timing analysis. 331-336 - Michael Orshansky, Arnab Bandyopadhyay:
Fast statistical timing analysis handling arbitrary delay correlations. 337-342 - Jiayong Le, Xin Li, Lawrence T. Pileggi:
STAC: statistical timing analysis with correlation. 343-348
Panel
- Francine Bacchini, Pierre G. Paulin, Reinaldo A. Bergamaschi, Raj Pawate, Arie Bernstein, Ramesh Chandra, Mohamed Ben-Romdhane:
System level design: six success stories in search of an industry. 349-350
New Ideas in Placement
- Zhong Xiu, James D. Z. Ma, Suzanne M. Fowler, Rob A. Rutenbar:
Large-scale placement by grid-warping. 351-356 - Andrew B. Kahng, Sherief Reda:
Placement feedback: a concept and method for better min-cut placements. 357-362 - Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dysart, Xiaobo Sharon Hu, Andrew B. Kahng, Peter M. Kogge, Richard C. Murphy, Michael T. Niemier:
Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions. 363-368
Model Order Reduction and Variational Techniques for Parasitic Analysis
- Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh:
Passivity-preserving model reduction via a computationally efficient project-and-balance scheme. 369-374 - Janet Meiling Wang, Omar Hafiz, Jun Li:
A linear fractional transform (LFT) based model for interconnect parametric uncertainty. 375-380 - Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula:
Variational delay metrics for interconnect timing analysis. 381-384 - Luís Miguel Silveira, Joel R. Phillips:
Exploiting input information in a model reduction algorithm for massively coupled parasitic networks. 385-388
Compilation Techniques for Embedded Applications
- Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee:
Automatic translation of software binaries onto FPGAs. 389-394 - Philip Brisk, Adam Kaplan, Majid Sarrafzadeh:
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. 395-400 - Ozcan Ozturk, Mahmut T. Kandemir, I. Demirkiran, Guangyu Chen, Mary Jane Irwin:
Data compression for improving SPM behavior. 401-406
Platform-based System Design
- Gary Smith:
Platform based design: does it answer the entire SoC challenge? 407 - Mark Hopkins:
Nomadic platform approach for wireless mobile multimedia. 408 - Alberto L. Sangiovanni-Vincentelli, Luca P. Carloni, Fernando De Bernardinis, Marco Sgroi:
Benefits and challenges for platform-based design. 409-414 - Max Baron:
Trends in the use of re-configurable platforms. 415
Innovations in Logic Synthesis
- David Bañeres, Jordi Cortadella, Michael Kishinevsky:
A recursive paradigm to solve Boolean relations. 416-421 - Nikhil Saluja, Sunil P. Khatri:
A robust algorithm for approximate compatible observability don't care (CODC) computation. 422-427 - Tsutomu Sasao, Munehiro Matsuura:
A method to decompose multiple-output logic functions. 428-433 - Kuo-Hua Wang, Jia-Hung Chen:
Symmetry detection for incompletely specified functions. 434-437 - Victor N. Kravets, Prabhakar Kudva:
Implicit enumeration of structural changes in circuit optimization. 438-441
Yield Estimation and Optimization
- Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester:
Parametric yield estimation considering leakage variability. 442-447 - Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang:
A methodology to improve timing yield in the presence of process variations. 448-453 - Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy:
Novel sizing algorithm for yield improvement under process variation in nanometer technology. 454-459 - Farid N. Najm, Noel Menezes:
Statistical timing analysis based on a timing yield model. 460-465
High-level Techniques for Signal Processing
- Abhijit K. Deb, Axel Jantsch, Johnny Öberg:
System design for DSP applications in transaction level modeling paradigm. 466-471 - Bin Wu, Jianwen Zhu, Farid N. Najm:
An analytical approach for dynamic range estimation. 472-477 - Changchun Shi, Robert W. Brodersen:
Automated fixed-point data-type optimization tool for signal processing and communication systems. 478-483 - Sanghamitra Roy, Prithviraj Banerjee:
An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design. 484-487 - Marghoob Mohiyuddin, Amit Prakash, Adnan Aziz, Wayne H. Wolf:
Synthesizing interconnect-efficient low density parity check codes. 488-491
Advanced Test Solutions
- Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir:
On path-based learning and its applications in delay test and diagnosis. 492-497 - Vinay Verma, Shantanu Dutt, Vishal Suthar:
Efficient on-line testing of FPGAs with provable diagnosabilities. 498-503 - Wei Li, Sudhakar M. Reddy, Irith Pomeranz:
On test generation for transition faults with minimized peak power dissipation. 504-509 - Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski:
A new state assignment technique for testing and low power. 510-513 - Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel:
Automatic generation of breakpoint hardware for silicon debug. 514-517
Panel
- Richard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah:
Is statistical timing statistically significant? 498
Advances in Boolean Analysis Techniques
- Yoonna Oh, Maher N. Mneimneh, Zaher S. Andraus, Karem A. Sakallah, Igor L. Markov:
AMUSE: a minimally-unsatisfiable subformula extractor. 518-523 - Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening:
A SAT-based algorithm for reparameterization in symbolic simulation. 524-529 - Paul T. Darga, Mark H. Liffiton, Karem A. Sakallah, Igor L. Markov:
Exploiting structure in symmetry detection for CNF. 530-534 - Chao Wang, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi:
Refining the SAT decision ordering for bounded model checking. 535-538 - Demos Anastasakis, Lisa McIlwain, Slawomir Pilarski:
Efficient equivalence checking with partitions and hierarchical cut-points. 539-542
Panel
- Shishpal Rawat, William H. Joyner Jr., John A. Darringer, Daniel Gajski, Pat O. Pistilli, Hugo De Man, Carl Harris, James Solomon:
Were the good old days all that good?: EDA then and now. 543
Power Optimization for Real-Time and Media-Rich Embedded Systems
- Kihwan Choi, Ramakrishna Soma, Massoud Pedram:
Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding. 544-549 - Ying Zhang, Robert P. Dick, Krishnendu Chakrabarty:
Energy-aware deterministic fault tolerance in distributed real-time embedded systems. 550-555 - Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta:
Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices. 556-561 - Xiaoping Hu, Radu Marculescu:
Adaptive data partitioning for ambient multimedia. 562-565