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ORCIDDATE 2010: Dresden, Germany
- Giovanni De Micheli, Bashir M. Al-Hashimi, Wolfgang Müller, Enrico Macii:
Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010. IEEE Computer Society 2010, ISBN 978-1-4244-7054-9
Keynote Addresses
- Alberto L. Sangiovanni-Vincentelli:
All things are connected. 1 - Hermann Eul:
Wireless communication - successful differentiation on standard technology by innovation. 2
Embedded Tutorial - Embedded Systems and their Physical Environment - The 'Cyberphysical' View
- Albert Benveniste:
Loosely Time-Triggered Architectures for Cyber-Physical Systems. 3-8
Power-Aware Technique for Real-Time Systems
- Chuan-Yue Yang, Jian-Jia Chen, Lothar Thiele, Tei-Wei Kuo
:
Energy-efficient real-time task scheduling with temperature-dependent leakage. 9-14 - Sandro Penolazzi, Ingo Sander, Ahmed Hemani:
Predicting energy and performance overhead of Real-Time Operating Systems. 15-20 - Min Bao, Alexandru Andrei, Petru Eles, Zebo Peng:
Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling. 21-26
System Level Design of Multicores
- Ramakrishna Vadlamani, Jia Zhao, Wayne P. Burleson, Russell Tessier:
Multicore soft error rate stabilization using adaptive dual modular redundancy. 27-32 - Yvain Thonnart, Pascal Vivet, Fabien Clermidy:
A fully-asynchronous low-power framework for GALS NoC integration. 33-38 - Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen:
Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller. 39-44 - Sergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Rostagno, Maurizio Zamboni:
MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture. 45-50
Reliability, Simulation, Yield and Enhancement
- Lin Huang, Qiang Xu:
AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs. 51-56 - Paul Zuber, Miguel Miranda, Petr Dobrovolný, Koen van der Zanden, Jong-Hoon Jung:
Statistical SRAM analysis for yield enhancement. 57-62 - Mingjing Chen, Alex Orailoglu:
Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme. 63-68 - Sheng Yang, Bashir M. Al-Hashimi, David Flynn, S. Saqib Khursheed:
Scan based methodology for reliable state retention power gating designs. 69-74
Advances in Embedded Software Development
- Wolfgang Ecker, Volkan Esen, Robert Schwencker, Thomas Steininger, Michael Velten:
TLM+ modeling of embedded HW/SW systems. 75-80 - Matthias Traub, Thilo Streichert, Oleg Krasovytskyy, Jürgen Becker:
Scenario extraction for a refined timing-analysis of automotive network topologies. 81-86 - Kebin Zeng, Yu Guo, Christo Angelov:
Graphical Model Debugger Framework for embedded systems. 87-92 - Shuai Mu, Xinya Zhang, Nairen Zhang, Jiaxin Lu, Yangdong Steve Deng, Shu Zhang:
IP routing processing with graphic processors. 93-98
Memory Stacking and Cooling Solutions
- Igor Loi, Luca Benini:
An efficient distributed memory interface for many-core platform with 3D stacked DRAM. 99-104 - Andrea Marongiu, Martino Ruggiero, Luca Benini:
Efficient OpenMP data mapping for multicore platforms with vertically stacked memory. 105-110 - Ayse K. Coskun, David Atienza, Tajana Simunic Rosing, Thomas Brunschwiler, Bruno Michel:
Energy-efficient variable-flow liquid cooling in 3D stacked architectures. 111-116 - Jieyi Long, Seda Ogrenci Memik, Matthew Grayson:
Optimization of an on-chip active cooling system based on thin-film thermoelectric coolers. 117-122
Panel
- Bryon Moyer, Joachim Kunkel, John Cornish, Chris Rowen, Eshel Haritan, Yankin Tanurhan:
Are we there yet? Has IP block assembly become as easy as LEGO? 123
Green and Emerging Technologies for Low Power
- Ehsan Pakbaznia, Mohammad Ghasemazar, Massoud Pedram:
Temperature-aware dynamic resource provisioning in a power-optimized datacenter. 124-129 - Michael B. Henry, Leyla Nazhandali:
From transistors to MEMS: Throughput-aware power gating in CMOS circuits. 130-135 - Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun, Naehyuck Chang, Yuan Xie:
Energy- and endurance-aware design of phase change memory caches. 136-141 - Mustafa Imran Ali, Bashir M. Al-Hashimi, Joaquín Recas, David Atienza:
Evaluation and design exploration of solar harvested-energy prediction algorithm. 142-147
Game-Changing Technologies for System Des
- Yiran Chen, Hai Li, Xiaobin Wang, Wenzhong Zhu, Wei Xu, Tong Zhang:
A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM). 148-153 - Tsung-Ching Huang, Kenjiro Fukuda, Chun-Ming Lo, Yung-Hui Yeh, Tsuyoshi Sekitani, Takao Someya, Kwang-Ting Cheng:
Pseudo-CMOS: A novel design style for flexible electronics. 154-159 - Héctor J. García, Igor L. Markov:
Spinto: High-performance energy minimization in spin glasses. 160-165 - Ang-Chih Hsieh, TingTing Hwang, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li:
TSV redundancy: Architecture and design issues in 3D IC. 166-171
Application Development for Multicores
- Aditi Rathi, Michael DeBole, Weina Ge, Robert T. Collins, Narayanan Vijaykrishnan:
A GPU based implementation of Center-Surround Distribution Distance for feature extraction and matching. 172-177 - R. Grottesi, Serena Morigi, Martino Ruggiero, Luca Benini:
Parallel subdivision surface rendering and animation on the Cell BE processor. 178-183 - Camille Jalier, Didier Lattard, Ahmed Amine Jerraya, Gilles Sassatelli, Pascal Benoit, Lionel Torres:
Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem. 184-189 - Rebecca L. Collins, Bharadwaj Vellore, Luca P. Carloni:
Recursion-driven parallel code generation for multi-core platforms. 190-195 - Giovanni Mariani, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria:
An industrial design space exploration framework for supporting run-time resource management on multi-core systems. 196-201
Advanced System Chip Testing
- A. M. Majid, David C. Keezer:
Stretching the limits of FPGA SerDes for enhanced ATE performance. 202-207 - Zhiyuan He, Zebo Peng, Petru Eles:
Multi-temperature testing for core-based system-on-chip. 208-213 - Ad J. van de Goor, Georgi Gaydadjiev, Said Hamdioui:
Memory testing with a RISC microcontroller. 214-219
Real-Time Scheduling in Embedded Systems
- Alejandro Masrur, Samarjit Chakraborty, Georg Färber:
Constant-time admission control for Deadline Monotonic tasks. 220-225 - Jonas Rox, Rolf Ernst:
Exploiting inter-event stream correlations between output event streams of non-preemptively scheduled tasks. 226-231 - Hessam Kooti, Elaheh Bozorgzadeh, Shenghui Liao, Lichun Bao:
Transition-aware real-time task scheduling for reconfigurable embedded systems. 232-237
Architectural Techniques for Robust Design
- Songjun Pan, Yu Hu, Xiaowei Li:
IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults. 238-243 - Hamed F. Dadgour, Kaustav Banerjee:
Aging-resilient design of pipelined architectures using novel detection and correction circuits. 244-249 - Omid Azizi, Aqeel Mahesri, John P. Stevenson, Sanjay J. Patel, Mark Horowitz:
An integrated framework for joint design space exploration of microarchitecture and circuits. 250-255
HOT TOPIC - AUTOSAR and Automotive Software Design
- Simon Fürst:
Challenges in the design of automotive software. 256-258 - Stefan Voget:
AUTOSAR and the automotive tool chain. 259-262 - Dirk Diekhoff:
AUTOSAR basic software for complex control units. 263-266
Interactive Presentations
- Jing Cao, Albert Nymeyer:
High-fidelity markovian power model for protocols. 267-270 - Arpad Gellert, Gianluca Palermo, Vittorio Zaccaria, Adrian Florea, Lucian N. Vintan, Cristina Silvano:
Energy-performance design space exploration in SMT architectures exploiting selective load value predictions. 271-274 - Vladimir Pasca, Lorena Anghel, Claudia Rusu, Riccardo Locatelli, Massimo Coppola:
Error resilience of intra-die and inter-die communication with 3D spidergon STNoC. 275-278 - Muhammad Bashir, Linda S. Milor:
Towards a chip level reliability simulator for copper/low-k backend processes. 279-282 - Seyab, Said Hamdioui:
NBTI modeling in the framework of temperature variation. 283-286 - Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Tay-Jyi Lin:
RunAssert: A non-intrusive run-time assertion for parallel programs debugging. 287-290 - Marco Facchini, Paul Marchal, Francky Catthoor, Wim Dehaene:
An RDL-configurable 3D memory tier to replace on-chip SRAM. 291-294 - Raid Zuhair Ayoub, Shervin Sharifi, Tajana Simunic Rosing:
GentleCool: Cooling aware proactive workload scheduling in multi-machine systems. 295-298 - Niklas Lotze, Jacob Göppert, Yiannos Manoli:
Timing modeling for digital sub-threshold circuits. 299-302 - M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli:
Power consumption of logic circuits in ambipolar carbon nanotube technology. 303-306 - Min Li, Yexin Zheng, Michael S. Hsiao, Chao Huang:
Reversible logic synthesis through ant colony optimization. 307-310 - Prateek Mishra, Niraj K. Jha:
Low-power FinFET circuit synthesis using surface orientation optimization. 311-314 - Kalyana C. Bollapalli, Sunil P. Khatri, Laszlo B. Kish:
Implementing digital logic with sinusoidal supplies. 315-318 - Antonino Tumeo, Francesco Regazzoni, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto:
A reconfigurable multiprocessor architecture for a reliable face recognition implementation. 319-322 - Alexander Krupp, Wolfgang Müller:
A systematic approach to the test of combined HW/SW systems. 323-326 - Steffen Ostendorff, Heinz-Dietrich Wuttke, Jörg Sachße, S. Köhler:
A new approach for adaptive failure diagnostics based on emulation test. 327-330 - Karthik Lakshmanan, Gaurav Bhatia, Ragunathan Rajkumar:
Integrated end-to-end timing analysis of networked AUTOSAR-compliant systems. 331-334 - Sriram Narayanan, John Sartori, Rakesh Kumar, Douglas L. Jones:
Scalable stochastic processors. 335-338
Variability Aware Low Power Design
- Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici:
AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics. 339-344 - Vikas Chandra, Cezary Pietrzyk, Robert C. Aitken:
On the efficacy of write-assist techniques in low voltage nanoscale SRAMs. 345-350 - Hwisung Jung, Massoud Pedram:
Optimizing the power delivery network in dynamically voltage scaled systems with uncertain power mode transition times. 351-356
Performance Estimation and Runtime Management of MPSoCs
- Timon D. ter Braak, Philip K. F. Hölzenspies, Jan Kuper, Johann L. Hurink, Gerard J. M. Smit:
Run-time spatial resource management for real-time applications on heterogeneous MPSoCs. 357-362 - Haris Javaid, Andhi Janapsatya, Mohammad Shihabul Haque, Sri Parameswaran:
Rapid runtime estimation methods for pipelined MPSoCs. 363-368 - Jari Kreku, Kari Tiensyrjä, Geert Vanmeerbeeck:
Automatic workload generation for system-level exploration based on modified GCC compiler. 369-374
Application of Reconfigurable and Adaptive Systems
- Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich:
A rapid prototyping system for error-resilient multi-processor systems-on-chip. 375-380 - Jih-Sheng Shen, Chun-Hsian Huang, Pao-Ann Hsiung:
Learning-based adaptation to applications and environments in a reconfigurable Network-on-Chip. 381-386 - Sean Whitty, Henning Sahlbach, Brady Hurlburt, Rolf Ernst, Wolfram Putzke-Röming:
Application-specific memory performance of a heterogeneous reconfigurable architecture. 387-392 - Abdulkadir Akin, Gokhan Sayilar, Ilker Hamzaoglu:
A reconfigurable hardware for one bit transform based multiple reference frame Motion Estimation. 393-398 - Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu:
Ultra-high throughput string matching for Deep Packet Inspection. 399-404 - Juan Fernando Eusse Giraldo, Nahri Moreano, Ricardo Pezzuol Jacobi, Alba Cristina Magalhaes Alves de Melo:
A HMMER hardware accelerator using divergences. 405-410
Wearout and Process Variation Mitigation and Modelling
- Lin Li, Youtao Zhang, Jun Yang, Jianhua Zhao:
Proactive NBTI mitigation for busy functional units in out-of-order microprocessors. 411-416 - Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio:
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability. 417-422 - Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken:
Analytical model for TDDB-based performance degradation in combinational logic. 423-428 - Bartomeu Alorda, Gabriel Torrens, Sebastià A. Bota, Jaume Segura:
Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs. 429-434
Model Based Design of Embedded Systems
- Alexander Michailidis, Uwe Spieth, Thomas Ringler, Bernd Hedenetz, Stefan Kowalewski:
Test front loading in early stages of automotive software development based on AUTOSAR. 435-440 - Purandar Bhaduri, Ingo Stierand:
A proposal for real-time interfaces in SPEEDS. 441-446 - Kim Guldstrand Larsen, Shuhao Li, Brian Nielsen, Saulius Pusinskas:
Scenario-based analysis and synthesis of real-time systems using uppaal. 447-452
Extraction and Model Order Reduction
- Tarek A. El-Moselhy, Luca Daniel:
Variation-aware interconnect extraction using statistical moment preserving model order reduction. 453-458 - Navin Srivastava, Roberto Suaya, Kaustav Banerjee:
Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. 459-464 - Jorge Fernandez Villena, Luís Miguel Silveira:
HORUS - high-dimensional Model Order Reduction via low moment-matching upgraded sampling. 465-470 - Maria V. Ugryumova, Wil H. A. Schilders:
On passivity of the super node algorithm for EM modeling of interconnect systems. 471-476
Panel
- Gerhard P. Fettweis:
The road to energy-efficient systems: From hardware-driven to software-defined. 477
Automating Verification with Simulation, Properties and Assertions
- Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli:
Vacuity analysis for property qualification by mutation of checkers. 478-483 - Tao Zhang, Tao Lv, Xiaowei Li:
An abstraction-guided simulation approach using Markov models for microprocessor verification. 484-489 - Mingsong Chen, Xiaoke Qin, Prabhat Mishra:
Efficient decision ordering techniques for SAT-based test generation. 490-495 - Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran:
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. 496-501
Power Optimization and Estimation for Flash and CMOS Technologies
- Vidyabhushan Mohan, Sudhanva Gurumurthi, Mircea R. Stan:
FlashPower: A detailed power model for NAND flash memory. 502-507 - Wei Gao, Richard Hornsey:
A power optimization method for CMOS Op-Amps using sub-space based geometric programming. 508-513 - Sin-Yu Chen, Rung-Bin Lin, Hui-Hsiang Tung, Kuen-Wey Lin:
Power gating design for standard-cell-like structured ASICs. 514-519 - Meng Tie, Haiying Dong, Tong Wang, Xu Cheng:
Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement. 520-525
Automotive Systems: Mastering Complexity and Uncertainty
- Luca Fanucci, Giuseppe Pasetti, Paolo D'Abramo, Riccardo Serventi, Francesco Tinfena, Pierre Chassard, L. Labiste, Pierre Tisserand:
An high voltage CMOS voltage regulator for automotive alternators with programmable functionalities and full reverse polarity capability. 526-531 - Matthias Müller, Axel G. Braun, Joachim Gerlach, Wolfgang Rosenstiel, Dennis Nienhüser, Johann Marius Zöllner, Oliver Bringmann:
Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation. 532-537 - Andreas Braun, Oliver Bringmann, Djones Lettnin, Wolfgang Rosenstiel:
Simulation-based verification of the MOST NetInterface specification revision 3.0. 538-543 - Michael Karner, Eric Armengaud, Christian Steger, Reinhold Weiss:
Holistic simulation of FlexRay networks by using run-time model switching. 544-549 - Arkadeb Ghosal, Haibo Zeng, Marco Di Natale, Yakov Ben-Haim:
Computing robustness of FlexRay schedules to uncertainties in design parameters. 550-555
Embedded Tutorial - Adaptive Testing
- Erik Jan Marinissen, Adit D. Singh, Dan Glotter, Marco Esposito, John M. Carulli Jr., Amit Nahar, Kenneth M. Butler, Davide Appello, Chris Portelli:
Adapting to adaptive testing. 556-561
Virtualization Technologies
- Ernest Artiaga, Toni Cortes:
Using filesystem virtualization to avoid metadata bottlenecks. 562-567 - Zhe-Mao Hsu, Jen-Chieh Yeh, I-Yao Chuang:
An accurate system architecture refinement methodology with mixed abstraction-level virtual platform. 568-573 - Matthias Bolte, Michael Sievers, Georg Birkenheuer, Oliver Niehörster, André Brinkmann:
Non-intrusive virtualization management using libvirt. 574-579
Variability Reliability and Thermal Trade-Offs for Low-Power Design
- Cheng Zhuo, Dennis Sylvester, David T. Blaauw:
Process variation and temperature-aware reliability management. 580-585 - Evelyn Mintarno, Joëlle Skaf, Rui Zheng, Jyothi Velamala, Yu Cao, Stephen P. Boyd, Robert W. Dutton, Subhasish Mitra:
Optimized self-tuning for circuit aging. 586-591 - Andrew J. Ricketts, Jawar Singh, Krishnan Ramakrishnan, Narayanan Vijaykrishnan, Dhiraj K. Pradhan:
Investigating the impact of NBTI on different power saving cache strategies. 592-597
Interactive Presentations
- Wang Huan, Zhang Yang, Mei Chen, Ling Ming:
Energy-oriented dynamic SPM allocation based on time-slotted Cache conflict graph. 598-601 - Wei Liu, Ying Tan, Qinru Qiu:
Enhanced Q-learning algorithm for dynamic power management with performance constraint. 602-605 - Aline Mello, Isaac Maia, Alain Greiner, François Pêcheux:
Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations. 606-609 - István Haller, Zoltan Francisc Baruch:
High-speed clock recovery for low-cost FPGAs. 610-613 - Uwe Proß, Sebastian Goller, Erik Markert, Michael Jüttner, Jan Langer, Ulrich Heinkel, Joachim Knäblein, Axel Schneider:
Demonstration of an in-band reconfiguration data distribution and network node reconfiguration. 614-617 - Julio César Vázquez, Víctor H. Champac, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira:
Programmable aging sensor for automotive safety-critical applications. 618-621