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ORCIDDATE 2014: Dresden, Germany
- Gerhard P. Fettweis, Wolfgang Nebel:
Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014. European Design and Automation Association 2014, ISBN 978-3-9815370-2-4 - Mohamed M. Sabry, Arvind Sridhar, David Atienza, Patrick W. Ruch, Bruno Michel:
Integrated microfluidic power generation and cooling for bright silicon MPSoCs. 1-6 - Baris Aksanli
, Tajana Rosing:
Providing regulation services and managing data center peak power budgets. 1-4 - Alexander Biewer, Jens Gladigau, Christian Haubelt:
A novel model for system-level decision making with combined ASP and SMT solving. 1-4 - Luis Gabriel Murillo, Simon Wawroschek, Jerónimo Castrillón, Rainer Leupers, Gerd Ascheid:
Automatic detection of concurrency bugs through event ordering constraints. 1-6 - Samantak Gangopadhyay, Youngtak Lee, Saad Bin Nasir, Arijit Raychowdhury:
Modeling and analysis of digital linear dropout regulators with adaptive control for high efficiency under wide dynamic range digital loads. 1-6 - Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
An efficient manipulation package for Biconditional Binary Decision Diagrams. 1-6 - Doohwang Chang, Sule Ozev, Ozgur Sinanoglu, Ramesh Karri:
Approximating the age of RF/analog circuits through re-characterization and statistical estimation. 1-4 - Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh:
Leakage-power-aware clock period minimization. 1-6 - Vikas Chandra, Subhasish Mitra, Chen-Yong Cher, Silvia Melitta Müller:
Cross layer resiliency in real world. 1 - M. Vijaykumar, V. Vasudevan:
Statistical static timing analysis using a skew-normal canonical delay model. 1-6 - Amitabha Roy, Timothy M. Jones:
ALLARM: Optimizing sparse directories for thread-local data. 1-6 - Dominik Erb, Karsten Scheibler, Matthias Sauer, Bernd Becker:
Efficient SMT-based ATPG for interconnect open defects. 1-6 - Leonardo Arturo Bautista-Gomez, Franck Cappello, Luigi Carro, Nathan DeBardeleben, Bo Fang, Sudhanva Gurumurthi, Karthik Pattabiraman, Paolo Rech, Matteo Sonza Reorda:
GPGPUs: How to combine high computational power with high reliability. 1-9 - Shrikanth Ganapathy, Ramon Canal, Dan Alexandrescu, Enrico Costenaro, Antonio González, Antonio Rubio:
INFORMER: An integrated framework for early-stage memory robustness analysis. 1-4 - Arslan Munir, Farinaz Koushanfar:
D2Cyber: A design automation tool for dependable cybercars. 1-4 - Christos Ttofis, Theocharis Theocharides:
High-quality real-time hardware stereo matching based on guided image filtering. 1-6 - Filippo Casamassima, Elisabetta Farella, Luca Benini:
Context aware power management for motion-sensing body area network nodes. 1-6 - Tariq B. Ahmad, Maciej J. Ciesielski:
Fast STA prediction-based gate-level timing simulation. 1-6 - Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi:
An adaptive Memory Interface Controller for improving bandwidth utilization of hybrid and reconfigurable systems. 1-4 - Kai Cong, Li Lei, Zhenkun Yang, Fei Xie:
Coverage evaluation of post-silicon validation tests with virtual prototypes. 1-6 - Rubén Braojos, Ahmed Yasir Dogan, Ivan Beretta, Giovanni Ansaloni, David Atienza:
Hardware/software approach for code synchronization in low-power multi-core sensor nodes. 1-6 - Mehdi Kamal, Amin Ghasemazar, Ali Afzali-Kusha, Massoud Pedram:
Improving efficiency of extensible processors by using approximate custom instructions. 1-4 - Ophir Friedler, Wisam Kadry, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin:
Effective post-silicon failure localization using dynamic program slicing. 1-6 - Paolo Burgio, Robin Danilo, Andrea Marongiu, Philippe Coussy, Luca Benini:
A tightly-coupled hardware controller to improve scalability and programmability of shared-memory heterogeneous clusters. 1-4 - Matthias Boettcher, Bashir M. Al-Hashimi, Mbou Eyole, Giacomo Gabrielli, Alastair Reid:
Advanced SIMD: Extending the reach of contemporary SIMD architectures. 1-4 - Brandon Del Bel, Jongyeon Kim, Chris H. Kim, Sachin S. Sapatnekar:
Improving STT-MRAM density through multibit error correction. 1-6 - Alex Iliasov, Arseniy Alekseyev, Danil Sokolov, Andrey Mokhov:
Design of safety critical systems by refinement. 1-4 - Yanzhi Wang, Xue Lin, Qing Xie, Naehyuck Chang, Massoud Pedram:
Minimizing state-of-health degradation in hybrid electrical energy storage systems with arbitrary source and load profiles. 1-4 - Valentin Mena Morales, Pierre-Henri Horrein, Amer Baghdadi, Erik Hochapfel, Sandrine Vaton:
Energy-efficient FPGA implementation for binomial option pricing using OpenCL. 1-6 - Mehrzad Nejat, Bijan Alizadeh, Ali Afzali-Kusha:
Dynamic Flip-Flop conversion to tolerate process variation in low power circuits. 1-4 - Matthias Kauer, Damoon Soudbakhsh, Dip Goswami, Samarjit Chakraborty, Anuradha M. Annaswamy:
Fault-tolerant control synthesis and verification of distributed embedded systems. 1-6 - Vijaykrishnan Narayanan, Suman Datta, Gert Cauwenberghs, Donald M. Chiarulli, Steven P. Levitan, H.-S. Philip Wong:
Video analytics using beyond CMOS devices. 1-5 - Clemens Helfmeier, Christian Boit, Dmitry Nedospasov, Shahin Tajik, Jean-Pierre Seifert:
Physical vulnerabilities of Physically Unclonable Functions. 1-4 - Maximilian Odendahl, Andres Goens, Rainer Leupers, Gerd Ascheid, Benjamin Ries, Berthold Vöcking, Tomas Henriksson:
Optimized buffer allocation in multicore platforms. 1-6 - Matthias Hiller, Georg Sigl:
Increasing the efficiency of syndrome coding for PUFs with helper data compression. 1-6 - Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors:
Reducing set-associative L1 data cache energy by early load data dependence detection (ELD3). 1-4 - Xiaohang Wang, Baoxin Zhao, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi:
Adaptive power allocation for many-core systems inspired from multiagent auction model. 1-4 - Yier Jin, Dean Sullivan:
Real-time trust evaluation in integrated circuits. 1-6 - Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang:
A fault detection mechanism in a Data-flow scheduled Multithreaded processor. 1-4 - Andrew Becker, David Novo, Paolo Ienne:
SKETCHILOG: Sketching combinational circuits. 1-4 - Manil Dev Gomony, Benny Akesson, Kees Goossens:
Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems. 1-6 - Ulrich Rührmair, Daniel E. Holcomb:
PUFs at a glance. 1-6 - Zoran Jaksic, Ramon Canal:
DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy. 1-4 - Jinbo Wan, Hans G. Kerkhoff:
An embedded offset and gain instrument for OpAmp IPs. 1-4 - Anup Das, Akash Kumar, Bharadwaj Veeravalli:
Temperature aware energy-reliability trade-offs for mapping of throughput-constrained applications on multimedia MPSoCs. 1-6 - Adam Zygmontowicz, Jennifer Dworak, Al Crouch, John C. Potter:
Making it harder to unlock an LSIB: Honeytraps and misdirection in a P1687 network. 1-6 - Bao Liu, Brandon Wang:
Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks. 1-6 - Maurizio Rossi, Alessandro Toppano, Davide Brunelli:
Real-time optimization of the battery banks lifetime in Hybrid Residential Electrical Systems. 1-6 - Dmitry Burlyaev, Pascal Fradet, Alain Girault:
Verification-guided voter minimization in triple-modular redundant circuits. 1-6 - Georgios Keramidas, Michail Mavropoulos, Anna Karvouniari, Dimitris Nikolos:
Spatial pattern prediction based management of faulty data caches. 1-6 - Milovan Duric, Oscar Palomar, Aaron Smith, Osman S. Unsal, Adrián Cristal, Mateo Valero, Doug Burger:
EVX: Vector execution on low power EDGE cores. 1-4 - Oliver Sander, Timo Sandmann, Viet Vu Duy, Steffen Bähr, Falco Bapp, Jürgen Becker, Hans-Ulrich Michel, Dirk Kaule, Daniel Adam, Enno Lübbers, Jürgen Hairbucher, Andre Oliver Richter, Christian Herber, Andreas Herkersdorf:
Hardware virtualization support for shared resources in mixed-criticality multicore systems. 1-6 - Mahmoud Zangeneh, Ajay Joshi:
Sub-threshold logic circuit design using feedback equalization. 1-6 - Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li:
Functional test generation guided by steady-state probabilities of abstract design. 1-4 - Lorenzo Zuolo, Cristian Zambelli, Rino Micheloni, Salvatore Galfano, Marco Indaco, Stefano Di Carlo, Paolo Prinetto, Piero Olivo, Davide Bertozzi:
SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives. 1-6 - Enrico Macrelli, Ningning Wang, Saibal Roy, Michael Hayes, Rudi Paolo Paganelli, Marco Tartagni, Aldo Romani:
Design and fabrication of a 315 μΗ bondwire micro-transformer for ultra-low voltage energy harvesting. 1-4 - Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori:
Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM. 1-6 - Amit Ranjan Trivedi, Mohammad Faisal Amir, Saibal Mukhopadhyay:
Ultra-low power electronics with Si/Ge tunnel FET. 1-6 - Alexander Kordes, Bart Vermeulen, Abhijit K. Deb, Michael G. Wahl:
Startup error detection and containment to improve the robustness of hybrid FlexRay networks. 1-6 - Delong Shang, Xuefu Zhang, Fei Xia, Alex Yakovlev:
Asynchronous design for new on-chip wide dynamic range power electronics. 1-6 - Ahmed Alhammad, Rodolfo Pellizzoni:
Time-predictable execution of multithreaded applications on multicore systems. 1-6 - Xue-Yang Zhu, Marc Geilen, Twan Basten, Sander Stuijk:
Memory-constrained static rate-optimal scheduling of synchronous dataflow graphs via retiming. 1-6 - Andrew B. Kahng, Ilgweon Kang:
Co-optimization of memory BIST grouping, test scheduling, and logic placement. 1-6 - Ogun Turkyilmaz, Gerald Cibrario, Olivier Rozeau, Perrine Batude, Fabien Clermidy:
3D FPGA using high-density interconnect Monolithic Integration. 1-4 - Gang Han, Haibo Zeng, Yaping Li, Wenhua Dou:
SAFE: Security-Aware FlexRay Scheduling Engine. 1-4 - Yu Pu, Juan Diego Echeverri, Maurice Meijer, José Pineda de Gyvez:
Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling. 1-2 - Waleed Dweik, Murali Annavaram, Michel Dubois:
Reliability-Aware Exceptions: Tolerating intermittent faults in microprocessor array structures. 1-6 - Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang:
Metal layer planning for silicon interposers with consideration of routability and manufacturing cost. 1-6 - Mojtaba Ebrahimi, Adrian Evans, Mehdi Baradaran Tahoori, Razi Seyyedi, Enrico Costenaro, Dan Alexandrescu:
Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales. 1-6 - Mafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di Natale:
Testing PUF-based secure key storage circuits. 1-6 - Heba Khdr, Thomas Ebi, Muhammad Shafique, Hussam Amrouch, Jörg Henkel:
mDTM: Multi-objective dynamic thermal management for on-chip systems. 1-6 - C. Katzschke, M.-P. Sohn, Markus Olbrich, Volker Meyer zu Bexten, Markus Tristl, Erich Barke:
Application of Mission Profiles to enable cross-domain constraint-driven design. 1-6 - Shuang Chen, Yanzhi Wang, Massoud Pedram:
Concurrent placement, capacity provisioning, and request flow control for a distributed cloud infrastructure. 1-6 - Zhengfeng Huang:
A high performance SEU-tolerant latch for nanoscale CMOS technology. 1-5 - Yuhao Wang, Hao Yu, Dennis Sylvester, Pingfan Kong:
Energy efficient in-memory AES encryption based on nonvolatile domain-wall nanowire. 1-4 - Caio Hoffman, Luiz Ramos, Rodolfo Azevedo, Guido Araujo:
Wear-out analysis of Error Correction Techniques in Phase-Change Memory. 1-4 - Shaoteng Liu, Axel Jantsch, Zhonghai Lu:
Parallel probe based dynamic connection setup in TDM NoCs. 1-6 - Saman Kiamehr, Farshad Firouzi, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
Aging-aware standard cell library design. 1-4 - Seung-Soo Han, Andrew B. Kahng, Siddhartha Nath, Ashok S. Vydyanathan:
A deep learning methodology to proliferate golden signoff timing. 1-6 - Ute Zschieschang, Reinhold Rodel, Ulrike Kraft, Kazuo Takimiya, Tarek Zaki, Florian Letzkus, Joerg Butschke, Harald Richter, Joachim N. Burghartz, Wei Xiong, Boris Murmann, Hagen Klauk:
Low-voltage organic transistors for flexible electronics. 1-6 - Kenneth Balck, Olga Grinchtein, Justin Pearson:
Model-based protocol log generation for testing a telecommunication test harness using CLP. 1-4 - Michael E. Imhof, Hans-Joachim Wunderlich:
Bit-Flipping Scan - A unified architecture for fault tolerance and offline test. 1-6 - A. Ubolli, Stefano Grivet-Talocia, M. Bandinu, Alessandro Chinea:
Sensitivity-based weighting for passivity enforcement of linear macromodels in power integrity applications. 1-6 - Chuansheng Dong, Haibo Zeng:
Minimizing stack memory for hard real-time applications on multicore platforms. 1-6 - Hsun-Cheng Lee, Jacob A. Abraham:
A novel low power 11-bit hybrid ADC using flash and delay line architectures. 1-4 - Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo:
Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems. 1-4 - Santanu Sarma, Nikil D. Dutt:
Minimal sparse observability of complex networks: Application to MPSoC sensor placement and run-time thermal estimation & tracking. 1-6 - Bing Li, Shuchang Shan, Yu Hu, Xiaowei Li:
Partial-SET: Write speedup of PCM main memory. 1-4 - Alain Fourmigue, Giovanni Beltrame, Gabriela Nicolescu:
Efficient transient thermal simulation of 3D ICs with liquid-cooling and through silicon vias. 1-6 - Dzmitry Maliuk, Yiorgos Makris:
An analog non-volatile neural network platform for prototyping RF BIST solutions. 1-6 - Myungsun Kim, Kibeom Kim, James R. Geraci, Seongsoo Hong:
Utilization-aware load balancing for the energy efficient operation of the big.LITTLE processor. 1-4 - Aurélien Francillon, Quan Nguyen, Kasper Bonne Rasmussen, Gene Tsudik:
A minimalist approach to Remote Attestation. 1-6 - MohammadSadegh Sadri, Matthias Jung, Christian Weis, Norbert Wehn, Luca Benini:
Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh. 1-4 - Hui Guo, Zhenjiang Wang, Chenggang Wu, Ruining He:
EATBit: Effective automated test for binary translation with high code coverage. 1-6 - Jan Henrik Weinstock, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Laura Tosoratto:
Time-decoupled parallel SystemC simulation. 1-4 - Rolf Drechsler, Christophe Chevallaz, Franco Fummi, Alan J. Hu, Ronny Morad, Frank Schirrmeister, Alex Goryachev:
Panel: Future SoC verification methodology: UVM evolution or revolution? 1-5 - Wolfgang Ecker, Michael Velten, Leily Zafari, Ajay Goyal:
The metamodeling approach to system level synthesis. 1-2 - Chuancai Gu, Nan Guan, Qingxu Deng, Wang Yi:
Partitioned mixed-criticality scheduling on multiprocessor platforms. 1-6 - Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang:
Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints. 1-4 - Nils Heidmann, Nico Hellwege, Tim Hohlein, Thomas Westphal, Dagmar Peters-Drolshagen, Steffen Paul:
Modeling of an analog recording system design for ECoG and AP signals. 1-6 - Akramul Azim, Gonzalo Carvajal, Rodolfo Pellizzoni, Sebastian Fischmeister:
Generation of communication schedules for multi-mode distributed real-time applications. 1-6 - Kam-yiu Lam, Jiantao Wang, Yuan-Hao Chang, Jen-Wei Hsieh, Po-Chun Huang, Chung Keung Poon, Chun Jiang Zhu:
Garbage collection for multi-version index on flash memory. 1-4 - Xiaolin Xu, Wayne P. Burleson:
Hybrid side-channel/machine-learning attacks on PUFs: A new threat? 1-6 - Somnath Paul, Robert Karam, Swarup Bhunia, Ruchir Puri:
Energy-efficient hardware acceleration through computing in the memory. 1-6 - Di Zhu, Yanzhi Wang, Naehyuck Chang, Massoud Pedram:
Optimal design and management of a smart residential PV and energy storage system. 1-6 - Sebastian Altmeyer, Robert I. Davis:
On the correctness, optimality and precision of Static Probabilistic Timing Analysis. 1-6 - Yiyu Shi, Hung-Ming Chen:
Memcomputing: The cape of good hope: [Extended special session description]. 1-3 - Wei Wang, Youyou Lu, Jiwu Shu:
p-OFTL: An object-based semantic-aware parallel flash translation layer. 1-6 - Ingo von Maurich, Tim Güneysu:
Lightweight code-based cryptography: QC-MDPC McEliece encryption on reconfigurable devices. 1-6 - Christoph Scholl, Florian Pigorsch, Stefan Disch, Ernst Althaus:
Simple interpolants for linear arithmetic. 1-6 - Ulrich Abelein, Alejandro Cook, Piet Engelke, Michael Glaß, Felix Reimann, Laura Rodríguez Gómez, Thomas Russ, Jürgen Teich, Dominik Ull, Hans-Joachim Wunderlich:
Non-intrusive integration of advanced diagnosis features in automotive E/E-architectures. 1-6 - Patrick Haddad, Yannick Teglia, Florent Bernard, Viktor Fischer:
On the assumption of mutual independence of jitter realizations in P-TRNG stochastic models. 1-6 - Pranav Koundinya, Sandhya Theril, Tao Feng, Varun Prakash, Jiming Bao, Weidong Shi:
Multi resolution touch panel with built-in fingerprint sensing support. 1-6 - Daniel Palomino, Muhammad Shafique, Hussam Amrouch, Altamiro Amadeu Susin, Jörg Henkel:
hevcDTM: Application-driven Dynamic Thermal Management for High Efficiency Video Coding. 1-4 - Semeen Rehman, Florian Kriebel, Muhammad Shafique, Jörg Henkel:
Compiler-driven dynamic reliability management for on-chip systems under variabilities. 1-4 - Javier Jalle, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
Bus designs for time-probabilistic multicore processors. 1-6 - Manish Rana, Ramon Canal:
SSFB: A highly-efficient and scalable simulation reduction technique for SRAM yield analysis. 1-6 - Josep Torrellas:
Extreme-scale computer architecture: Energy efficiency from the ground up‡. 1-5 - Nan Guan, Wang Yi:
General and efficient Response Time Analysis for EDF scheduling. 1-6 - Morteza Gholipour, Ying-Yu Chen, Amit Sangai, Deming Chen:
Highly accurate SPICE-compatible modeling for single- and double-gate GNRFETs with studies on technology scaling. 1-6 - Karthik Swaminathan, Moon Seok Kim, Nandhini Chandramoorthy, Behnam Sedighi, Robert Perricone, Jack Sampson, Vijaykrishnan Narayanan:
Modeling steep slope devices: From circuits to architectures. 1-6 - Benoît Dupont de Dinechin, Duco van Amstel, Marc Poulhiès, Guillaume Lager:
Time-critical computing on a single-chip massively parallel processor. 1-6 - Michael B. Taylor:
A landscape of the new dark silicon design regime. 1 - Wolfgang Büter, Christof Osewold, Daniel Gregorek, Alberto García Ortiz:
DCM: An IP for the autonomous control of optical and electrical reconfigurable NoCs. 1-4 - Levent Aksoy, Paulo F. Flores, José Monteiro:
Optimization of design complexity in time-multiplexed constant multiplications. 1-4 - Di Zhu, Lizhong Chen, Siyu Yue, Massoud Pedram:
Application mapping for express channel-based networks-on-chip. 1-6 - Jae Woong Jeong, Sule Ozev, Shreyas Sen, Vishwanath Natarajan, Mustapha Slamani:
Built-in self-test and characterization of polar transmitter parameters in the loop-back mode. 1-6 - Libo Huang:
Leveraging on-chip networks for efficient prediction on multicore coherence. 1-4 - Cristian Andrades, M. Andrea Rodríguez, Charles C. Chiang:
Signature indexing of design layouts for hotspot detection. 1-6 - Tobias Gemmeke, Mohamed M. Sabry, Jan Stuijt, Praveen Raghavan, Francky Catthoor, David Atienza:
Resolving the memory bottleneck for single supply near-threshold computing. 1-6 - Adarsh Reddy Ashammagari, Hamid Mahmoodi, Houman Homayoun:
Exploiting STT-NV technology for reconfigurable, high performance, low power, and low temperature functional unit design. 1-6 - Karthik Chandrasekar, Sven Goossens, Christian Weis, Martijn Koedam, Benny Akesson, Norbert Wehn, Kees Goossens:
Exploiting expendable process-margins in DRAMs for run-time performance optimization. 1-6 - Qing'an Li, Yanxiang He, Yong Chen, Chun Jason Xue, Nan Jiang, Chao Xu:
A wear-leveling-aware dynamic stack for PCM memory in embedded systems. 1-4 - Yue Zhang, Weisheng Zhao, Jacques-Olivier Klein, Wang Kang, Damien Querlioz, Youguang Zhang, Dafine Ravelosona, Claude Chappert:
Spintronics for low-power computing. 1-6 - Andrew Nelson, Ashkan Beyranvand Nejad, Anca Mariana Molnos, Martijn Koedam, Kees Goossens:
CoMik: A predictable and cycle-accurately composable real-time microkernel. 1-4 - Nektarios Georgios Tsoutsos, Michail Maniatakos:
HEROIC: Homomorphically EncRypted One Instruction Computer. 1-6 - Preethi P. Damodaran, Stefan Wallentowitz, Andreas Herkersdorf:
Distributed cooperative shared last-level caching in tiled multiprocessor system on chip. 1-4 - Dirk Müller, Alejandro Masrur:
The schedulability region of two-level mixed-criticality systems based on EDF-VD. 1-6 - Kaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra:
Brain-inspired computing with spin torque devices. 1-6 - Alexandre Guerre, Jean-Thomas Acquaviva, Yves Lhuillier:
A unified methodology for a fast benchmarking of parallel architecture. 1-4 - Muhammad Usman Karim Khan, Muhammad Shafique, Jörg Henkel:
Software architecture of High Efficiency Video Coding for many-core systems with power-efficient workload balancing. 1-6 - Hayoung Kim, Dongyoung Kim, Jae-Joon Kim, Sungjoo Yoo, Sunggu Lee:
Coarse-grained Bubble Razor to exploit the potential of two-phase transparent latch designs. 1-6 - Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta:
Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures. 1-6 - André Lange, Christoph Sohrmann, Roland Jancke, Joachim Haase, Ingolf Lorenz, Ulf Schlichtmann:
Probabilistic standard cell modeling considering non-Gaussian parameters and correlations. 1-4 - Ulf Schlichtmann, Veit Kleeberger, Jacob A. Abraham, Adrian Evans, Christina Gimmler-Dumont, Michael Glaß, Andreas Herkersdorf, Sani R. Nassif, Norbert Wehn:
Connecting different worlds - Technology abstraction for reliability-aware design and Test. 1-8 - Daniele Bortolotti, Andrea Bartolini, Christian Weis, Davide Rossi, Luca Benini:
Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors. 1-6 - Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan:
Width minimization in the Single-Electron Transistor array synthesis. 1-4 - Engin Afacan, Simge Ay, Francisco V. Fernández, Günhan Dündar, I. Faik Baskaya:
Model based hierarchical optimization strategies for analog design automation. 1-4 - Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Rubin A. Parekhji, Arvind Jain:
Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing. 1-6 - Mottaqiallah Taouil, Mahmoud Masadeh, Said Hamdioui, Erik Jan Marinissen:
Interconnect test for 3D stacked memory-on-logic. 1-6 - Yusuke Matsunaga:
Synthesis algorithm of parallel index generation units. 1-6 - Per Stenström:
Effective resource management towards efficient computing. 1 - BaekGyu Kim, Hyeon I. Hwang, Taejoon Park, Sang Hyuk Son, Insup Lee:
A layered approach for testing timing in the model-based implementation. 1-4 - Shengcheng Wang, Farshad Firouzi, Fabian Oboril, Mehdi Baradaran Tahoori:
P/G TSV planning for IR-drop reduction in 3D-ICs. 1-6 - Rainer Leupers, Norbert Wehn, Marco Roodzant, Johannes Stahl, Luca Fanucci, Albert Cohen, Bernd Janson:
Technology transfer towards Horizon 2020. 1 - Masoud Rostami, James B. Wendt, Miodrag Potkonjak, Farinaz Koushanfar:
Quo vadis, PUF?: Trends and challenges of emerging physical-disorder based security. 1-6 - Chun Zhang, Peng Deng, Hui Geng, Jianming Liu, Qi Zhu, Jinjun Xiong, Yiyu Shi:
MSim: A general cycle accurate simulation platform for memcomputing studies. 1-5 - Kecheng Hao, Sandip Ray, Fei Xie:
Equivalence checking for function pipelining in behavioral synthesis. 1-6 - Thomas Nirmaier, Andreas Burger, Manuel Harrant, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel, Georg Pelz:
Mission profile aware robustness assessment of automotive power devices. 1-6 - Abbas Rahimi, Luca Benini, Rajesh K. Gupta:
Temporal memoization for energy-efficient timing error recovery in GPGPUs. 1-6 - Robert Perricone, Xiaobo Sharon Hu, Joseph Nahas, Michael T. Niemier:
Design of 3D nanomagnetic logic circuits: A full-adder case study. 1-6 - Cristian Ferent, Alex Doboli:
Novel circuit topology synthesis method using circuit feature mining and symbolic comparison. 1-4 - Sebastien Fabrie, Juan Diego Echeverri, Maarten Vertregt, José Pineda de Gyvez:
Standard cell library tuning for variability tolerant designs. 1-6 - Amir Aminifar, Enrico Bini, Petru Eles, Zebo Peng:
Bandwidth-efficient controller-server co-design with stability guarantees. 1-6 - Yu Bai, Klaus Schneider:
Isochronous networks by construction. 1-6 - Shuangyue Zhang, Fan Lin, Chun-Kai Hsu, Kwang-Ting Cheng, Hong Wang:
Joint Virtual Probe: Joint exploration of multiple test items' spatial patterns for efficient silicon characterization and test prediction. 1-6 - Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Jian Zhang, Giovanni De Micheli:
Advanced system on a chip design based on controllable-polarity FETs. 1-6 - Nicodemus Banagaaya, Giuseppe Alì, Wil H. A. Schilders, Caren Tischendorf:
Implicit index-aware model order reduction for RLC/RC networks. 1-6 - Xueqian Zhao, Zhonghai Lu:
Empowering study of delay bound tightness with simulated annealing. 1-6 - Francesco Robino, Johnny Öberg:
From Simulink to NoC-based MPSoC on FPGA. 1-4 - Loïc Zussa, Amine Dehbaoui, Karim Tobich, Jean-Max Dutertre, Philippe Maurine, Ludovic Guillaume-Sage, Jessy Clédière, Assia Tria:
Efficiency of a glitch detector against electromagnetic fault injection. 1-6 - Jungsoo Kim, Mohamed M. Sabry, David Atienza, Kalyan Vaidyanathan, Kenny C. Gross:
Global fan speed control considering non-ideal temperature measurements in enterprise servers. 1-6 - Heinz Schmid, B. M. Borg, Kirsten E. Moselund, Pratyush Das Kanungo, G. Signorello, Siegfried F. Karg, Philipp Mensch, Volker Schmidt, Heike Riel:
III-V semiconductor nanowires for future devices. 1-2 - Luo Sun, Jimson Mathew, Rishad A. Shafik, Dhiraj K. Pradhan, Zhen Li:
A low power and robust carbon nanotube 6T SRAM design with metallic tolerance. 1-4 - Ulrich Rührmair, Jan Sölter:
PUF modeling attacks: An introduction and overview. 1-6 - Ali Ahari, Hossein Asadi, Behnam Khaleghi, Mehdi Baradaran Tahoori:
A power-efficient reconfigurable architecture using PCM configuration technology. 1-6 - Cong Liu, Jie Han, Fabrizio Lombardi:
A low-power, high-performance approximate multiplier with configurable partial error recovery. 1-4 - Paolo Burgio, Giuseppe Tagliavini, Francesco Conti, Andrea Marongiu, Luca Benini:
Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters. 1-6 - Namita Sharma, Preeti Ranjan Panda, Min Li, Prashant Agrawal, Francky Catthoor:
Energy efficient data flow transformation for Givens Rotation based QR Decomposition. 1-4 - Andreas Richter, Andreas Voigt, René Schüffny, Stephan Henker, Marcus Völp:
Integrated circuits processing chemical information: Prospects and challenges. 1 - Yuankai Chen, Xuan Zeng, Hai Zhou:
Recovery-based resilient latency-insensitive systems. 1-6 - Biswabandan Panda, Shankar Balachandran:
Introducing Thread Criticality awareness in Prefetcher Aggressiveness Control. 1-6 - Hao Shen, Qiuwen Chen, Qinru Qiu:
Battery aware stochastic QoS boosting in mobile computing devices. 1-4 - Emanuel Dogaru, Filipe Vinci dos Santos, William Rebernak:
A flexible BIST strategy for SDR transmitters. 1-6 - Goeran Jerke, Andrew B. Kahng:
Mission profile aware IC design - A case study. 1-6 - Chang-Hong Hsu, Debapriya Chatterjee, Ronny Morad, Raviv Gal, Valeria Bertacco:
ArChiVED: Architectural checking via event digests for high performance validation. 1-6 - Franco Fummi, Michele Lora, Francesco Stefanni, Dimitrios Trachanis, Jahn Vanhese, Sara Vinco:
Moving from co-simulation to simulation for effective smart systems design. 1-4 - Faisal Alam, Preeti Ranjan Panda, Nikhil Tripathi, Namita Sharma, Sanjiv Narayan:
Energy optimization in Android applications through wakelock placement. 1-4 - Heng Yu, Rizwan Syed, Yajun Ha:
Thermal-aware frequency scaling for adaptive workloads on heterogeneous MPSoCs. 1-6 - Christian Zebelein, Christian Haubelt, Joachim Falk, Tobias Schwarzer, Jürgen Teich:
Model-based actor multiplexing with application to complex communication protocols. 1-4 - Andrea Bartolini, Matteo Cacciari, Carlo Cavazzoni, Giampietro Tecchiolli, Luca Benini:
Unveiling Eurora - Thermal and power characterization of the most energy-efficient supercomputer in the world. 1-6 - Tanguy Sassolas, Chiara Sandionigi, Alexandre Guerre, Alexandre Aminot, Pascal Vivet, Hela Boussetta, Luca Ferro, Nicolas Peltier:
Early design stage thermal evaluation and mitigation: The locomotiv architectural case. 1-2 - Antonis Nikitakis, Theofilos Paganos, Ioannis Papaefstathiou:
A novel embedded system for vision tracking. 1-4 - I. Seitanidis, Anastasios Psarras, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos:
ElastiStore: An elastic buffer architecture for Network-on-Chip routers. 1-6 - Pilin Junsangsri, Fabrizio Lombardi, Jie Han:
A hybrid non-volatile SRAM cell with concurrent SEU detection and correction. 1-4 - Giovanni Mariani, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano:
DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling. 1-4 - Mohammad D. Mottaghi, Arjun Rallapalli, Chris Dwyer:
RETLab: A fast design-automation framework for arbitrary RET networks. 1-6 - Jan Nowotsch, Michael Paulitsch, Arne Henrichsen, Werner Pongratz, Andreas Schacht:
Monitoring and WCET analysis in COTS multi-core-SoC-based mixed-criticality systems. 1-5 - Haroon Mahmood, Massimo Poncino, Enrico Macii:
Cache aging reduction with improved performance using dynamically re-sizable cache. 1-6 - Sofiane Lagraa, Alexandre Termier, Frédéric Pétrot:
Scalability bottlenecks discovery in MPSoC platforms using data mining on simulation traces. 1-6 - Gnaneswara Rao Jonna, John Jose, Rachana Radhakrishnan, Madhu Mutyam:
Minimally buffered single-cycle deflection router. 1-4 - Eunhyuk Park, Sungjoo Yoo, Sunggu Lee, Hai Helen Li:
Accelerating graph computation with racetrack memory and pointer-assisted graph representation. 1-4 - Indranil Palit, Behnam Sedighi, András Horváth, Xiaobo Sharon Hu, Joseph Nahas, Michael T. Niemier:
Impact of steep-slope transistors on non-von Neumann architectures: CNN case study. 1-6 - Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano:
Low-latency wireless 3D NoCs via randomized shortcut chips. 1-6 - Armin Alaghi, John P. Hayes:
Fast and accurate computation using stochastic circuits. 1-4 - Yu-Guang Chen, Kuan-Yu Lai, Ming-Chao Lee, Yiyu Shi, Wing-Kai Hon, Shih-Chieh Chang:
Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits. 1-4 - Xuemeng Zhang, Hui Wu, Haiyan Sun, Jingling Xue:
Lifetime holes aware register allocation for clustered VLIW processors. 1-4 - Tianyue Lu, Licheng Chen, Mingyu Chen:
Achieving efficient packet-based memory system by exploiting correlation of memory requests. 1-6 - Naman Saraf, Kia Bazargan, David J. Lilja, Marc D. Riedel:
IIR filters using stochastic arithmetic. 1-6 - Noritaka Yamashita, Kazuhiko Minematsu, Toshihiko Okamura, Yukiyasu Tsunoo:
A smaller and faster variant of RSM. 1-6 - Pierluigi Nuzzo, John B. Finn, Antonio Iannopollo, Alberto L. Sangiovanni-Vincentelli:
Contract-based design of control protocols for safety-critical cyber-physical systems. 1-4 - Garo Bournoutian, Alex Orailoglu:
On-device objective-C application optimization framework for high-performance mobile processors. 1-6 - Pietro Mercati, Andrea Bartolini, Francesco Paterna, Tajana Simunic Rosing, Luca Benini:
A Linux-governor based Dynamic Reliability Manager for android mobile devices. 1-4 - Igor Loi, Luca Benini:
A multi banked - Multi ported - Non blocking shared L2 cache for MPSoC platforms. 1-6 - Xin He, Guihai Yan, Yinhe Han, Xiaowei Li:
SuperRange: Wide operational range power delivery design for both STV and NTV computing. 1-6 - Weiwei Chen, Xu Han, Rainer Dömer:
May-happen-in-parallel analysis based on segment graphs for safe ESL models. 1-6 - Tobias Welp, Andreas Kuehlmann:
Property directed invariant refinement for program verification. 1-6 - Gerd Teepe:
The growing importance of microelectronics from a foundry perspective. 1 - Ulrich Rührmair, Ulf Schlichtmann, Wayne P. Burleson:
Special session: How secure are PUFs really? On the reach and limits of recent PUF attacks. 1-4 - Cristina Silvano, Gianluca Palermo, Sotirios Xydis, Ioannis S. Stamelakos:
Voltage island management in near threshold manycore architectures to mitigate dark silicon. 1-6 - Hamed Farbeh, Seyed Ghassem Miremadi:
PSP-Cache: A low-cost fault-tolerant cache memory architecture. 1-4 - Haeseung Lee, Mohammad Abdullah Al Faruque:
GPU-EvR: Run-time event based real-time scheduling framework on GPGPU platform. 1-6 - Stefan Scholl, Norbert Wehn:
Hardware implementation of a Reed-Solomon soft decoder based on information set decoding. 1-6 - Giorgio C. Buttazzo, Enrico Bini, Darren Buttle:
Rate-adaptive tasks: Model, analysis, and design issues. 1-6 - Marco Casale-Rossi, Pietro Palella, Mario Anton, Ori Galzur, Robert Hum, Rainer Kress, Paul Lo:
Panel: The world is going... analog & mixed-signal! What about EDA? 1-5 - Franz Kreupl:
Advancing CMOS with carbon electronics. 1-6 - Said Hamdioui, Jean-Luc Danger, Giorgio Di Natale, Fethulah Smailbegovic, Gerard van Battum, Mark M. Tehranipoor:
Hacking and protecting IC hardware. 1-7 - Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid, Patrick Sudowe, Bastian Leibe, Tamon Sadasue:
A flexible ASIP architecture for connected components labeling in embedded vision applications. 1-6 - Fabien Clermidy, Natalija Jovanovic, Santhosh Onkaraiah, Houcine Oucheikh, Olivier Thomas, Ogun Turkyilmaz, Elisa Vianello, Jean-Michel Portal, Marc Bocquet:
Resistive memories: Which applications? 1-6 - Yu Wang, Boxun Li, Rong Luo, Yiran Chen, Ningyi Xu, Huazhong Yang:
Energy efficient neural networks for big data analytics. 1-2 - Georgios Karakonstantis, Aviinaash Sankaranarayanan, Mohamed M. Sabry, David Atienza, Andreas Burg:
A quality-scalable and energy-efficient approach for spectral analysis of heart rate variability. 1-6 - Jui-Hung Chien, Hao Yu, Ruei-Siang Hsu, Hsueh-Ju Lin, Shih-Chieh Chang:
Package geometric aware thermal analysis by infrared-radiation thermal images. 1-4 - Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell:
New implementions of predictive alternate analog/RF test with augmented model redundancy. 1-4 - Doowon Lee, Ritesh Parikh, Valeria Bertacco:
Brisk and limited-impact NoC routing reconfiguration. 1-6 - Guangshan Duan, Shuai Wang:
Exploiting narrow-width values for improving non-volatile cache lifetime. 1-4 - R. Venkatesh, Ulka Shrotri, G. Murali Krishna, Supriya Agrawal:
EDT: A specification notation for reactive systems. 1-6 - Nathaniel A. Conos, Saro Meguerdichian, Foad Dabiri, Miodrag Potkonjak:
Provably minimal energy using coordinated DVS and power gating. 1-6 - Yue Gao, Sandeep K. Gupta, Yanzhi Wang, Massoud Pedram:
An energy-aware fault tolerant scheduling framework for soft error resilient cloud computing systems. 1-6 - Sébastien Le Nours, Adam Postula, Neil W. Bergmann:
A dynamic computation method for fast and accurate performance evaluation of multi-core architectures. 1-6 - Sven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker:
Using MaxBMC for Pareto-optimal circuit initialization. 1-6 - Oshri Adler, Eli Arbel, Ilia Averbouch, Ilan Beer, Inna Grijnevitch:
Facilitating timing debug by logic path correspondence. 1-6 - Ryan W. Moore, Bruce R. Childers:
Program affinity performance models for performance and utilization. 1-4 - Manu Komalan, José Ignacio Gómez Pérez, Christian Tenllado, Praveen Raghavan, Matthias Hartmann, Francky Catthoor:
Feasibility exploration of NVM based I-cache through MSHR enhancements. 1-6 - Neil Dhruva, Pratyush Kumar, Georgia Giannopoulou, Lothar Thiele:
Computing a language-based guarantee for timing properties of cyber-physical systems. 1-6 - Kumud Nepal, Yueting Li, R. Iris Bahar, Sherief Reda:
ABACUS: A technique for automated behavioral synthesis of approximate computing circuits. 1-6 - Miriam Leeser, Saoni Mukherjee, Jaideep Ramachandran, Thomas Wahl:
Make it real: Effective floating-point reasoning via exact arithmetic. 1-4 - Stefan Wildermann, Michael Glaß, Jürgen Teich:
Multi-objective distributed run-time resource management for many-cores. 1-6 - Giorgos Dimitrakopoulos, I. Seitanidis, Anastasios Psarras, K. Tsiouris, Pavlos M. Mattheakis, Jordi Cortadella:
Hardware primitives for the synthesis of multithreaded elastic systems. 1-4 - Seokwoo Song, Minseok Lee, John Kim, Woong Seo, Yeon-Gon Cho, Soojung Ryu:
Energy-efficient scheduling for memory-intensive GPGPU workloads. 1-6 - Masaaki Kondo, Hiroaki Kobayashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura:
Design and evaluation of fine-grained power-gating for embedded microprocessors. 1-6 - Shan Tang, Ziyuan Zhu, Yongtao Su:
System-level design methodology enabling fast development of baseband MP-SoC for 4G small cell base station. 1-6 - Timon D. ter Braak:
Using guided local search for adaptive resource reservation in large-scale embedded systems. 1-4 - Manfred Thanner:
Virtual prototype life cycle in automotive applications. 1 - David Fuller:
System design challenges for next generation wireless and embedded systems. 1 - Jan Reineke, Reinhard Wilhelm:
Impact of resource sharing on performance and performance prediction. 1-2 - Alexandru Paler, Simon J. Devitt, Kae Nemoto, Ilia Polian:
Software-based Pauli tracking in fault-tolerant quantum circuits. 1-4 - Sébastien Le Beux, Hui Li, Ian O'Connor, Kazem Cheshmi, Xuchen Liu, Jelena Trajkovic, Gabriela Nicolescu:
Chameleon: Channel efficient Optical Network-on-Chip. 1-6 - Luca Ramini, Alberto Ghiribaldi, Paolo Grani, Sandro Bartolini, Hervé Tatenguem Fankem, Davide Bertozzi:
Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline. 1-6 - Di Liu, Jelena Spasic, Jiali Teddy Zhai, Todor P. Stefanov, Gang Chen:
Resource optimization for CSDF-modeled streaming applications with latency constraints. 1-6 - Walter M. Weber, Jens Trommer, Matthias Grube, Andre Heinzig, Markus König, Thomas Mikolajick:
Reconfigurable silicon nanowire devices and circuits: Opportunities and challenges. 1-6 - Moning Zhang, Zuochang Ye, Yan Wang:
Efficient high-sigma yield analysis for high dimensional problems. 1-6 - Kajori Banerjee, Pallab Dasgupta:
Acceptance and random generation of event sequences under real time calculus constraints. 1-6 - Yier Jin:
EDA tools trust evaluation through security property proofs. 1-4 - Marten van Dijk, Ulrich Rührmair:
Protocol attacks on advanced PUF protocols and countermeasures. 1-6 - Yuelin Du, Martin D. F. Wong:
Optimization of standard cell based detailed placement for 16 nm FinFET process. 1-6 - Ji Qi, Mark Zwolinski:
Efficient simulation and modelling of non-rectangular NoC topologies. 1-4 - Eberle A. Rambo, Alexander Tschiene, Jonas Diemer, Leonie Ahrendts, Rolf Ernst:
Failure analysis of a network-on-chip for real-time mixed-critical systems. 1-4 - Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Pass-XNOR logic: A new logic style for P-N junction based graphene circuits. 1-4 - Hoang Minh Le, Rolf Drechsler:
Towards verifying determinism of SystemC designs. 1-4 - Nima Aghaee, Zebo Peng, Petru Eles:
An efficient temperature-gradient based burn-in technique for 3D stacked ICs. 1-4 - Rudy Lauwereins:
Interfacing to living cells. 1-3 - Boxun Li, Yu Wang, Yiran Chen, Hai (Helen) Li, Huazhong Yang:
ICE: Inline calibration for memristor crossbar-based computing engine. 1-4 - Felipe Sampaio, Muhammad Shafique, Bruno Zatt, Sergio Bampi, Jörg Henkel:
dSVM: Energy-efficient distributed Scratchpad Video Memory Architecture for the next-generation High Efficiency Video Coding. 1-6 - Mudit Bhargava, Ken Mai:
An efficient reliable PUF-based cryptographic key generator in 65nm CMOS. 1-6 - Francesco Paterna, Joe Zanotelli, Tajana Simunic Rosing:
Ambient variation-tolerant and inter components aware thermal management for mobile system on chips. 1-6 - Yuanfan Yang, Jimson Mathew, Dhiraj K. Pradhan, Marco Ottavi, Salvatore Pontarelli:
Complementary resistive switch based stateful logic operations using material implication. 1-4 - Andy Heinig, Manfred Dietrich, Andreas Herkersdorf, Felix Miller, Thomas Wild, Kai Hahn, Armin Grünewald, Rainer Brück, Steffen Krohnert, Jochen Reisinger:
System integration - The bridge between More than Moore and More Moore. 1-9 - Michael Bolle:
The connected car and its implication to the automotive chip roadmap. 1 - Arquimedes Canedo, Mohammad Abdullah Al Faruque, Jan H. Richter:
Multi-disciplinary integrated design automation tool for automotive cyber-physical systems. 1-2 - Jonah Caplan, Maria Isabel Mera, Peter A. Milder, Brett H. Meyer:
Trade-offs in execution signature compression for reliable processor systems. 1-6 - Swarup Bhunia, Vaishnavi Nattar Ranganathan, Tina He, Srihari Rajgopal, Rui Yang, Mehran Mehregany, Philip X.-L. Feng:
Toward ultralow-power computing at exteme with silicon carbide (SiC) nanoelectromechanical logic. 1-6 - Carna Radojicic, Christoph Grimm, Javier Moreno, Xiao Pan:
Semi-symbolic analysis of mixed-signal systems including discontinuities. 1-4 - Martina Seidl, Robert Könighofer:
Partial witnesses from preprocessed quantified Boolean formulas. 1-6 - Mirko Caspar, Mirko Lippmann, Wolfram Hardt:
Automated system testing using dynamic and resource restricted clients. 1-4 - Jiaxing Zhang, Gunar Schirner:
Automatic specification granularity tuning for design space exploration. 1-6 - Jianxiong Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung:
Image progressive acquisition for hardware systems. 1-6 - Guowei Zhang, Peter A. Beerel:
Stochastic analysis of Bubble Razor. 1-6 - Jedrzej Kufel, Peter R. Wilson, Stephen Hill, Bashir M. Al-Hashimi, Paul N. Whatmough, James Myers:
Clock-modulation based watermark for protection of embedded processors. 1-6 - Muhammad Yasin, Anas Shahrour, Ibrahim Abe M. Elfadel:
Unified, ultra compact, quadratic power proxies for multi-core processors. 1-4 - Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania:
An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs. 1-6 - Yanchen Long, Zhonghai Lu, Xiaolang Yan:
Analysis and evaluation of per-flow delay bound for multiplexing models. 1-4 - Syed Rameez Naqvi, Andreas Steininger:
A tree arbiter cell for high speed resource sharing in asynchronous environments. 1-6 - Young-Joon Lee, Sung Kyu Lim:
On GPU bus power reduction with 3D IC technologies. 1-6 - Jiayin Li, Kartik Mohanram:
Write-once-memory-code phase change memory. 1-6 - Gianpiero Cabodi, Paolo Pasini, Stefano Quer, Danilo Vendraminetto:
Tightening BDD-based approximate reachability with SAT-based clause generalization∗. 1-6 - Marta Ortín, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals:
Dynamic construction of circuits for reactive traffic in homogeneous CMPs. 1-4 - Seiyang Yang, Jaehoon Han, Doowhan Kwak, Namdo Kim, Daeseo Cha, Junhyuck Park, Jay Kim:
Predictive parallel event-driven HDL simulation with a new powerful prediction strategy. 1-3 - Andreas Riefert, Lyl M. Ciganda, Matthias Sauer, Paolo Bernardi, Matteo Sonza Reorda, Bernd Becker:
An effective approach to automatic functional processor test generation for small-delay faults. 1-6 - Li Yu, Sharad Saxena, Christopher Hess, Ibrahim M. Elfadel, Dimitri A. Antoniadis, Duane S. Boning:
Efficient performance estimation with very small sample size via physical subspace projection and maximum a posteriori estimation. 1-6 - Shin-Haeng Kang, Hoeseok Yang, Sungchan Kim, Iuliana Bacivarov, Soonhoi Ha, Lothar Thiele:
Reliability-aware mapping optimization of multi-core systems with mixed-criticality. 1-4 - Hu Chen, Sanghamitra Roy, Koushik Chakraborty:
DARP: Dynamically Adaptable Resilient Pipeline design in microprocessors. 1-6 - Hsi-An Chien, Zhen-Yu Peng, Yun-Ru Wu, Ting-Hsiung Wang, Hsin-Chang Lin, Chi-Feng Wu, Ting-Chi Wang:
Mask-cost-aware ECO routing∗. 1-4 - Francesco Beneventi, Andrea Bartolini, Pascal Vivet, Denis Dutoit, Luca Benini:
Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip. 1-4 - Nahid Farhady Ghalaty, Aydin Aysu, Patrick Schaumont:
Analyzing and eliminating the causes of fault sensitivity analysis. 1-6 - Hao Shen, Qinru Qiu:
Contention aware frequency scaling on CMPs with guaranteed quality of service. 1-6 - Georgia Giannopoulou, Nikolay Stoimenov, Pengcheng Huang, Lothar Thiele:
Mapping mixed-criticality applications on multi-core architectures. 1-6 - Antonio Iannopollo, Pierluigi Nuzzo, Stavros Tripakis, Alberto L. Sangiovanni-Vincentelli:
Library-based scalable refinement checking for contract-based design. 1-6 - Jan R. Seyler, Thilo Streichert, Juri Warkentin, Matthias Spagele, Michael Glaß, Jürgen Teich:
A self-propagating wakeup mechanism for point-to-point networks with partial network support. 1-6 - Sih-Sian Wu, Kanwen Wang, Sai Manoj Pudukotai Dinakarrao, Tsung-Yi Ho, Mingbin Yu, Hao Yu:
A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os. 1-4 - Jorge Fernandez Villena, L. Miguel Silveira:
Efficient analysis of variability impact on interconnect lines and resistor networks. 1-6 - Yang Lin, Mark Zwolinski, Basel Halak:
A low-cost radiation hardened flip-flop. 1-6 - Sebastiaan J. C. Joosten, Julien Schmaltz:
Scalable liveness verification for communication fabrics. 1-6 - Ralph Nathan, Daniel J. Sorin:
Nostradamus: Low-cost hardware-only error detection for processor cores. 1-6 - Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei:
Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms. 1-6 - Radoslav Ivanov, Miroslav Pajic, Insup Lee:
Attack-resilient sensor fusion. 1-6 - Burkhard Hensel, Klaus Kabitzsch:
The energy benefit of level-crossing sampling including the actuator's energy consumption. 1-4 - Ashish Ranjan, Arnab Raha, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
ASLAN: Synthesis of approximate sequential circuits. 1-6 - Xuan Wang, Jiang Xu, Zhe Wang, Kevin J. Chen, Xiaowen Wu, Zhehui Wang:
Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors. 1-4 - Antonio J. Ginés, Gildas Léger:
Sigma-delta testability for pipeline A/D converters. 1-6 - Chia-Chun Lin, Chun-Yao Wang, Yung-Chih Chen, Ching-Yi Huang:
Rewiring for threshold logic circuit minimization. 1-6 - Irith Pomeranz:
Test and non-test cubes for diagnostic test generation based on merging of test cubes. 1-4 - Marco Casale-Rossi, Giovanni De Micheli, Rob Aitken, Antun Domic, Manfred Horstmann, Robert Hum, Philippe Magarshack:
Panel: Emerging vs. established technologies, a two sphinxes' riddle at the crossroads? 1-4 - Yang Song, Sai Manoj Pudukotai Dinakarrao, Hao Yu:
Zonotope-based nonlinear model order reduction for fast performance bound analysis of analog circuits with multiple-interval-valued parameter variations. 1-6 - Yi-En Chen, Tu-Hsiung Tsai, Shi-Hao Chen, Hung-Ming Chen:
Cost-effective decap selection for beyond die power integrity. 1-4 - Paul Wettin, Jacob Murray, Ryan Gary Kim, Xinmin Yu, Partha Pratim Pande, Deuk Hyoun Heo:
Performance evaluation of wireless NoCs in presence of irregular network routing strategies. 1-6 - Hong Chinh Doan, Haris Javaid, Sri Parameswaran:
Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs. 1-6 - Peter M. Maurer:
A universal symmetry detection algorithm. 1-4 - Bernhard Fischer, Christian Cech, Hannes Muhr:
Power modeling and analysis in early design phases. 1-6 - Kitae Park, Geunho Kim, Taewhan Kim:
Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs. 1-4 - Ziyi Liu, Weidong Shi, Shouhuai Xu, Zhiqiang Lin:
Programmable decoder and shadow threads: Tolerate remote code injection exploits with diversified redundancy. 1-6 - Matthias Wuttig:
Exploring the limits of phase change memories. 1-2 - Pramod Subramanyan, Divya Arora:
Formal verification of taint-propagation security properties in a commercial SoC design. 1-2 - Wim Meeus, Dirk Stroobandt:
Automating data reuse in High-Level Synthesis. 1-4 - Seyab Khan, Innocent Agbo, Said Hamdioui, Halil Kukner, Ben Kaczer, Praveen Raghavan, Francky Catthoor:
Bias Temperature Instability analysis of FinFET based SRAM cells. 1-6 - Kathrin Rosvall, Ingo Sander:
A constraint-based design space exploration framework for real-time applications on MPSoCs. 1-6 - Taemin Kim, Yatin Hoskote:
Automatic generation of custom SIMD instructions for Superword Level Parallelism. 1-6 - Md. Tauhidur Rahman, Domenic Forte, Jim Fahrny, Mohammad Tehranipoor:
ARO-PUF: An aging-resistant ring oscillator PUF design. 1-6 - Anup Das, Akash Kumar, Bharadwaj Veeravalli, Cristiana Bolchini, Antonio Miele:
Combined DVFS and mapping exploration for lifetime and soft-error susceptibility improvement in MPSoCs. 1-6 - David Novo, Nazanin Farahpour, Paolo Ienne, Ubaid Ahmad, Francky Catthoor:
Energy efficient MIMO processing: A case study of opportunistic run-time approximations. 1-6 - Tiansheng Zhang, José L. Abellán, Ajay Joshi, Ayse K. Coskun:
Thermal management of manycore systems with silicon-photonic networks. 1-6 - Meng-Ling Tsai, Yi-Jung Chen, Yi-Ting Chen, Ru-Hua Chang:
Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs. 1-6 - Chia-Yi Lee, Tai-Hung Li, Tai-Chen Chen:
Design-for-debug routing for FIB probing. 1-4 - Guillaume Prenat, Gregory di Pendina, Christophe Layer, Olivier Goncalves, K. Jaber, Bernard Dieny, Ricardo C. Sousa, Ioan Lucian Prejbeanu, Jean-Pierre Nozieres:
Magnetic memories: From DRAM replacement to ultra low power logic chips. 1 - Woojoo Lee, Yanzhi Wang, Massoud Pedram:
VRCon: Dynamic reconfiguration of voltage regulators in a multicore platform. 1-6 - Swaminathan Narayanaswamy, Sebastian Steinhorst, Martin Lukasiewycz, Matthias Kauer, Samarjit Chakraborty:
Optimal dimensioning of active cell balancing architectures. 1-6 - Sebastian Graf, Michael Glaß, Jürgen Teich, Christoph Lauer:
Multi-variant-based design space exploration for automotive embedded systems. 1-6 - Ammar Karkar, Nizar Dahir, Ra'ed Al-Dujaily, Kenneth Tong, Terrence S. T. Mak, Alex Yakovlev:
Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip. 1-4 - Sujan Pandey, Bart Vermeulen:
Transient errors resiliency analysis technique for automotive safety critical applications. 1-4 - Umair Siddique, Sofiène Tahar:
Towards the formal analysis of microresonators based photonic systems. 1-6 - Shu-Yung Chen, Chien-Hao Chen, Ren-Song Tsay:
An activity-sensitive contention delay model for highly efficient deterministic full-system simulations. 1-6 - Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle:
A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks. 1-4 - Isuru Nawinne, Josef Schneider, Haris Javaid, Sri Parameswaran:
Hardware-based fast exploration of cache hierarchies in application specific MPSoCs. 1-6 - Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho:
A logic integrated optimal pin-count design for digital microfluidic biochips. 1-6 - Bartomeu Alorda, Cristian Carmona, Sebastià A. Bota:
Word-line power supply selector for stability improvement of embedded SRAMs in high reliability applications. 1-6 - Manuel Harrant, Thomas Nirmaier, Jérôme Kirscher, Christoph Grimm, Georg Pelz:
Emulation-based robustness assessment for automotive smart-power ICs. 1-6 - Paula Aguilera, Jungseob Lee, Amin Farmahini Farahani, Katherine Morrow, Michael J. Schulte, Nam Sung Kim:
Process variation-aware workload partitioning algorithms for GPUs supporting spatial-multitasking. 1-6 - Hrishikesh Salunkhe, Orlando Moreira, Kees van Berkel:
Mode-Controlled Dataflow based modeling & analysis of a 4G-LTE receiver. 1-4 - Irith Pomeranz:
Substituting transition faults with path delay faults as a basic delay fault model. 1-6 - Kitae Kim, Donghwa Shin, Qing Xie, Yanzhi Wang, Massoud Pedram, Naehyuck Chang:
FEPMA: Fine-grained event-driven power meter for android smartphones based on device driver layer event monitoring. 1-6 - Raymond Frijns, Shreya Adyanthaya, Sander Stuijk, Jeroen Voeten, Marc C. W. Geilen, Ramon R. H. Schiffelers, Henk Corporaal:
Timing analysis of First-Come First-Served scheduled interval-timed Directed Acyclic Graphs. 1-6 - Valerio Guarnieri, Massimo Petricca, Alessandro Sassone, Sara Vinco, Nicola Bombieri, Franco Fummi, Enrico Macii, Massimo Poncino:
A cross-level verification methodology for digital IPs augmented with embedded timing monitors. 1-6 - Manuel Velasco-Jimenez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
Implementation issues in the hierarchical composition of performance models of analog circuits. 1-6 - Huping Ding, Yun Liang, Tulika Mitra:
WCET-Centric dynamic instruction cache locking. 1-6 - K. Leo:
Organic electronics - From lab to markets. 1 - Poona Bahrebar, Dirk Stroobandt:
Improving hamiltonian-based routing methods for on-chip networks: A turn model approach. 1-4 - Richard Membarth, Oliver Reiche, Frank Hannig, Jürgen Teich:
Code generation for embedded heterogeneous architectures on android. 1-6 - Pratyush Kumar, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele:
COOLIP: Simple yet effective job allocation for distributed thermally-throttled processors. 1-4 - Jeroen Delvaux, Ingrid Verbauwhede:
Key-recovery attacks on various RO PUF constructions via helper data manipulation. 1-6 - Christer Karlsson, Peter Fischer:
Thinfilm printed ferro-electric memories and integrated products. 1 - Emanuele Cannella, Mohamed Bamakhrama, Todor P. Stefanov:
System-level scheduling of real-time streaming applications using a semi-partitioned approach. 1-6 - Donghwa Shin, Massimo Poncino, Enrico Macii:
Thermal management of batteries using a hybrid supercapacitor architecture. 1-6 - Bhanu Pratap Singh, Arunprasath Shankar, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, Steve Clay:
Cross-correlation of specification and RTL for soft IP analysis. 1-6
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