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ORCIDSudhakar M. Reddy
Person information
- affiliation: University of Iowa, Iowa City, IA, USA
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2020 – today
- 2022
[j228]Chong-Siao Ye
, Shi-Xuan Zheng, Fong-Jyun Tsai, Chen Wang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Justyna Zawada, Mark Kassab, Janusz Rajski:
Efficient Test Compression Configuration Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2323-2336 (2022)- [c432]Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy:
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. VTS 2022: 1-7 - 2020
- [j227]Leonel Hernández Martínez, S. Saqib Khursheed, Sudhakar M. Reddy:
LFSR generation for high test coverage and low hardware overhead. IET Comput. Digit. Tech. 14(1): 27-36 (2020) - [j226]Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy:
Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1340-1345 (2020) - [j225]Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer:
Deterministic Stellar BIST for Automotive ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(8): 1699-1710 (2020) - [c431]Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski:
Efficient Prognostication of Pattern Count with Different Input Compression Ratios. ETS 2020: 1-2 - [c430]Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada:
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. ITC 2020: 1-10 - [c429]Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Shi-Xuan Zheng:
Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. ITC-Asia 2020: 130-135
2010 – 2019
- 2019
- [j224]Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman:
Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design. ACM Trans. Design Autom. Electr. Syst. 24(4): 42:1-42:19 (2019) - [j223]Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy:
An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2105-2118 (2019) - [c428]Cheng-Hung Wu, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Gaurav Veda, Sudhakar M. Reddy, Chun-Cheng Hu, Chong-Siao Ye:
Deep Learning Based Test Compression Analyzer. ATS 2019: 1-6 - [c427]Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman:
Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines. DATE 2019: 1022-1027 - [c426]Xijiang Lin, Sudhakar M. Reddy:
On Generating Fault Diagnosis Patterns for Designs with X Sources. ETS 2019: 1-6 - [c425]Yue Tian, Gaurav Veda, Wu-Tung Cheng, Manish Sharma, Huaxing Tang, Neerja Bawaskar, Sudhakar M. Reddy:
A supervised machine learning application in volume diagnosis. ETS 2019: 1-6 - 2018
- [j222]Daniele Rossi, Vasileios Tenentes, Sudhakar M. Reddy, Bashir M. Al-Hashimi, Andrew D. Brown:
Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1345-1357 (2018) - [j221]Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker:
On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2152-2165 (2018) - [j220]Cheng-Hung Wu, Sheng-Lin Lin, Kuen-Jong Lee, Sudhakar M. Reddy:
A Repair-for-Diagnosis Methodology for Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2254-2267 (2018) - [c424]Daniele Rossi, Vasileios Tenentes, S. Saqib Khursheed, Sudhakar M. Reddy:
Recycled IC detection through aging sensor. ETS 2018: 1-2 - [c423]Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy:
Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run. ITC 2018: 1-10 - [c422]Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer:
Deterministic Stellar BIST for In-System Automotive Test. ITC 2018: 1-9 - [c421]Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy:
Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run. ITC-Asia 2018: 1-6 - [c420]Yingdi Liu, Janusz Rajski, Sudhakar M. Reddy, Jedrzej Solecki, Jerzy Tyszer:
Staggered ATPG with capture-per-cycle observation test points. VTS 2018: 1-6 - 2017
- [j219]Cesar Acero, Derek Feltham, Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Marek Patyra, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Justyna Zawada:
Embedded Deterministic Test Points. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2949-2961 (2017) - [c419]Wu-Tung Cheng, Randy Klingenberg, Brady Benware, Wu Yang, Manish Sharma, Geir Eide, Yue Tian, Sudhakar M. Reddy, Yan Pan, Sherwin Fernandes, Atul Chittora:
Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data. ATS 2017: 219-224 - [c418]Jan Burchard, Dominik Erb, Adit D. Singh, Sudhakar M. Reddy, Bernd Becker:
Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG. DATE 2017: 422-427 - [c417]Wu-Tung Cheng, Yue Tian, Sudhakar M. Reddy:
Volume diagnosis data mining. ETS 2017: 1-10 - [c416]Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy:
Test generation for open and delay faults in CMOS circuits. ITC-Asia 2017: 21-26 - [c415]Pascal Raiola, Dominik Erb, Sudhakar M. Reddy, Bernd Becker:
Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model. VLSID 2017: 135-140 - [c414]Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker:
Efficient SAT-based generation of hazard-activated TSOF tests. VTS 2017: 1-6 - 2016
- [c413]Irith Pomeranz, Sudhakar M. Reddy:
On the Switching Activity in Faulty Circuits During Test Application. ATS 2016: 13-18 - [c412]Xijiang Lin, Sudhakar M. Reddy, Wu-Tung Cheng:
On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection. ATS 2016: 132-137 - [c411]Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski:
Transistor stuck-on fault detection tests for digital CMOS circuits. ETS 2016: 1-6 - [c410]Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer:
Minimal area test points for deterministic patterns. ITC 2016: 1-7 - 2015
- [j218]Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang:
Isometric Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1847-1859 (2015) - [c409]Xijiang Lin, Sudhakar M. Reddy:
On generating high quality tests based on cell functions. ITC 2015: 1-9 - [c408]Wu-Tung Cheng, Sudhakar M. Reddy:
Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement. VLSID 2015: 21-23 - [c407]Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski:
Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits. VLSID 2015: 399-404 - [c406]Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker:
Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects. VTS 2015: 1-6 - [c405]Andreas Riefert, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker:
Improving diagnosis resolution of a fault detection test set. VTS 2015: 1-6 - 2014
- [j217]Sudhakar M. Reddy, Zhuo Zhang:
On achieving minimal size test sets for scan designs. it Inf. Technol. 56(4): 150-156 (2014) - [c404]Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker:
Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects. ATS 2014: 131-136 - [c403]Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang:
Isometric test compression with low toggling activity. ITC 2014: 1-7 - [c402]Alexander Czutro, Sudhakar M. Reddy, Ilia Polian, Bernd Becker:
SAT-Based Test Pattern Generation with Improved Dynamic Compaction. VLSID 2014: 56-61 - [c401]Matthias Sauer, Sven Reimer, Sudhakar M. Reddy, Bernd Becker:
Efficient SAT-Based Circuit Initialization for Larger Designs. VLSID 2014: 62-67 - [c400]Sharada Jha, Kameshwar Chandrasekar, Weixin Wu, Ramesh Sharma, Sanjay Sengupta, Sudhakar M. Reddy:
A Cube-Aware Compaction Method for Scan ATPG. VLSID 2014: 98-103 - [p1]Sudhakar M. Reddy, Peter Maxwell:
Fundamentals of Small-Delay Defect Testing. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 1-22 - 2013
- [c399]Amit Kumar, Janusz Rajski, Sudhakar M. Reddy, Thomas Rinderknecht:
On the Generation of Compact Deterministic Test Sets for BIST Ready Designs. Asian Test Symposium 2013: 201-206 - [c398]Amit Kumar, Janusz Rajski, Sudhakar M. Reddy, Chen Wang:
On the generation of compact test sets. ITC 2013: 1-10 - [c397]Yu Huang, Xiaoxin Fan, Huaxing Tang, Manish Sharma, Wu-Tung Cheng, Brady Benware, Sudhakar M. Reddy:
Distributed dynamic partitioning based diagnosis of scan chain. VTS 2013: 1-6 - 2012
- [j216]Irith Pomeranz, Sudhakar M. Reddy:
Reset and partial-reset-based functional broadside tests. IET Comput. Digit. Tech. 6(4): 232-239 (2012) - [j215]Irith Pomeranz, Sudhakar M. Reddy:
Resolution of Diagnosis Based on Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 172-176 (2012) - [c396]Xiaoxin Fan, Manish Sharma, Wu-Tung Cheng, Sudhakar M. Reddy:
Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns. Asian Test Symposium 2012: 7-12 - [c395]Xiaoqing Wen, Sudhakar M. Reddy:
Session Summary III: Power-Aware Testing: Present and Future. Asian Test Symposium 2012: 220 - [c394]Amit Kumar, Sudhakar M. Reddy, Bernd Becker, Irith Pomeranz:
Performance aware partitioning for 3D-SOCs. ISOCC 2012: 163-166 - [c393]Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker:
TSV and DFT cost aware circuit partitioning for 3D-SOCs. ISQED 2012: 21-26 - [c392]Xiaoxin Fan, Huaxing Tang, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Brady Benware:
Improved volume diagnosis throughput using dynamic design partitioning. ITC 2012: 1-10 - [c391]Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker:
Functional test of small-delay faults using SAT and Craig interpolation. ITC 2012: 1-8 - [c390]Matthias Sauer, Stefan Kupferschmid, Alejandro Czutro, Sudhakar M. Reddy, Bernd Becker:
Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation. VLSI Design 2012: 382-387 - 2011
- [j214]Irith Pomeranz, Sudhakar M. Reddy:
Primary input cones based on test sequences in synchronous sequential circuits. IET Comput. Digit. Tech. 5(1): 16-24 (2011) - [j213]Irith Pomeranz, Sudhakar M. Reddy:
Two-dimensional partially functional broadside tests. IET Comput. Digit. Tech. 5(4): 247-253 (2011) - [j212]Irith Pomeranz, Sudhakar M. Reddy:
Sizes of test sets for path delay faults using strong and weak non-robust tests. IET Comput. Digit. Tech. 5(5): 405-414 (2011) - [j211]Irith Pomeranz, Sudhakar M. Reddy:
Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation. IET Comput. Digit. Tech. 5(5): 415-423 (2011) - [j210]Irith Pomeranz, Sudhakar M. Reddy:
Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan. J. Low Power Electron. 7(2): 245-253 (2011) - [j209]Ilia Polian, John P. Hayes, Sudhakar M. Reddy, Bernd Becker:
Modeling and Mitigating Transient Errors in Logic Circuits. IEEE Trans. Dependable Secur. Comput. 8(4): 537-547 (2011) - [j208]Irith Pomeranz, Sudhakar M. Reddy:
Reducing the switching activity of test sequences under transparent-scan. ACM Trans. Design Autom. Electr. Syst. 16(2): 17:1-17:21 (2011) - [j207]Irith Pomeranz, Sudhakar M. Reddy:
Fixed-State Tests for Delay Faults in Scan Designs. IEEE Trans. Very Large Scale Integr. Syst. 19(1): 142-146 (2011) - [j206]Irith Pomeranz, Sudhakar M. Reddy:
Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(2): 333-337 (2011) - [j205]Irith Pomeranz, Sudhakar M. Reddy:
On Functional Broadside Tests With Functional Propagation Conditions. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1094-1098 (2011) - [j204]Irith Pomeranz, Sudhakar M. Reddy:
Broadside and Functional Broadside Tests for Partial-Scan Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1104-1108 (2011) - [j203]Irith Pomeranz, Sudhakar M. Reddy:
Static Test Data Volume Reduction Using Complementation or Modulo- M Addition. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1108-1112 (2011) - [j202]Irith Pomeranz, Sudhakar M. Reddy:
Reducing the Storage Requirements of a Test Sequence by Using One or Two Background Vectors. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1755-1764 (2011) - [j201]Irith Pomeranz, Sudhakar M. Reddy:
Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1907-1911 (2011) - [c389]J. M. Howard, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker:
Fault diagnosis aware ATE assisted test response compaction. ASP-DAC 2011: 812-817 - [c388]Xiaoxin Fan, Huaxing Tang, Sudhakar M. Reddy, Wu-Tung Cheng, Brady Benware:
On Using Design Partitioning to Reduce Diagnosis Memory Footprint. Asian Test Symposium 2011: 219-225 - [c387]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Jakub Janicki:
Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating. Asian Test Symposium 2011: 267-272 - [c386]Shida Zhong, S. Saqib Khursheed, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Krishnendu Chakrabarty:
Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation. Asian Test Symposium 2011: 389-394 - [c385]Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker:
Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing. DATE 2011: 1424-1429 - [c384]Xiaoxin Fan, Sudhakar M. Reddy, Irith Pomeranz:
Max-Fill: A method to generate high quality delay tests. DDECS 2011: 375-380 - [c383]Xun Tang, Wu-Tung Cheng, Ruifeng Guo, Huaxing Tang, Sudhakar M. Reddy:
Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence Tree. DFT 2011: 217-225 - [c382]Xiaoxin Fan, Sudhakar M. Reddy, Senling Wang, Seiji Kajihara, Yasuo Sato:
Genetic algorithm based approach for segmented testing. DSN Workshops 2011: 85-90 - [c381]Janusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy:
Low power compression utilizing clock-gating. ITC 2011: 1-8 - 2010
- [j200]Irith Pomeranz, Sudhakar M. Reddy:
Diagnosis of path delay faults based on low-coverage tests. IET Comput. Digit. Tech. 4(2): 89-103 (2010) - [j199]Irith Pomeranz, Sudhakar M. Reddy:
Static test compaction for diagnostic test sets of full-scan circuits. IET Comput. Digit. Tech. 4(5): 365-373 (2010) - [j198]Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker:
Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. Int. J. Parallel Program. 38(3-4): 185-202 (2010) - [j197]Irith Pomeranz, Sudhakar M. Reddy:
Test Sequences with Reduced and Increased Switching Activity. J. Low Power Electron. 6(2): 350-358 (2010) - [j196]Irith Pomeranz, Sudhakar M. Reddy:
Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis. IEEE Trans. Computers 59(2): 150-158 (2010) - [j195]Irith Pomeranz, Sudhakar M. Reddy:
TOV: Sequential Test Generation by Ordering of Test Vectors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 454-465 (2010) - [j194]Irith Pomeranz, Sudhakar M. Reddy:
On Test Generation With Test Vector Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 502-506 (2010) - [j193]Irith Pomeranz, Sudhakar M. Reddy:
On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1135-1140 (2010) - [j192]Irith Pomeranz, Sudhakar M. Reddy:
Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1449-1453 (2010) - [j191]Irith Pomeranz, Sudhakar M. Reddy:
On Undetectable Faults and Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1832-1837 (2010) - [j190]Irith Pomeranz, Sudhakar M. Reddy:
Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 333-337 (2010) - [j189]Irith Pomeranz, Sudhakar M. Reddy:
Path Selection for Transition Path Delay Faults. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 401-409 (2010) - [j188]Irith Pomeranz, Sudhakar M. Reddy:
Robust Fault Models Where Undetectable Faults Imply Logic Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1230-1234 (2010) - [j187]Irith Pomeranz, Sudhakar M. Reddy:
Switching Activity as a Test Compaction Heuristic for Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. 18(9): 1357-1361 (2010) - [j186]Irith Pomeranz, Sudhakar M. Reddy:
Selection of a Fault Model for Fault Diagnosis Based on Unique Responses. IEEE Trans. Very Large Scale Integr. Syst. 18(11): 1533-1543 (2010) - [c380]Irith Pomeranz, Sudhakar M. Reddy:
Functional and partially-functional skewed-load tests. ASP-DAC 2010: 505-510 - [c379]Xun Tang, Wu-Tung Cheng, Ruifeng Guo, Sudhakar M. Reddy:
Diagnosis of Multiple Physical Defects Using Logic Fault Models. Asian Test Symposium 2010: 94-99 - [c378]Irith Pomeranz, Sudhakar M. Reddy:
On Bias in Transition Coverage of Test Sets for Path Delay Faults. Asian Test Symposium 2010: 349-352 - [c377]Irith Pomeranz, Sudhakar M. Reddy:
Reducing the storage requirements of a test sequence by using a background vector. DATE 2010: 1237-1242 - [c376]Irith Pomeranz, Sudhakar M. Reddy:
On reset based functional broadside tests. DATE 2010: 1438-1443 - [c375]Irith Pomeranz, Sudhakar M. Reddy:
Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs. DFT 2010: 349-357 - [c374]Irith Pomeranz, Sudhakar M. Reddy:
Input test data volume reduction based on test vector chains. ETS 2010: 240 - [c373]Bo Yao, Irith Pomeranz, Sudhakar M. Reddy:
Deterministic broadside test generation for transition path delay faults. ACM Great Lakes Symposium on VLSI 2010: 135-138 - [c372]Irith Pomeranz, Sudhakar M. Reddy:
Selecting state variables for improved on-line testability through output response comparison of identical circuits. IOLTS 2010: 179-184 - [c371]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab:
Low capture power at-speed test in EDT environment. ITC 2010: 714-723 - [c370]Narendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz:
Multiple fault activation cycle tests for transistor stuck-open faults. ITC 2010: 821 - [c369]Irith Pomeranz, Sudhakar M. Reddy:
Output-Dependent Diagnostic Test Generation. VLSI Design 2010: 3-8 - [c368]Irith Pomeranz, Sudhakar M. Reddy:
Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration. VLSI Design 2010: 39-44 - [c367]Irith Pomeranz, Sudhakar M. Reddy:
Forming multi-cycle tests for delay faults by concatenating broadside tests. VTS 2010: 51-56 - [c366]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab:
At-speed scan test with low switching activity. VTS 2010: 177-182 - [c365]Irith Pomeranz, Sudhakar M. Reddy:
On multiple bridging faults. VTS 2010: 221-226
2000 – 2009
- 2009
- [j185]Irith Pomeranz, Sudhakar M. Reddy:
Definition and generation of partially-functional broadside tests. IET Comput. Digit. Tech. 3(1): 1-13 (2009) - [j184]Irith Pomeranz, Sudhakar M. Reddy:
Same/different fault dictionary: an extended pass/fail fault dictionary with improved diagnostic resolution. IET Comput. Digit. Tech. 3(1): 85-93 (2009) - [j183]Irith Pomeranz, Sudhakar M. Reddy: