


default search action
IEEE Transactions on Very Large Scale Integration Systems, Volume 28
Volume 28, Number 1, January 2020
- Massimo Alioto
:
Editorial on the Opening of the New Editorial Year - The State of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1-2 - Jan M. Rabaey
:
Human-Centric Computing. 3-11 - Xiaoran Wang
, Tianwei Liu, Shita Guo
, Mitchell A. Thornton
, Ping Gui
:
A 2.56-Gb/s Serial Wireline Transceiver That Supports an Auxiliary Channel in 65-nm CMOS. 12-22 - Yu-Chuan Lin
, Hen-Wai Tsao
:
A 10-Gb/s Eye-Opening Monitor Circuit for Receiver Equalizer Adaptations in 65-nm CMOS. 23-34 - Yunxuan Yu
, Chen Wu, Tiandong Zhao, Kun Wang, Lei He
:
OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks. 35-47 - Shihui Yin
, Zhewei Jiang
, Minkyu Kim
, Tushar Gupta, Mingoo Seok
, Jae-Sun Seo
:
Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks. 48-61 - Kangjun Bai
, Qiyuan An, Lingjia Liu, Yang Yi
:
A Training-Efficient Hybrid-Structured Deep Neural Network With Reconfigurable Memristive Synapses. 62-75 - Adarsha Balaji
, Francky Catthoor, Anup Das
, Yuefeng Wu, Khanh Huynh, Francesco Dell'Anna, Giacomo Indiveri
, Jeffrey L. Krichmar
, Nikil D. Dutt
, Siebren Schaafsma:
Mapping Spiking Neural Networks to Neuromorphic Hardware. 76-86 - Jaehyeong Sim
, Somin Lee, Lee-Sup Kim
:
An Energy-Efficient Deep Convolutional Neural Network Inference Processor With Enhanced Output Stationary Dataflow in 65-nm CMOS. 87-100 - Jin Woo Park
, Hyokeun Lee
, Boyeal Kim
, Dong-Goo Kang
, Seung Oh Jin, Hyun Kim
, Hyuk-Jae Lee
:
A Low-Cost and High-Throughput FPGA Implementation of the Retinex Algorithm for Real-Time Video Enhancement. 101-114 - Julian Faraone
, Martin Kumm
, Martin Hardieck, Peter Zipf
, Xueyuan Liu, David Boland
, Philip H. W. Leong
:
AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. 115-128 - Muhammad Asif
, Xiangzhou Guo, Anyong Hu
, Jungang Miao:
An FPGA-Based 1-GHz, 128 × 128 Cross-Correlator for Aperture Synthesis Imaging. 129-141 - Adewale Adetomi
, Godwin Enemali
, Tughrul Arslan:
Enabling Dynamic Communication for Runtime Circuit Relocation. 142-155 - Irith Pomeranz
:
Selection of Primary Output Vectors to Observe Under Multicycle Tests. 156-162 - Pavan Kumar Javvaji
, Spyros Tragoudas:
Test Pattern Generation and Critical Path Selection in the Presence of Statistical Delays. 163-173 - Yizhong Liu
, Tian Song
, Yiqi Zhuang:
A High-Throughput Subspace Pursuit Processor for ECG Recovery in Compressed Sensing Using Square-Root-Free MGS QR Decomposition. 174-187 - Ranendra Kumar Sarma
, Mohd. Tasleem Khan
, Rafi Ahamed Shaik
, Jinti Hazarika
:
A Novel Time-Shared and LUT-Less Pipelined Architecture for LMS Adaptive Filter. 188-197 - Zichen Fan
, Zheyu Liu
, Zheng Qu, Fei Qiao
, Qi Wei
, Xinjun Liu, Yinan Sun
, Shuzheng Xu, Huazhong Yang
:
ASP-SIFT: Using Analog Signal Processing Architecture to Accelerate Keypoint Detection of SIFT Algorithm. 198-211 - A. R. Aravinth Kumar
, Ashudeb Dutta, Bibhu Datta Sahoo
:
A Low-Power Reconfigurable Narrowband/Wideband LNA for Cognitive Radio-Wireless Sensor Network. 212-223 - Tomasz Kulej
, Fabian Khateb
:
A Compact 0.3-V Class AB Bulk-Driven OTA. 224-232 - Huan Yu
, Tim Michalka, Mourad Larbi
, Madhavan Swaminathan:
Behavioral Modeling of Tunable I/O Drivers With Preemphasis Including Power Supply Noise. 233-242 - Dashan Pan
, Chao Ma, Lanqi Cheng, Hao Min
:
A Highly Efficient Conditional Feedthrough Pulsed Flip-Flop for High-Speed Applications. 243-251 - Shan Shen, Tianxiang Shao, Xiaojing Shang, Yichen Guo, Ming Ling
, Jun Yang
, Longxing Shi:
TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply Voltages. 252-262 - Samir Ben Dodo
, Rajendra Bishnoi
, Mehdi Baradaran Tahoori:
Secure STT-MRAM Bit-Cell Design Resilient to Differential Power Analysis Attacks. 263-272 - Roohollah Yarmand, Mehdi Kamal
, Ali Afzali-Kusha
, Massoud Pedram
:
DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy. 273-286 - Morteza Soltani, Mehdi Kamal
, Ali Afzali-Kusha
, Massoud Pedram
:
RandShift: An Energy-Efficient Fault-Tolerant Method in Secure Nonvolatile Main Memory. 287-291 - Chia-Hung Chang
, Wei-Hsien Chen
:
Vital-Sign Processing Receiver With Clutter Elimination Using Servo Feedback Loop for UWB Pulse Radar System. 292-296 - Shokat Ganjeheizadeh Rohani, Nima Taherinejad
, David Radakovits:
A Semiparallel Full-Adder in IMPLY Logic. 297-301 - Dimitrios Konstantinou, Anastasios Psarras
, Chrysostomos Nicopoulos
, Giorgos Dimitrakopoulos
:
The Mesochronous Dual-Clock FIFO Buffer. 302-306
Volume 28, Number 2, February 2020
- Jonathon Edstrom, Hritom Das
, Yiwen Xu, Na Gong
:
Memory Optimization for Energy-Efficient Differentially Private Deep Learning. 307-316 - Mohammad Saeed Ansari
, Vojtech Mrazek
, Bruce F. Cockburn
, Lukás Sekanina, Zdenek Vasícek
, Jie Han
:
Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. 317-328 - Krishna Praveen Yalamarthy, Saurabh Dhall
, Mohd. Tasleem Khan
, Rafi Ahamed Shaik
:
Low-Complexity Distributed-Arithmetic-Based Pipelined Architecture for an LSTM Network. 329-338 - Liting Yu
, Xiaoxiao Wang
, Fahim Rahman
, Mark M. Tehranipoor:
Interconnect-Based PUF With Signature Uniqueness Enhancement. 339-352 - Ahmet Can Mert
, Erdinç Öztürk
, Erkay Savas
:
Design and Implementation of Encryption/Decryption Architectures for BFV Homomorphic Encryption Scheme. 353-362 - Andrew Stern
, Ulbert Botero
, Fahim Rahman
, Domenic Forte
, Mark M. Tehranipoor:
EMFORCED: EM-Based Fingerprinting Framework for Remarked and Cloned Counterfeit IC Detection Using Machine Learning Classification. 363-375 - Thorben Moos
, Amir Moradi
, Bastian Richter:
Static Power Side-Channel Analysis - An Investigation of Measurement Factors. 376-389 - Dong Wang
, Pak Kwong Chan
:
A Sub-1-V 100-mA OCL-LDO Regulator With Process-Temperature-Aware Design for Transient Sustainability. 390-402 - Kan Li
, Xiao Xiao
, Xiangliang Jin
, Yuanjin Zheng
:
A 600-mA, Fast-Transient Low-Dropout Regulator With Pseudo-ESR Technique in 0.18- m CMOS Process. 403-413 - Albert Ciprut
, Eby G. Friedman
:
Distributed Pass Gates in Power Delivery Systems With Digital Low-Dropout Regulators. 414-420 - Liang Chen
, Sheldon X.-D. Tan
, Zeyu Sun
, Shaoyi Peng
, Min Tang
, Junfa Mao
:
Fast Analytic Electromigration Analysis for General Multisegment Interconnect Wires. 421-432 - Iraj Moghaddasi
, Mostafa E. Salehi, Mehdi Kargahi
:
Aging-Aware Instruction-Level Statistical Dynamic Timing Analysis for Embedded Processors. 433-442 - Mohammad Saber Golanbari
, Saman Kiamehr, Fabian Oboril, Anteneh Gebregiorgis
, Mehdi Baradaran Tahoori:
Achieving Energy Efficiency for Near-Threshold Circuits Through Postfabrication Calibration and Adaptation. 443-455 - Sourav Sanyal
, Prabal Basu, Aatreyi Bal
, Sanghamitra Roy
, Koushik Chakraborty
:
Exploring Warp Criticality in Near-Threshold GPGPU Applications Using a Dynamic Choke Point Analysis. 456-466 - Guanghui He
, Xiaoyu Zhang
, Zhuojun Liang:
Algorithm and Architecture of an Efficient MIMO Detector With Cross-Level Parallel Tree-Search. 467-479 - Diwei Li
, Dixian Zhao
:
High-Throughput Low-Power Area-Efficient Outphasing Modulator Based on Unrolled and Pipelined Radix-2 CORDIC. 480-491 - Duo Sheng
, Jun-Wei Lin, Yi-Hsiang Wang
, Chih-Chung Huang:
High-Resolution All-Digital Transmit Beamformer for High-Frequency and Wearable Ultrasound Imaging Systems. 492-502 - James R. Hoff
:
Conflux - An Asynchronous Two-to-One Multiplexor for Time-Division Multiplexing and Clockless, Tokenless Readout. 503-515 - He Li
, James J. Davis
, John Wickerson
, George A. Constantinides:
architect: Arbitrary-Precision Hardware With Digit Elision for Efficient Iterative Compute. 516-529 - Matheus A. Cavalcante
, Fabian Schuiki
, Florian Zaruba
, Michael Schaffner
, Luca Benini
:
Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI. 530-543 - Irith Pomeranz
:
Extra Clocking of LFSR Seeds for Improved Path Delay Fault Coverage. 544-552 - Stavros Hadjitheophanous
, Stelios N. Neophytou
, Maria K. Michael
:
Maintaining Scalability of Test Generation Using Multicore Shared Memory Systems. 553-564 - Rongdi Sun
, Jiuchao Qian
, José Romero Hung
, Zheng Gong
, Ruihang Miao
, Wuyang Xue
, Peilin Liu
:
A Flexible and Efficient Real-Time ORB-Based Full-HD Image Feature Extraction Accelerator. 565-575 - Farah Fahim
, Siddhartha Joshi
, Seda Ogrenci-Memik
, Hooman Mohseni
:
A Low-Power, High-Speed Readout for Pixel Detectors Based on an Arbitration Tree. 576-584 - Mehmet Meric Isgenc
, Mayler G. A. Martins
, V. Mohammed Zackriya
, Samuel N. Pagliarini
, Lawrence T. Pileggi
:
Logic IP for Low-Cost IC Design in Advanced CMOS Nodes. 585-595 - Li Tan
, Zhongcai Li
, Gang Su
, Desheng Wang:
Asymptotically Linear Analysis and Gate Probability Allocation Schemes in Probabilistic Circuits. 596-606
Volume 28, Number 3, March 2020
- Zhiting Lin
, Yong Wang
, Chunyu Peng
, Xiulong Wu
, Xuan Li
, Junning Chen:
Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield. 607-619 - Rui Zhang
, Taizhi Liu
, Kexin Yang
, Chang-Chih Chen, Linda Milor
:
SRAM Stability Analysis and Performance-Reliability Tradeoff for Different Cache Configurations. 620-633 - Shyue-Kung Lu
, Shu-Chi Yu, Chun-Lung Hsu, Chi-Tien Sun, Masaki Hashizume
, Hiroyuki Yotsuyanagi
:
Fault-Aware Dependability Enhancement Techniques for Flash Memories. 634-645 - Andrea Bonetti
, Roman Golman, Robert Giterman, Adam Teman
, Andreas Burg
:
Gain-Cell Embedded DRAMs: Modeling and Design Space. 646-659 - Bo-Cheng Lai
, Bo-Ya Chen, Bo-En Chen
, Yi-Da Hsin:
REMAP+: An Efficient Banking Architecture for Multiple Writes of Algorithmic Memory. 660-671 - Khanh N. Dang
, Akram Ben Ahmed
, Abderazek Ben Abdallah
, Xuan-Tu Tran
:
TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems. 672-685 - Shouvik Musavvir
, Anwesha Chatterjee, Ryan Gary Kim
, Dae Hyun Kim, Partha Pratim Pande
:
Inter-Tier Process-Variation-Aware Monolithic 3-D NoC Design Space Exploration. 686-699 - Nandini Vitee
, Harikrishnan Ramiah
, Pui-In Mak
, Jun Yin
, Rui Paulo Martins
:
A 3.15-mW +16.0-dBm IIP3 22-dB CG Inductively Source Degenerated Balun-LNA Mixer With Integrated Transformer-Based Gate Inductor and IM2 Injection Technique. 700-713 - Pallavi Paliwal
, Vivek Yadav, Zeeshan Ali
, Shalabh Gupta
:
A Fast Settling Fractional-N DPLL With Loop-Order Switching. 714-725 - Yusuke Kanno
, Tadanobu Toba, Kotaro Shimamura
, Nobuyasu Kanekawa
:
Design Method for Online Totally Self-Checking Comparators Implementable on FPGAs. 726-735 - Jin-Tai Yan
:
Single-Layer Delay-Driven GNR Nontree Routing Under Resource Constraint for Yield Improvement. 736-749 - Trevor E. Pogue
, Nicola Nicolici
:
Incremental Fault Analysis: Relaxing the Fault Model of Differential Fault Attacks. 750-763 - Omar Al-Terkawi Hasib
, Yvon Savaria
, Claude Thibeault
:
Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage. 764-776 - Saurabh Jain
, Longyang Lin
, Massimo Alioto
:
Automated Design of Reconfigurable Microarchitectures for Accelerators Under Wide-Voltage Scaling. 777-790 - Yu-Sheng Lin
, Wei-Chao Chen
, Shao-Yi Chien
:
MERIT: Tensor Transform for Memory-Efficient Vision Processing on Parallel Architectures. 791-804 - Tae Hyun Kim
, Hayoung Lee
, Sungho Kang
:
GPU-Based Redundancy Analysis Using Concurrent Evaluation. 805-817 - Jaeyoung Seo
, Jaehyun Ko, Kyunghyun Lim, Sooeun Lee
, Jae-Yoon Sim
, Hong-June Park
, Byungsub Kim
:
A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels. 818-822 - Mohammad Bavandpour
, Shubham Sahay
, Mohammad Reza Mahmoodi
, Dmitri B. Strukov
:
Efficient Mixed-Signal Neurocomputing Via Successive Integration and Rescaling. 823-827 - Mao Ye
, Xiaoxiao Zheng
, Yao Li
, Yiqiang Zhao:
A Low-Complexity Hybrid Readout Circuit for Lidar Receiver. 828-832 - Meera Kumari, S. M. Rezaul Hasan
:
A Low Duty Cycle Burst-Mode Telemeter Signal Generation Technique for VHF Insect Tracking and Its CMOS Implementation. 833-837 - Erfan Bank-Tavakoli, Seyed Abolfazl Ghasemzadeh
, Mehdi Kamal
, Ali Afzali-Kusha
, Massoud Pedram
:
POLAR: A Pipelined/Overlapped FPGA-Based LSTM Accelerator. 838-842 - Shizhong Li
, Kamal El-Sankary
, Alireza Karami
, Dmitri V. Truhachev
:
Area- and Power-Efficient Staircase Encoder Implementation for High-Throughput Fiber-Optical Communications. 843-847 - Qiang Zhao
, Chunyu Peng
, Junning Chen, Zhiting Lin
, Xiulong Wu
:
Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications. 848-852
Volume 28, Number 4, April 2020
- Juan Yepez
, Seok-Bum Ko
:
Stride 2 1-D, 2-D, and 3-D Winograd for Convolutional Neural Networks. 853-863 - Yuxuan Wang
, Yuanyong Luo
, Zhongfeng Wang
, Qinghong Shen, Hongbing Pan
:
GH CORDIC-Based Architecture for Computing $N$ th Root of Single-Precision Floating-Point Number. 864-875 - Avishek Sinha Roy
, Rajdeep Biswas
, Anindya Sundar Dhar:
On Fast and Exact Computation of Error Metrics in Approximate LSB Adders. 876-889 - Ibrahim Ahmed
, Linda L. Shen, Vaughn Betz:
Optimizing FPGA Logic Circuitry for Variable Voltage Supplies. 890-903 - Poki Chen
, Jian-Ting Lan, Ruei-Ting Wang, Nguyen My Qui
, John Carl Joel Salao Marquez
, Seiji Kajihara, Yousuke Miyake
:
High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters. 904-913 - Oscar Garnica
, Juan Lanchares
, José Ignacio Hidalgo
:
Optimal Runtime Algorithm to Improve Fault Tolerance of Bus-Based Reconfigurable Designs. 914-925 - Henry Lopez Davila
, Hsun-Wei Chan, Kang-Lun Chiu, Pei-Yun Tsai
, Shyh-Jye Jou
:
A 75-Gb/s/mm2 and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm. 926-939 - Dong-Yuan Shi
, Woon-Seng Gan
, Jianjun He
, Bhan Lam
:
Practical Implementation of Multichannel Filtered-x Least Mean Square Algorithm Based on the Multiple-Parallel-Branch With Folding Architecture for Large-Scale Active Noise Control. 940-953 - Shervin Roshanisefat
, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
SAT-Hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain. 954-967 - Asmit De
, Mohammad Nasim Imtiaz Khan
, Karthikeyan Nagarajan, Swaroop Ghosh
:
HarTBleed: Using Hardware Trojans for Data Leakage Exploits. 968-979 - Ashish Ranjan
, Arnab Raha
, Vijay Raghunathan
, Anand Raghunathan
:
Approximate Memory Compression. 980-991 - Sayed Ahmad Salehi
:
Low-Cost Stochastic Number Generators for Stochastic Computing. 992-1001 - Binod Kumar
, Jay Adhaduk, Kanad Basu, Masahiro Fujita
, Virendra Singh:
A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug. 1002-1015 - Surajit Das
, Chandan Karfa
, Santosh Biswas
:
Formal Modeling of Network-on-Chip Using CFSM and its Application in Detecting Deadlock. 1016-1029 - Dave Y.-W. Lin
, Charles H.-P. Wen
:
DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction. 1030-1042 - Haoyu Zhuang
, Xiaoxian Liu
, Hao Wang
:
Voltage Reference With Linear-Temperature-Dependent Power Consumption. 1043-1049 - Niranjan Raj, Rajeev Kumar Ranjan
, Fabian Khateb
:
Flux-Controlled Memristor Emulator and Its Experimental Results. 1050-1061 - Saptadeep Pal
, Daniel Petrisko
, Rakesh Kumar, Puneet Gupta
:
Design Space Exploration for Chiplet-Assembly-Based Processors. 1062-1073 - Jie Sun
, Minglei Zhang
, Lei Qiu
, Jianhui Wu
, Weiqiang Liu
:
Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators. 1074-1078 - Juhyun Park
, Tae Woo Oh
, Seong-Ook Jung
:
pMOS Pass Gate Local Bitline SRAM Architecture With Virtual $V_{\mathrm{SS}}$ for Near-Threshold Operation. 1079-1083 - Inayat Ullah
, Joon-Sung Yang
, Jaeyong Chung
:
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs. 1084-1088 - Yuanyuan Han
, Xu Cheng
, Jun Han
, Xiaoyang Zeng:
Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications. 1089-1093 - Chun-Chi Chen
, Chorng-Sii Hwang
, Kai-Hsiang Chang:
All-Digital Cost-Efficient CMOS Digital-to-Time Converter Using Binary-Weighted Pulse Expansion. 1094-1098
Volume 28, Number 5, May 2020
- Chan-Ho Kye, Han-Gon Ko
, Jinhyung Lee
, Deog-Kyoon Jeong
:
A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS. 1099-1106 - Hyochang Kim
, Changsik Yoo
:
A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS. 1107-1117 - Dimitris Theodoropoulos
, Nektarios Kranitis
, Antonis Tsigkanos
, Antonis M. Paschalis:
Efficient Architectures for Multigigabit CCSDS LDPC Encoders. 1118-1127 - Zhongyuan Tian
, Jiang Xu
, Haoran Li
, Rafael Kioji Vivas Maeda
:
Multidevice Collaborative Power Management Through Decentralized Knowledge Sharing. 1128-1140 - Chung-Hsun Huang
, Wei-Chen Liao
:
A High-Performance LDO Regulator Enabling Low-Power SoC With Voltage Scaling Approaches. 1141-1149 - Haoran Li
, Zhongyuan Tian
, Jiang Xu
, Rafael K. V. Maeda
, Zhehui Wang
, Zhifei Wang:
Chip-Specific Power Delivery and Consumption Co-Management for Process-Variation-Aware Manycore Systems Using Reinforcement Learning. 1150-1163 - Nandini Vitee
, Harikrishnan Ramiah
, Pui-In Mak
, Jun Yin
, Rui Paulo Martins
:
A 1-V 4-mW Differential-Folded Mixer With Common-Gate Transconductor Using Multiple Feedback Achieving 18.4-dB Conversion Gain, +12.5-dBm IIP3, and 8.5-dB NF. 1164-1174 - Yang Azevedo Tavares
, Kang-Yoon Lee
, Minjae Lee
:
All-Digital Bandwidth Mismatch Calibration of TI-ADCs Based on Optimally Induced Minimization. 1175-1184 - Alireza Mosalmani
, Mehdi Khoee
, Omid Shoaei
:
A 9-Bit 70-MS/s Two-Stage SAR ADC With Passive Residue Transfer. 1185-1194 - Aili Wang
, Chuanjin Richard Shi
:
Analysis of Passive Charge Sharing-Based Segmented SAR ADCs. 1195-1206