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ORCIDSandeep Gupta 0001
Sandeep K. Gupta 0001
Person information
- affiliation: University of Southern California, Department of Electrical Engineering-Systems, Los Angeles, USA
- affiliation (PhD 1991): University of Massachusetts at Amherst, MA, USA
Other persons with the same name
- Sandeep Gupta — disambiguation page
- Sandeep Gupta 0002
![[0000-0001-9220-7700]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-9220-7700")
— University of Trento, Department of Information Engineering and Computer Science (DISI), Trento, Italy - Sandeep Gupta 0003 — Indian Institute of Technology Kanpur, Department of Electrical Engineering, India
- Sandeep Gupta 0004 — University of California, San Diego, La Jolla, CA, USA (and 3 more)
- Sandeep Gupta 0005 — JECRC University, Jaipur, Rajasthan, India
- Sandeep K. Gupta — disambiguation page
- Sandeep K. Gupta 0002 — Massachusetts Institute of Technology (MIT), Laboratory for Computer Science, Cambridge, MA, USA
- Sandeep K. Gupta 0003 — Teranetics Inc., Santa Clara, CA, USA (and 1 more)
- Sandeep K. Gupta 0004 — University of Alabama at Birmingham, AL, USA (and 2 more)
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2020 – today
- 2024
[j32]Baishakhi Rani Biswas, Claire Yuan, Fangzhou Wang, Sandeep Gupta:
Systematic Generation of Memristor-Transistor Single-Phase Combinational Logic Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 2990-3003 (2024)- [c157]Sasan Razmkhah, Robert S. Aviles, Mingye Li, Sandeep Gupta, Peter A. Beerel, Massoud Pedram:
Challenges and Unexplored Frontiers in Electronic Design Automation for Superconducting Digital Logic. DATE 2024: 1-6 - [c156]Mutian Zhu, Mohsen Hassanpourghadi, Qiaochu Zhang, Mike Shuo-Wei Chen, Anthony F. J. Levi, Sandeep Gupta:
A Novel Multi-Objective Optimization Framework for Analog Circuit Customization. DATE 2024: 1-2 - [c155]Yunkun Lin, Mingye Li, Sandeep Gupta:
Predictive Testing for Aging in SRAMs and Mitigation. ITC 2024: 293-302 - [c154]Qiaochu Zhang, Shiyu Su, Baishakhi Rani Biswas, Sandeep Gupta, Mike Shuo-Wei Chen:
Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder with 0.012mm2 Active Area in 12nm FinFET. VLSI Technology and Circuits 2024: 1-2 - [c153]Mingye Li, Yunkun Lin, Sandeep Gupta:
Built in self test (BIST) for RSFQ circuits. VTS 2024: 1-7 - 2023
- [c152]Mingye Li, Yunkun Lin, Sandeep Gupta:
Design for testability (DFT) for RSFQ circuits. VTS 2023: 1-7 - 2022
- [c151]Feng Yun, Yunkun Lin, Lou Yunfei, Lei Gao, Vaibhav Gera, Boxuan Li, Vennela Chowdary Nekkanti, Aditya Rajendra Pharande, Kunal Sheth, Meghana Thommondru, Guizhong Ye, Sandeep Gupta:
Fault-coverage Maximizing March Tests for Memory Testing. ITC 2022: 529-533 - [c150]Baishakhi Rani Biswas, Sandeep Gupta:
Memristor-Specific Failures: New Verification Methods and Emerging Test Problems. VTS 2022: 1-7 - [c149]Mingye Li, Fangzhou Wang, Sandeep Gupta:
Methods for testing path delay and static faults in RSFQ circuits. VTS 2022: 1-7 - 2021
- [c148]Soowang Park, Jae-Won Nam, Sandeep K. Gupta:
HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large Benchmarks. ASP-DAC 2021: 29-34 - [c147]Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen:
From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD 2021: 1-9 - 2020
- [c146]Mingye Li, Fangzhou Wang, Sandeep Gupta:
Data-driven fault model development for superconducting logic. ITC 2020: 1-5 - [c145]Xuan Zuo, Sandeep K. Gupta:
Aging-resilient SRAM design: an end-to-end framework. VTS 2020: 1-6
2010 – 2019
- 2019
- [j31]Adam Brinckman, Ewa Deelman, Sandeep Gupta, Jarek Nabrzyski, Soowang Park, Rafael Ferreira da Silva, Ian J. Taylor, Karan Vahi:
Collaborative circuit designs using the CRAFT repository. Future Gener. Comput. Syst. 94: 841-853 (2019) - [c144]Fangzhou Wang, Sandeep Gupta:
Multi-cell characterization: Developing robust cells and abstraction for Rapid Single Flux Quantum (RSFQ) Logic. ITC 2019: 1-10 - [c143]Steve Bogol, Paul R. Brenner, Adam Brinckman, Ewa Deelman, Rafael Ferreira da Silva, Sandeep Gupta, Jarek Nabrzyski, Soowang Park, Damian Perez, Mats Rynge, Ian J. Taylor, Karan Vahi, Matt Vander Werf, Sarah Rucker, Sebastian Wyngaard:
A Secure Gateway for Enabling ASIC Design Collaborations. IWSG 2019 - [c142]Soowang Park, Sandeep K. Gupta:
Cache Design for Yield-per-Area Maximization: Switchable Spare Columns with Disabling (SSC-Disable). VTS 2019: 1-6 - [c141]Fangzhou Wang, Sandeep Gupta:
Automatic Test Pattern Generation for timing verification and delay testing of RSFQ circuits. VTS 2019: 1-6 - [c140]Jianwei Zhang, Sandeep K. Gupta, William G. J. Halfond:
A New Method for Software Test Data Generation Inspired by D-algorithm. VTS 2019: 1-6 - 2017
- [c139]Jizhe Zhang, Sandeep K. Gupta:
Wordline overdriving test: An effective predictive testing method for SRAMs against BTI aging. ISQED 2017: 454-459 - [c138]Ian J. Taylor, Adam Brinckman, Ewa Deelman, Rafael Ferreira da Silva, Sandeep Gupta, Jarek Nabrzyski, Soowang Park, Karan Vahi:
Accelerating Circuit Realization via a Collaborative Gateway of Innovations. IWSG 2017 - [c137]Sandeep Gupta, Miron Abramovici, Magdy Abadir, Sridhar Narayanan:
Keynote address tribute to Professor Mel Breuer: Contributions to CAD and Test. VTS 2017: 1 - [c136]Xuan Zuo, Sandeep K. Gupta:
Asymmetric sizing: An effective design approach for SRAM cells against BTI aging. VTS 2017: 1-6 - 2016
- [c135]Jizhe Zhang, Sandeep K. Gupta:
Yield estimation and statistical design of memristor cross-point memory systems. ISQED 2016: 95-100 - [c134]Jianwei Zhang, Sandeep K. Gupta:
Using hardware testing approaches to improve software testing: Undetectable mutant identification. VTS 2016: 1-6 - [c133]Jizhe Zhang, Sandeep K. Gupta:
SRAM yield-per-area optimization under spatially-correlated process variation. VTS 2016: 1-6 - [c132]Xuan Zuo, Sandeep K. Gupta:
Process variation oriented delay testing of SRAMs. VTS 2016: 1-6 - 2015
- [c131]Bowen Zheng, Yue Gao, Qi Zhu, Sandeep K. Gupta:
Analysis and optimization of soft error tolerance strategies for real-time systems. CODES+ISSS 2015: 55-64 - [c130]Da Cheng, Sandeep K. Gupta:
PPB: Partially-working processors binning for maximizing wafer utilization. VTS 2015: 1-6 - [c129]Hsunwei Hsiung, Sandeep K. Gupta:
A multi-layered methodology for defect-tolerance of datapath modules in processors. VTS 2015: 1-6 - 2014
- [j30]Da Cheng, Sandeep K. Gupta:
Maximizing Yield per Area of Highly Parallel CMPs Using Hardware Redundancy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(10): 1545-1558 (2014) - [c128]Da Cheng, Fangzhou Wang, Feng Gao, Sandeep K. Gupta:
Optimal Redundancy Designs for CNFET-Based Circuits. ATS 2014: 25-32 - [c127]Jizhe Zhang, Sandeep Gupta:
SRAM Array Yield Estimation under Spatially-Correlated Process Variation. ATS 2014: 149-155 - [c126]Byeongju Cha, Sandeep K. Gupta:
A Resizing Method to Minimize Effects of Hardware Trojans. ATS 2014: 192-199 - [c125]Yue Gao, Sandeep K. Gupta, Yanzhi Wang, Massoud Pedram:
An energy-aware fault tolerant scheduling framework for soft error resilient cloud computing systems. DATE 2014: 1-6 - [c124]Prasanjeet Das, Sandeep K. Gupta:
Efficient post-silicon validation via segmentation of process variation envelope - Global vs local variations. ISQED 2014: 115-122 - [c123]Da Cheng, Sandeep K. Gupta:
Optimizing redundancy design for chip-multiprocessors for flexible utility functions. ITC 2014: 1-8 - 2013
- [c122]Da Cheng, Hsunwei Hsiung, Bin Liu, Jianing Chen, Jia Zeng, Ramesh Govindan, Sandeep K. Gupta:
A New March Test for Process-Variation Induced Delay Faults in SRAMs. Asian Test Symposium 2013: 115-122 - [c121]Hsunwei Hsiung, Da Cheng, Bin Liu, Ramesh Govindan, Sandeep K. Gupta:
Interplay of Failure Rate, Performance, and Test Cost in TCAM under Process Variations. Asian Test Symposium 2013: 251-258 - [c120]Yue Gao, Yanzhi Wang, Sandeep K. Gupta, Massoud Pedram:
An energy and deadline aware resource provisioning, scheduling and optimization framework for cloud systems. CODES+ISSS 2013: 31:1-31:10 - [c119]Yue Gao, Sandeep K. Gupta, Melvin A. Breuer:
Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors. DATE 2013: 927-932 - [c118]Byeongju Cha, Sandeep K. Gupta:
Trojan detection via delay measurements: a new approach to select paths and vectors to maximize effectiveness and minimize cost. DATE 2013: 1265-1270 - [c117]Prasanjeet Das, Sandeep K. Gupta:
Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits. ICCD 2013: 227-234 - [c116]Prasanjeet Das, Sandeep K. Gupta:
Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning. VTS 2013: 1-6 - 2012
- [c115]Byeongju Cha, Sandeep K. Gupta:
Efficient Trojan Detection via Calibration of Process Variations. Asian Test Symposium 2012: 355-361 - [c114]Hsunwei Hsiung, Byeongju Cha, Sandeep K. Gupta:
Salvaging chips with caches beyond repair. DATE 2012: 1263-1268 - [c113]Da Cheng, Sandeep K. Gupta:
A systematic methodology to improve yield per area of highly-parallel CMPs. DFT 2012: 126-133 - [c112]Bin Liu, Hsunwei Hsiung, Da Cheng, Ramesh Govindan, Sandeep Gupta:
Towards systematic roadmaps for networked systems. HotNets 2012: 91-96 - [c111]Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian:
Theory of redundancy for logic circuits to maximize yield/area. ISQED 2012: 663-671 - [c110]Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta:
A design flow to maximize yield/area of physical devices via redundancy. ITC 2012: 1-10 - 2011
- [c109]Jae Chul Cha, Sandeep K. Gupta:
Yield-per-Area Optimization for 6T-SRAMs Using an Integrated Approach to Exploit Spares and ECC to Efficiently Combat High Defect and Soft-Error Rates. Asian Test Symposium 2011: 126-135 - [c108]Prasanjeet Das, Sandeep K. Gupta:
On Generating Vectors for Accurate Post-Silicon Delay Characterization. Asian Test Symposium 2011: 251-260 - [c107]Doochul Shin, Sandeep K. Gupta:
A new circuit simplification method for error tolerant applications. DATE 2011: 1566-1571 - [c106]Da Cheng, Sandeep Gupta:
A novel software-based defect-tolerance approach for application-specific embedded systems. ICCD 2011: 443-444 - 2010
- [j29]Shamim Begum, Ahmed Helmy, Sandeep Gupta:
Modeling the interactions between MAC and higher layer: A systematic approach to generate high-level scenarios from MAC-layer scenarios. ACM Trans. Model. Comput. Simul. 21(1): 7:1-7:27 (2010) - [c105]Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta:
HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC. Asian Test Symposium 2010: 249-254 - [c104]Doochul Shin, Sandeep K. Gupta:
Approximate logic synthesis for error tolerant applications. DATE 2010: 957-960 - [c103]Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta:
Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules. DATE 2010: 1249-1254 - [c102]Kun Young Chung, Sandeep K. Gupta:
Design and test of latch-based circuits to maximize performance, yield, and delay test quality. ITC 2010: 94-103
2000 – 2009
- 2009
- [j28]Zhigang Jiang, Sandeep K. Gupta:
Threshold Testing: Improving Yield for Nanoscale VLSI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(12): 1883-1895 (2009) - [c101]Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta:
SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement. Asian Test Symposium 2009: 193-199 - [c100]Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee:
Tolerance of performance degrading faults for effective yield improvement. ITC 2009: 1-10 - [c99]Shamim Begum, Ahmed Helmy, Sandeep Gupta:
Modeling and test generation for worst-case performance evaluation of MAC protocols for wireless ad hoc networks. MASCOTS 2009: 1-10 - [c98]Kun Young Chung, Sandeep K. Gupta:
Efficient Scheduling of Path Delay Tests for Latch-Based Circuits. VTS 2009: 103-110 - 2008
- [j27]Jung-Yup Kang, Sandeep K. Gupta, Jean-Luc Gaudiot:
An Efficient Data-Distribution Mechanism in a Processor-In-Memory (PIM) Architecture Applied to Motion Estimation. IEEE Trans. Computers 57(3): 375-388 (2008) - [c97]Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer:
A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults. ATS 2008: 89-96 - [c96]Doochul Shin, Sandeep K. Gupta:
A Re-design Technique for Datapath Modules in Error Tolerant Applications. ATS 2008: 431-437 - [c95]Jae Chul Cha, Sandeep K. Gupta:
Matrix Inversion on a PIM (Processor-in-Memory). CSSE (3) 2008: 419-422 - [c94]Shideh Shahidi, Sandeep Gupta:
Multi-Vector Tests: A Path to Perfect Error-Rate Testing. DATE 2008: 1178-1183 - [c93]Jae Chul Cha, Sandeep K. Gupta:
Characterization of granularity and redundancy for SRAMs for optimal yield-per-area. ICCD 2008: 219-226 - [c92]Jae Chul Cha, Sandeep K. Gupta:
Data Partitioning and Placement Schemes for Matrix Multiplications on a PIM Architecture. ISPDC 2008: 309-316 - [c91]I-De Huang, Yi-Shing Chang, Suriyaprakash Natarajan, Ramesh Sharma, Sandeep K. Gupta:
On Accelerating Path Delay Fault Simulation of Long Test Sequences. ITC 2008: 1-9 - [c90]I-De Huang, Yi-Shing Chang, Sandeep K. Gupta, Sreejit Chakravarty:
An Industrial Case Study of Sticky Path-Delay Faults. VTS 2008: 395-402 - 2007
- [c89]Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer:
Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay Faults. ATS 2007: 57-64 - [c88]I-De Huang, Sandeep K. Gupta:
On Generating Vectors That Invoke High Circuit Delays - Delay Testing and Dynamic Timing Analysis. ATS 2007: 485-492 - [c87]Shamim Begum, Sandeep Gupta, Ahmed Helmy:
Performance Analysis of Wireless MAC Protocols Using a Search Based Framework. MASCOTS 2007: 95-102 - 2006
- [j26]Seongmoon Wang, Sandeep K. Gupta:
LT-RTPG: a new test-per-scan BIST TPG for low switching activity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8): 1565-1574 (2006) - [c86]Lei Wang, Sandeep K. Gupta, Melvin A. Breuer:
Diagnosis of delay faults due to resistive bridges, delay variations and defects. ATS 2006: 215-224 - [c85]Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer:
Test Generation for Weak Resistive Bridges. ATS 2006: 265-272 - [c84]Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer:
STAX: statistical crosstalk target set compaction. DATE Designers' Forum 2006: 172-177 - [c83]Shideh Shahidi, Sandeep K. Gupta:
A theory of Error-Rate Testing. ICCD 2006: 438-445 - [c82]Kun Young Chung, Sandeep K. Gupta:
Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing. VTS 2006: 8-15 - 2005
- [j25]Ahmed Helmy, Sandeep Gupta:
FOTG: fault-oriented stress testing of IP multicast. IEEE Commun. Lett. 9(4): 375-377 (2005) - [c81]Wichian Sirisaengtaksin, Sandeep K. Gupta:
A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects. Asian Test Symposium 2005: 112-119 - [c80]I-De Huang, Sandeep K. Gupta:
Selection of Paths for Delay Testing. Asian Test Symposium 2005: 208-215 - [c79]Zhigang Jiang, Sandeep K. Gupta:
Threshold testing: Covering bridging and other realistic faults. Asian Test Symposium 2005: 390-397 - [c78]Shirin Ebrahimi-Taghizadeh, Ahmed Helmy, Sandeep Gupta:
TCP vs. TCP: a systematic study of adverse impact of short-lived TCP flows on long-lived TCP flows. INFOCOM 2005: 926-937 - [c77]Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer:
Multiple tests for each gate delay fault: higher coverage and lower test application cost. ITC 2005: 9 - 2004
- [j24]Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak:
Defect and Error Tolerance in the Presence of Massive Numbers of Defects. IEEE Des. Test Comput. 21(3): 216-227 (2004) - [j23]Karim Seada, Ahmed Helmy, Sandeep Gupta:
A framework for systematic evaluation of multicast congestion control protocols. IEEE J. Sel. Areas Commun. 22(10): 2048-2061 (2004) - [j22]Ahmed Helmy, Sandeep Gupta, Deborah Estrin:
The STRESS method for boundary-point performance analysis of end-to-end multicast timer-suppression mechanisms. IEEE/ACM Trans. Netw. 12(1): 44-58 (2004) - [c76]Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian:
Efficient Identification of Crosstalk Induced Slowdown Targets. Asian Test Symposium 2004: 124-131 - [c75]Wichian Sirisaengtaksin, Sandeep K. Gupta:
Modeling and Testing Crosstalk Faults in Inter-Core Interconnects that Include Tri-State and Bi-Directional Nets. Asian Test Symposium 2004: 132-139 - [c74]Lei Wang, Sandeep K. Gupta, Melvin A. Breuer:
Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects. Asian Test Symposium 2004: 440-447 - [c73]Jung-Yup Kang, Sandeep Gupta, Jean-Luc Gaudiot:
Accelerating the Kernels of BLAST with an Efficient PIM (Processor-In-Memory) Architecture. CSB 2004: 552-553 - [c72]Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer:
Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models. ITC 2004: 1024-1033 - [c71]Md. Saffat Quasem, Sandeep K. Gupta:
Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip. VTS 2004: 367-376 - 2003
- [j21]Md. Saffat Quasem, Zhigang Jiang, Sandeep K. Gupta:
Benefits of a SoC-Specific Test Methodology. IEEE Des. Test Comput. 20(3): 68-77 (2003) - [c70]Jung-Yup Kang, Sandeep Gupta, Saurabh Shah, Jean-Luc Gaudiot:
An Efficient PIM (Processor-In-Memory) Architecture for Motion Estimation. ASAP 2003: 282-292 - [c69]Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer:
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults. Asian Test Symposium 2003: 174-177 - [c68]Zhigang Jiang, Sandeep K. Gupta:
A Test Generation Approach for Systems-on-Chip that Use Intellectual Property Cores. Asian Test Symposium 2003: 278-283 - [c67]Md. Saffat Quasem, Sandeep K. Gupta:
Designing Multiple Scan Chains for Systems-on-Chip. Asian Test Symposium 2003: 424-427 - [c66]Kun Young Chung, Sandeep K. Gupta:
Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing. ITC 2003: 1089-1097 - [c65]Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer:
Test Generation for Maximizing Ground Bounce Considering Circuit Delay. VTS 2003: 151-157 - [c64]Nabil M. Abdulrazzaq, Sandeep K. Gupta:
Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets. VTS 2003: 186-196 - [c63]Sultan M. Al-Harbi, Sandeep K. Gupta:
Generating Complete and Optimal March Tests for Linked Faults in Memories. VTS 2003: 254-266 - [c62]Shahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta, Melvin A. Breuer:
Analyzing Crosstalk in the Presence of Weak Bridge Defects. VTS 2003: 385-392 - 2002
- [j20]Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer:
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results. J. Electron. Test. 18(1): 17-28 (2002) - [j19]Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
TA-PSV - Timing Analysis for Partially Specified Vectors. J. Electron. Test. 18(1): 73-88 (2002) - [j18]Seongmoon Wang, Sandeep K. Gupta:
DS-LFSR: a BIST TPG for low switching activity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7): 842-851 (2002) - [j17]Seongmoon Wang, Sandeep K. Gupta:
An automatic test pattern generator for minimizing switching activity during scan testing activity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8): 954-968 (2002) - [j16]Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer:
Analytical models for crosstalk excitation and propagation in VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1117-1131 (2002) - [c61]Wichian Sirisaengtaksin, Sandeep K. Gupta:
Enhanced Crosstalk Fault Model and Methodology to Generate Tests for Arbitrary Inter-core Interconnect Topology. Asian Test Symposium 2002: 163-169 - [c60]I-De Huang, Sandeep K. Gupta, Melvin A. Breuer:
Accurate and Efficient Static Timing Analysis with Crosstalk. ICCD 2002: 265-272 - [c59]Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer:
XIDEN: Crosstalk Target Identification Framework. ITC 2002: 365-374 - [c58]Zhigang Jiang, Sandeep K. Gupta:
An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes. ITC 2002: 824-833 - [i3]Ahmed Helmy, Sandeep Gupta, Deborah Estrin:
The STRESS Method for Boundary-point Performance Analysis of End-to-end Multicast Timer-Suppression Mechanisms. CoRR cs.NI/0208023 (2002) - 2001
- [j15]Pankaj Pant, Yuan-Chieh Hsu, Sandeep K. Gupta, Abhijit Chatterjee:
Path delay fault diagnosis in combinational circuits with implicitfault enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(10): 1226-1235 (2001) - [j14]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Introducing redundant computations in RTL data paths for reducing BIST resources. ACM Trans. Design Autom. Electr. Syst. 6(3): 423-445 (2001) - [c57]Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
A New Gate Delay Model for Simultaneous Switching and Its Applications. DAC 2001: 289-294 - [c56]Md. Saffat Quasem, Sandeep K. Gupta:
Exact fault simulation for systems on Silicon that protects each core's intellectual property. DATE 2001: 804 - [c55]Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer:
Switch-level delay test of domino logic circuits. ITC 2001: 367-376 - [c54]Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer:
Crosstalk test generation on pseudo industrial circuits: a case study. ITC 2001: 548-557 - [c53]Sultan M. Al-Harbi, Sandeep K. Gupta:
An Efficient Methodology for Generating Optimal and Uniform March Tests. VTS 2001: 231-239 - [c52]Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer:
Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out. VTS 2001: 358-367 - 2000
- [j13]Chen-Huan Chiang, Sandeep K. Gupta:
BIST TPG for Combinational Cluster Interconnect Testing at Board Level. J. Electron. Test. 16(5): 427-442 (2000) - [j12]Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer:
Novel Test Pattern Generators for Pseudoexhaustive Testing. IEEE Trans. Computers 49(11): 1228-1240 (2000) - [c51]Chen-Huan Chiang, Sandeep K. Gupta:
BIST TPG for SRAM cluster interconnect testing at board level. Asian Test Symposium 2000: 58-65 - [c50]Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
A new framework for static timing analysis, incremental timing refinement, and timing simulation. Asian Test Symposium 2000: 102-107 - [c49]Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer:
Test generation for crosstalk-induced faults: framework and computational result. Asian Test Symposium 2000: 305-310 - [c48]Ahmed Helmy, Sandeep Gupta, Deborah Estrin, Alberto Cerpa, Yan Yu:
Systematic Performance Evaluation of Multipoint Protocols. FORTE 2000: 189-204 - [c47]Ahmed Helmy, Deborah Estrin, Sandeep Gupta:
Systematic testing of multicast routing protocols: analysis of forward and backward search techniques. ICCCN 2000: 590-597 - [c46]Nabil M. Abdulrazzaq, Sandeep K. Gupta:
Test generation for path-delay faults in one-dimensional iterative logic arrays. ITC 2000: 326-335 - [c45]Shamim Begum, Meeta Sharma, Ahmed Helmy, Sandeep Gupta:
Systematic Testing of Protocol Robustness: Case Studies on Mobile IP and MARS. LCN 2000: 369-380 - [c44]Melvin A. Breuer, Sandeep K. Gupta:
New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits. VLSI Design 2000: 8 - [c43]Hugo Cheung, Sandeep K. Gupta:
A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study. VTS 2000: 89-96 - [i2]Ahmed Helmy, Sandeep Gupta, Deborah Estrin, Alberto Cerpa, Yan Yu:
Systematic Performance Evaluation of Multipoint Protocols. CoRR cs.NI/0006029 (2000) - [i1]Ahmed Helmy, Deborah Estrin, Sandeep Gupta:
Systematic Testing of Multicast Routing Protocols: Analysis of Forward and Backward Search Techniques. CoRR cs.NI/0007005 (2000)
1990 – 1999
- 1999
- [c42]Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer:
Validation and test generation for oscillatory noise in VLSI interconnects. ICCAD 1999: 289-296 - [c41]Seongmoon Wang, Sandeep K. Gupta:
LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation. ITC 1999: 85-94 - [c40]Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer:
Switch-level delay test. ITC 1999: 171-180 - [c39]Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer:
Test generation for crosstalk-induced delay in integrated circuits. ITC 1999: 191-200 - [c38]Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer:
Test Generation for Ground Bounce in Internal Logic Circuitry. VTS 1999: 95-105 - 1998
- [j11]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Allocation Techniques for Reducing BIST Area Overhead of Data Paths. J. Electron. Test. 13(2): 149-166 (1998) - [j10]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Estimation of BIST Resources During High-Level Synthesis. J. Electron. Test. 13(3): 221-237 (1998) - [j9]Seongmoon Wang, Sandeep K. Gupta:
ATPG for Heat Dissipation Minimization During Test Application. IEEE Trans. Computers 47(2): 256-262 (1998) - [j8]Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer:
Bounds on pseudoexhaustive test lengths. IEEE Trans. Very Large Scale Integr. Syst. 6(3): 420-431 (1998) - [c37]Yuan-Chieh Hsu, Sandeep K. Gupta:
An Automatic Test Pattern Generator for At-Speed Robust Path Delay Testing. Asian Test Symposium 1998: 88-95 - [c36]Chen-Huan Chiang, Sandeep K. Gupta:
BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level. Asian Test Symposium 1998: 244-252 - [c35]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Introducing Redundant Computations in a Behavior for Reducing BIST Resources. DAC 1998: 548-553 - [c34]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Scheduling and Module Assignment for Reducing Bist Resources. DATE 1998: 66-73 - [c33]Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta:
Process Variations and their Impact on Circuit Operation. DFT 1998: 73- - [c32]Ahmed Helmy, Deborah Estrin, Sandeep Gupta:
Fault-oriented Test Generation for Multicast Routing Protocol Design. FORTE 1998: 93-109 - [c31]Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer:
Test generation in VLSI circuits for crosstalk noise. ITC 1998: 641-650 - [c30]Yuan-Chieh Hsu, Sandeep K. Gupta:
A new path-oriented effect-cause methodology to diagnose delay failures. ITC 1998: 758-767 - [c29]Sultan M. Al-Harbi, Sandeep K. Gupta:
A Methodology for Transforming Memory Tests for In-System Testing of Direct Mapped Cache Tags. VTS 1998: 394-400 - 1997
- [c28]Seongmoon Wang, Sandeep K. Gupta:
ATPG for Heat Dissipation Minimization During Scan Testing. DAC 1997: 614-619 - [c27]Chen-Huan Chiang, Sandeep K. Gupta:
BIST TPG for faults in system backplanes. ICCAD 1997: 406-413 - [c26]Weiyu Chen, Melvin A. Breuer, Sandeep K. Gupta:
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs. ITC 1997: 809-818 - [c25]Seongmoon Wang, Sandeep K. Gupta:
DS-LFSR: A New BIST TPG for Low Heat Dissipation. ITC 1997: 848-857 - [c24]Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
High Quality Robust Tests for Path Delay Faults. VTS 1997: 88-93 - [c23]Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer:
Analysis of Ground Bounce in Deep Sub-Micron Circuits. VTS 1997: 110-116 - [c22]Chen-Huan Chiang, Sandeep K. Gupta:
BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. VTS 1997: 376-383 - 1996
- [j7]Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta:
Fault macromodeling and a testing strategy for opamps. J. Electron. Test. 9(3): 225-235 (1996) - [j6]Sandeep K. Gupta, Dhiraj K. Pradhan:
Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa. IEEE Trans. Computers 45(1): 63-73 (1996) - [j5]Chih-Ang Chen, Sandeep K. Gupta:
BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms. IEEE Trans. Computers 45(3): 257-269 (1996) - [j4]Yuan-Chieh Hsu, Sandeep K. Gupta:
A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits. IEEE Trans. Computers 45(11): 1312-1318 (1996) - [c21]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Lower Bounds on Test Resources for Scheduled Data Flow Graphs. DAC 1996: 143-148 - [c20]Chih-Ang Chen, Sandeep K. Gupta:
A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts. DAC 1996: 209-214 - [c19]Melvin A. Breuer, Sandeep K. Gupta:
Process-Aggravated Noise (PAN): New Validation and Test Problems. ITC 1996: 914-923 - [c18]Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma:
Delay Fault Testing: How Robust are Our Models? VTS 1996: 502-503 - 1995
- [j3]Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer:
Test embedding with discrete logarithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5): 554-566 (1995) - [c17]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. DAC 1995: 395-401 - 1994
- [c16]Wen-Chang Fang, Sandeep K. Gupta:
Clock Grouping: A Low Cost DFT Methodology for Delay Testing. DAC 1994: 94-99 - [c15]Sen-Pin Lin, Sandeep K. Gupta, Melvin A. Breuer:
A Low Cost BIST Methodology and Associated Novel Test Pattern Generator. EDAC-ETC-EUROASIC 1994: 106-112 - [c14]Chih-Ang Chen, Sandeep K. Gupta:
BIST Test Pattern Generators for Stuck-Open and Delay Testing. EDAC-ETC-EUROASIC 1994: 289-296 - [c13]Chen-Huan Chiang, Sandeep K. Gupta:
Random pattern testable logic synthesis. ICCAD 1994: 125-128 - [c12]Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta:
A comprehensive fault macromodel for opamps. ICCAD 1994: 344-348 - [c11]Seongmoon Wang, Sandeep K. Gupta:
ATPG for Heat Dissipation Minimization During Test Application. ITC 1994: 250-258 - [c10]Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer:
Test embedding with discrete logarithms. VTS 1994: 74-80 - [c9]Weili Wang, Sandeep K. Gupta:
Weighted random robust path delay testing of synthesized multilevel circuits. VTS 1994: 291-297 - 1993
- [c8]Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer:
An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing. DAC 1993: 242-248 - [c7]Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer:
Novel Test Pattern Generators for Pseudo-Exhaustive Testing. ITC 1993: 1041-1050 - 1992
- [c6]Sandeep K. Gupta, Dhiraj K. Pradhan:
Can Concurrent Checkers Help BIST? ITC 1992: 140-150 - [c5]Sandeep K. Gupta:
Recent advances in BIST. VTS 1992: 235-240 - 1991
- [j2]Dhiraj K. Pradhan, Sandeep K. Gupta:
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression. IEEE Trans. Computers 40(6): 743-763 (1991) - [c4]Mark G. Karpovsky, Sandeep K. Gupta, Dhiraj K. Pradhan:
Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model. ITC 1991: 828-839 - 1990
- [j1]Dhiraj K. Pradhan, Sandeep K. Gupta, Mark G. Karpovsky:
Aliasing Probability for Multiple Input Signature Analyzer. IEEE Trans. Computers 39(4): 586-591 (1990) - [c3]Sandeep K. Gupta, Dhiraj K. Pradhan, Sudhakar M. Reddy:
Zero aliasing compression. FTCS 1990: 254-263
1980 – 1989
- 1988
- [c2]Sandeep K. Gupta, Dhiraj K. Pradhan:
A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability. ITC 1988: 329-342 - [c1]Sandeep K. Gupta, Melvin A. Breuer, Jung-Cheun Lien:
Concurrent Control of Multiple BIT Structures. ITC 1988: 431-442
Coauthor Index
[c119] [c111] [c110] [c105] [c103] [c101] [c100] [c97] [c89] [c86] [c85] [c84] [c77] [j24] [c76] [c74] [c72] [c69] [c65] [c62] [j20] [j19] [j16] [c60] [c59] [j14] [c57] [c55] [c54] [c52] [j12] [c50] [c49] [c44] [c42] [c40] [c39] [c38] [j11] [j10] [j8] [c35] [c34] [c33] [c31] [c26] [c24] [c23] [c21] [c19] [j3] [c17] [c15] [c10] [c8] [c7] [c1]
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