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ORCIDASP-DAC 2006: Yokohama, Japan
- Fumiyasu Hirose:
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006. IEEE 2006, ISBN 0-7803-9451-8
Keynote address I
- Alberto L. Sangiovanni-Vincentelli:
Automotive electronics: steady growth for years to come!
Keynote address II
- Satoru Ito:
Challenging device innovation.
Keynote address III
- Yukichi Niwa:
Effective platform-based development for large-scale systems design.
Formal methods for coverage and scalable verification
- Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya:
Transition-based coverage estimation for symbolic model checking. 1-6 - Bijan Alizadeh:
Word level functional coverage computation. 7-12 - Prasenjit Basu, Sayantan Das, Pallab Dasgupta, Partha Pratim Chakrabarti:
Discovering the input assumptions in specification refinement coverage. 13-18 - Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah:
Refinement strategies for verification methods based on datapath abstraction. 19-24 - Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng
, John Moondanos, Ziyad Hanna:
Generation of shorter sequences for high resolution error diagnosis using sequential SAT. 25-29
Interconnect for high-end SoC
- Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane:
Constraint-driven bus matrix synthesis for MPSoC. 30-35 - Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz:
Improving routing efficiency for network-on-chip through contention-aware input selection. 36-41 - Jin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor:
Physical design implementation of segmented buses to reduce communication energy. 42-47 - Mário P. Véstias, Horácio C. Neto:
Co-synthesis of a configurable SoC platform based on a network on chip architecture. 48-53 - Muhammad Omer Cheema, Omar Hammami:
Customized SIMD unit synthesis for system on programmable chip: a foundation for HW/SW partitioning with vectorization. 54-60
Timing analysis and optimization
- Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan:
Robust analytical gate delay modeling for low voltage circuits. 61-66 - Shahin Nazarian, Massoud Pedram, Tao Lin, Emre Tuncer:
CGTA: current gain-based timing analysis for logic cells. 67-72 - Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton:
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. 73-78 - Sachin Shrivastava, Rajendra Pratap, Harindranath Parameswaran, Manuj Verma:
Crosstalk analysis using reconvergence correlation. 79-83 - Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown:
Process-induced skew reduction in nominal zero-skew clock trees. 84-89
University design contest
- Tadayoshi Enomoto, Nobuaki Kobayashi:
A low dynamic power and low leakage power 90-nm CMOS square-root circuit. 90-91 - Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, C.-J. Richard Shi:
A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits. 92-93 - Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Richard B. Brown:
A 16-bit, low-power microsystem with monolithic MEMS-LC clocking. 94-95 - Chi-Ying Tsui, Hui Shao, Wing-Hung Ki, Feng Su:
Ultra-low voltage power management circuit and computation methodology for energy harvesting applications. 96-97 - Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai:
A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression. 98-99 - Fangqing Chu, Wei Li, Junyan Ren:
An implementation of a CMOS down-conversion mixer for GSM1900 receiver. 100-101 - Yat-Hei Lam, Suet-Chui Koon, Wing-Hung Ki, Chi-Ying Tsui:
Integrated direct output current control switching converter using symmetrically-matched self-biased current sensors. 102-103 - Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui:
Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback. 104-105 - Mitsuya Fukazawa, Koichiro Noguchi, Makoto Nagata, Kazuo Taki:
A built-in power supply noise probe for digital LSIs. 106-107 - Minoru Watanabe, Fuminori Kobayashi:
A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology. 108-109 - Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera:
Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices. 110-111 - Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto:
High-throughput decoder for low-density parity-check code. 112-113 - Nursani Rahmatullah, Arif E. Nugroho:
Hardware implementation of super minimum all digital FM demodulator. 114-115 - Bita Gorjiara, Mehrdad Reshadi, Daniel D. Gajski:
Designing a custom architecture for DCT using NISC technology. 116-117 - Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen:
A 52mW 1200MIPS compact DSP for multi-core media SoC. 118-119 - Suh Ho Lee, Ji Hwan Park, Seon Wook Kim, Sung-Jea Ko, Suki Kim:
Implementation of H.264/AVC decoder for mobile video applications. 120-121 - Min Wu, Xiaoyang Zeng, Jun Han, Yongyi Wu, Yibo Fan:
A high-performance platform-based SoC for information security. 122-123 - Tsutomu Nishimura, Takuji Miki, Hiroaki Sugiura, Yuki Matsumoto, Masatsugu Kobayashi, Toshiyuki Kato, Tsutomu Eda, Hironori Yamauchi:
Configurable multi-processor architecture and its processor element design. 124-125 - Hansu Cho, Samar Abdi, Daniel Gajski:
Design and implementation of transducer for ARM-TMS communication. 126-127
Software techniques for efficient SoC design
- Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir, Feihui Li:
Energy savings through embedded processing on disk system. 128-133 - Guilin Chen, Mahmut T. Kandemir, Feihui Li:
Energy-aware computation duplication for improving reliability in embedded chip multiprocessors. 134-139 - Guilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
Object duplication for improving reliability. 140-145 - Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli:
Mapping and configuration methods for multi-use-case networks on chips. 146-151 - Hyeyoung Hwang, Taewook Oh, Hyunuk Jung, Soonhoi Ha:
Conversion of reference C code to dataflow model: H.264 encoder case study. 152-157
Application examples with leading edge design methodology
- Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh:
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. 158-163 - Robert D. Mullins, Andrew West, Simon W. Moore:
The design and implementation of a low-latency on-chip network. 164-169 - Shen-Yu Shih, Cheng-Ru Chang, Youn-Long Lin:
A near optimal deblocking filter for H.264 advanced video coding. 170-175 - Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch:
Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. 176-181 - Ismail Kadayif, Mahmut T. Kandemir, Feihui Li:
Prefetching-aware cache line turnoff for saving leakage energy. 182-187
Placement
- Jason Cong, Min Xie:
A robust detailed placement for mixed-size IC designs. 188-194 - Natarajan Viswanathan, Min Pan, Chris C. N. Chu:
FastPlace 2.0: an efficient analytical placer for mixed-mode designs. 195-200 - Chanseok Hwang, Massoud Pedram:
Timing-driven placement based on monotone cell ordering constraints. 201-206 - Jinjun Xiong, Yiu-Chung Wong, Egino Sarto, Lei He:
Constraint driven I/O planning and placement for chip-package co-design. 207-212 - Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang:
Simultaneous block and I/O buffer floorplanning for flip-chip design. 213-218
Special session: electrothermal design of nanoscale integrated circuits
- Yong Zhan, Brent Goplen, Sachin S. Sapatnekar:
Electrothermal analysis and optimization techniques for nanoscale integrated circuits. 219-222 - Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava:
Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. 223-230 - Ja Chun Ku, Yehea I. Ismail:
Area optimization for leakage reduction and thermal stability in nanometer scale technologies. 231-236 - Aditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy:
Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. 237-242
Logic Synthesis
- Neil Kettle, Andy King:
An anytime symmetry detection algorithm for ROBDDs. 243-248 - Ming-Hong Su, Chun-Yao Wang:
High level equivalence symmetric input identification. 249-253 - Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh:
Fast multi-domain clock skew scheduling for peak current reduction. 254-259 - Bakhtiar Affendi Rosdi, Atsushi Takahashi:
Low area pipelined circuits by multi-clock cycle paths and clock scheduling. 260-265 - Shigeru Yamashita, Katsunori Tanaka, Hideyuki Takada, Koji Obata, Kazuyoshi Takagi:
A transduction-based framework to synthesize RSFQ circuits. 266-272
Future technical directions for design automation
- Xiaolue Lai, Jaijeet S. Roychowdhury:
Fast simulation of large networks of nanotechnological and biochemical oscillators for investigating self-organization phenomena. 273-278 - Michael S. McCorquodale, James McCann, Richard B. Brown:
Newton: a library-based analytical synthesis tool for RF-MEMS resonators. 279-284 - Qingqi Dou, Jacob A. Abraham:
Jitter decomposition in ring oscillators. 285-290 - Prashant Goyal, Xiaolue Lai, Jaijeet S. Roychowdhury:
A fast methodology for first-time-correct design of PLLs using nonlinear phase-domain VCO macromodels. 291-296 - S. H. Rasouli, Amir Amirabadi, A. Seyedi, Ali Afzali-Kusha:
Double edge triggered Feedback Flip-Flop in sub 100NM technology. 297-302
Routing and interconnect optimization
- Kuang-Yao Lee, Ting-Chi Wang:
Post-routing redundant via insertion for yield/reliability improvement. 303-308 - Tianpei Zhang, Yong Zhan, Sachin S. Sapatnekar:
Temperature-aware routing in 3D ICs. 309-314 - Sebastian Vogel, Martin D. F. Wong:
Closed form solution for optimal buffer sizing using the Weierstrass elliptic function. 315-319 - Zhuo Li, Weiping Shi:
An O(mn) time algorithm for optimal buffer insertion of nets with m sinks. 320-325 - Man Chung Hon:
Spec-based flip-flop and latch repeater planning. 326-331
Special session: flash memory in embedded systems
- Sang Lyul Min, Eyee Hyun Nam:
Current trends in flash memory technology: invited paper. 332-333 - Tei-Wei Kuo, Jen-Wei Hsieh, Li-Pin Chang, Yuan-Hao Chang:
Configurability of performance and overheads in flash management. 334-341
Resolving timing issues: design and test
- Noriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara, Chihiro Endoh, Masahiro Yanagida, Takeshi Kono, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi:
Delay defect screening for a 2.16GHz SPARC64 microprocessor. 342-347 - Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato:
A dynamic test compaction procedure for high-quality path delay testing. 348-353 - Kai-Chiang Wu, Cheng-Tao Hsieh, Shih-Chieh Chang:
Delay variation tolerance for domino circuits. 354-359 - Kai Yang, Kwang-Ting Cheng:
Efficient identification of multi-cycle false path. 360-365 - Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen:
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. 366-371
Leading edge design methodology for SoCs and SiPs
- Marius Bonaciu, Aimen Bouchhima, Mohamed-Wassim Youssef, Xi Chen, Wander O. Cesário, Ahmed Amine Jerraya:
High-level architecture exploration for MPEG4 encoder with custom parameters. 372-377 - Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Programmable numerical function generators based on quadratic approximation: architecture and synthesis method. 378-383 - Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang:
An automated design flow for 3D microarchitecture evaluation. 384-389 - Ozcan Ozturk, Feng Wang, Mahmut T. Kandemir, Yuan Xie:
Optimal topology exploration for application-specific 3D architectures. 390-395 - Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos:
Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems. 396-401
Advanced circuit simulation
- Zhao Li, C.-J. Richard Shi:
A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings. 402-407 - Kiyotaka Yamamura, Wataru Kuroki:
An efficient and globally convergent homotopy method for finding DC operating points of nonlinear circuits. 408-415 - Baohua Wang, Pinaki Mazumder:
Optimization of circuit trajectories: an auxiliary network approach. 416-421 - Jitesh Jain, Stephen Cauley, Cheng-Kok Koh, Venkataramanan Balakrishnan:
SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices. 422-427 - Zhengyong Zhu, Rui Shi, Chung-Kuan Cheng, Ernest S. Kuh:
An unconditional stable general operator splitting method for transistor level transient analysis. 428-433
Special session: open access overview
- Michaela Guiney, Eric Leavitt:
An introduction to OpenAccess: an open source data model and API for IC design. 434-436 - Yoshio Inoue:
Open access overview "industrial experience". 437-438 - Hillel Ofek:
EDA vendor adoption. 439 - David A. Papa, Igor L. Markov, Philip Chong:
Utility of the OpenAccess database in academic research. 440-441
Advances in simulation technologies
- Ilya Wagner, Valeria Bertacco, Todd M. Austin:
Depth-driven verification of simultaneous interfaces. 442-447 - Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou:
FSM-based transaction-level functional coverage for interface compliance verification. 448-453 - Nobuyuki Ohba, Kohji Takano:
Hardware debugging method based on signal transitions and transactions. 454-459 - Junghee Lee, Joonhwan Yi:
Cycle error correction in asynchronous clock modeling for cycle-based simulation. 460-465 - Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A fast logic simulator using a look up table cascade emulator. 466-472
Scheduling for embedded systems
- Peng Rong, Massoud Pedram:
Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system. 473-478 - Ernesto Wandeler, Lothar Thiele:
Optimal TDMA time slot and cycle length allocation for hard real-time systems. 479-484 - Hector Posadas, Jesús Ádamez, Pablo Sánchez, Eugenio Villar, Francisco Blasco:
POSIX modeling in SystemC. 485-490 - Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt:
PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures. 491-496 - Hyunok Oh, Nikil D. Dutt, Soonhoi Ha:
Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs. 497-502
High frequency interconnect effects in nanometer technology
- Sean X. Shi, David Z. Pan:
Wire sizing with scattering effect for nanoscale interconnection. 503-508 - Ya-Chi Yang, Cheng-Kok Koh, Venkataramanan Balakrishnan:
Adaptive admittance-based conductor meshing for interconnect analysis. 509-514 - Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Interconnect RL extraction at a single representative frequency. 515-520 - Mengsheng Zhang, Wenjian Yu, Yu Du, Zeyi Wang:
An efficient algorithm for 3-D reluctance extraction considering high frequency effect. 521-526 - Xiaolue Lai, Jaijeet S. Roychowdhury:
Macromodelling oscillators using Krylov-subspace methods. 527-532
Designers' forum: low power design
- Takeshi Kitahara, Hiroyuki Hara, Shinichiro Shiratake, Yoshiki Tsukiboshi, Tomoyuki Yoda, Tetsuaki Utsumi, Fumihiro Minami:
Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems. 533-540 - Satoshi Imai, Atsuki Inoue, Motoaki Matsumura, Kenichi Kawasaki, Atsuhiro Suga:
Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise. 541-546 - Masafumi Onouchi, Tetsuya Yamada, Kimihiro Morikawa, Isamu Mochizuki, Hidetoshi Sekine:
A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation. 547-550 - Ikhwan Lee, Hyunsuk Kim, Peng Yang, Sungjoo Yoo, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo:
PowerViP: Soc power estimation framework at transaction level. 551-558
Power optimization of large-scale circuits
- Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. 559-564 - Hyung-Ock Kim, Youngsoo Shin:
Analysis and optimization of gate leakage current of power gating circuits. 565-569 - Naoaki Ohkubo, Kimiyoshi Usami:
Delay modeling and static timing analysis for MTCMOS circuits. 570-575 - Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang:
Switching-activity driven gate sizing and Vth assignment for low power design. 576-581 - Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong:
Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs. 582-587
Advanced memory and processor architectures for MPSoC
- Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae:
Reusable component IP design using refinement-based design environment. 588-593