default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID22nd ETS 2017: Limassol, Cyprus
- 22nd IEEE European Test Symposium, ETS 2017, Limassol, Cyprus, May 22-26, 2017. IEEE 2017, ISBN 978-1-5090-5457-2
- Maria K. Michael, Rolf Drechsler
, Stephan Eggersglüß, Haralampos-G. D. Stratigopoulos, Sybille Hellebrand, Rob Aitken:
Foreword. 1-2 - Bernd Becker, Adit D. Singh:
Best paper. 1 - Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell, Keshav Singh:
Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions. 1-2 - Elena Ioana Vatajelu, Rosa Rodríguez-Montañés, Michel Renovell, Joan Figueras:
Mitigating read & write errors in STT-MRAM memories under DVS. 1-2 - Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Extension of power supply impedance emulation method on ATE for multiple power domain. 1-2 - Siavoosh Payandeh Azad, Behrad Niazmand, Apneet Kaur Sandhu, Jaan Raik, Gert Jervan, Thomas Hollstein:
Automated area and coverage optimization of minimal latency checkers. 1-2 - Enrico Fraccaroli, Luca Piccolboni, Franco Fummi:
A homogeneous framework for AMS languages instrumentation, abstraction and simulation. 1-2 - Ingrid Kovacs, Marina Dana Topa, Andi Buzo, Georg Pelz:
Integrated circuits' characterization for non-normal data in semiconductor quality analysis. 1-2 - Hani Malloug, Manuel J. Barragan Asian, Salvador Mir, Laurent Basteres, Hervé Le Gall:
Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology. 1-6 - Nektar Xama, Anthony Coyette, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen:
Automatic testing of analog ICs for latent defects using topology modification. 1-6 - Maryam Shafiee, Sule Ozev:
Contact-less near-field measurement of RF phased array antenna mismatches. 1-6 - Nour Sayed, Fabian Oboril, Azadeh Shirvanian, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Exploiting STT-MRAM for approximate computing. 1-6 - Suvadeep Banerjee, Abhijit Chatterjee:
Real-time self-learning for control law adaptation in nonlinear systems using encoded check states. 1-6 - Amir Charif, Nacer-Eddine Zergainoh, Alexandre Coelho, Michael Nicolaidis:
Rout3D: A lightweight adaptive routing algorithm for tolerating faulty vertical links in 3D-NoCs. 1-6 - Jan Schat:
ISO26262-compliant soft-error mitigation in register banks. 1-2 - Yiorgos Tsiatouhas:
Periodic Bias-Temperature Instability monitoring in SRAM cells. 1-2 - Michele Portolan, Manuel J. Barragán, Rshdee Alhakim, Salvador Mir:
Mixed-signal BIST computation offloading using IEEE 1687. 1-2 - Naghmeh Karimi, Jean-Luc Danger, Mariem Slimani, Sylvain Guilley:
Impact of the switching activity on the aging of delay-PUFs. 1-2 - Mohamed A. Abufalgha, Alex Bystrov:
Derivation of the reliability metric for digital circuits. 1-2 - Baris Esen, Anthony Coyette, Nektar Xama, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen:
A very low cost and highly parallel DfT method for analog and mixed-signal circuits. 1-2 - Marcus Wagner, Hans-Joachim Wunderlich:
Probabilistic sensitization analysis for variation-aware path delay fault test evaluation. 1-6 - Peter C. Maxwell, Friedrich Hapke, Maija Ryynaenen, Peter Weseloh:
Bridge over troubled waters: Critical area based pattern generation. 1-6 - Mohammad Saber Golanbari, Nour Sayed, Mojtaba Ebrahimi, Mohammad Hadi Moshrefpour Esfahany, Saman Kiamehr, Mehdi Baradaran Tahoori:
Aging-aware coding scheme for memory arrays. 1-6 - Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
ROM fault diagnosis for O(n2) test algorithms. 1-6 - Ilia Polian, Francesco Regazzoni:
Counteracting malicious faults in cryptographic circuits. 1-10 - Ben Niewenhuis, Soumya Mittal, R. D. (Shawn) Blanton:
Multiple-defect diagnosis for Logic Characterization Vehicles. 1-6 - Tong Guan, Zhaobo Zhang, Wen Dong, Chunming Qiao, Xinli Gu:
Data-driven fault diagnosis with missing syndromes imputation for functional test through conditional specification. 1-6 - Marcelino Seif, Emna Farjallah, Franck Badets, Emna Chabchoub, Christophe Layer, Jean-Marc Armani, Francis Joffre, Costin Anghel, Luigi Dilillo, Valentin Gherman:
Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps. 1-6 - Rasool Sharifi, Zainalabedin Navabi:
Online Profiling for cluster-specific variable rate refreshing in high-density DRAM systems. 1-6 - Angelos Antonopoulos, Christiana Kapatsori, Yiorgos Makris:
Security and trust in the analog/mixed-signal/RF domain: A survey and a perspective. 1-10 - Tareq Muhammad Supon, Rashid Rashidzadeh:
A phase locking test solution for MEMS devices. 1-6 - Sebastian Simon, Deeksha Bhat, Alexander W. Rath, Jérôme Kirscher, Linus Maurer:
Coverage-driven mixed-signal verification of smart power ICs in a UVM environment. 1-6 - Wu-Tung Cheng, Yue Tian, Sudhakar M. Reddy:
Volume diagnosis data mining. 1-10 - Mauricio D. Gutierrez, Vasileios Tenentes, Tom J. Kazmierski, Daniele Rossi:
Low power probabilistic online monitoring of systematic erroneous behaviour. 1-2 - Ioannis Voyiatzis:
SIC pair generation in optimal time using rotatable counters. 1-2 - Satyadev Ahlawat, Darshit Vaghani, Virendra Singh:
An efficient test technique to prevent scan-based side-channel attacks. 1-2 - Ciprian V. Pop, Corneliu Burileanu, Andi Buzo, Georg Pelz:
Application-aware lifetime estimation of power devices. 1-2 - Andreina Zambrano, Hans G. Kerkhoff:
Improving the dependability of AMR sensors used in automotive applications. 1-2 - Ondrej Novák:
Extended binary nonlinear codes and their application in testing and compression. 1-2 - Chia-Ming Chang, Yong-Xiao Chen, Jin-Fu Li:
A built-in self-test scheme for classifying refresh periods of DRAMs. 1-2 - Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue, Alex Orailoglu:
Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions. 1-6 - Michael A. Kochte, Matthias Sauer, Laura Rodríguez Gómez, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich:
Specification and verification of security in reconfigurable scan networks. 1-6 - Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Paolo Prinetto, Marco Restifo:
Scan chain encryption for the test, diagnosis and debug of secure circuits. 1-6
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-09-28 01:33 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
