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ORCIDIEEE Transactions on Computers, Volume 39
Volume 39, Number 1, January 1990
- Jason Gait:
A Checkpointing Page Store for Write-Once Optical Disk. 2-9
- Ming-Syan Chen
, Kang G. Shin, Dilip D. Kandlur:
Addressing, Routing, and Broadcasting in Hexagonal Mesh Multiprocessors. 10-18 - Myungwhan Choi, C. M. Krishna:
An Adaptive Algorithm to Ensure Differential Service in aToken-Ring Network. 19-33 - Pro Rong Chang, George Lee:
A Decomposition Approach for Balancing Large-Scale Acyclic Data Flow Graphs. 34-46 - Douglas M. Blough, Gerald M. Masson:
Performance Analysis of a Generalized Concurrent Error Detection Procedure. 47-62 - Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan:
Design and Analysis of a Gracefully Degrading Interleaved Memory System. 63-71 - Yoheved Dotan, Benjamin Arazi:
Concurrent Logic Programming as a Hardware Description Tool. 72-88 - Behrooz Parhami:
Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations. 89-98 - Kang G. Shin, Ming-Syan Chen:
On the Number of Acceptable Task Assignments in Distributed Computing Systems. 99-110 - Dik Lun Lee, Frederick H. Lochovsky:
HYTREM - A Hybrid Text-Retrieval Machine for Large Databases. 111-123
- Sumio Masuda, Kazuo Nakajima, Toshinobu Kashiwabara, Toshio Fujisawa:
Crossing Minimization in Linear Embeddings of Graphs. 124-127 - David M. Mandelbaum:
A Systematic Method for Division with High Average Bit Skipping. 127-130 - Y. N. Srikant:
Parallel Parsing of Arithmetic Expressions. 130-132 - Philip Heidelberger, V. Alan Norton, John T. Robinson:
Parallel Quicksort Using Fetch-and-Add. 133-138 - Mark G. Karpovsky, Prawat Nagvajara:
Optimal Robust Compression of Test Responses. 138-141 - Youngju Won, Sartaj Sahni, Yacoub M. El-Ziq:
A Hardware Accelerator for Maze Routing. 141-145 - Jorge L. Aravena:
Recursive Moving Window DFT Algorithm. 145-148 - Martin L. Brady, Majid Sarrafzadeh:
Stretching a Knock-Knee Layout for Multilayer Wiring. 148-151 - Lars-Magnus Ewerbring, Franklin T. Luk:
Computing the Singular Value Decomposition on the Connection Machine. 152-155 - James Jacob, Nripendra N. Biswas:
Further Comments on "Detection of Faults in Programmable Logic Arrays". 155-157
Volume 39, Number 2, February 1990
- Krishna Kant, A. Ravichandran:
Synthesizing Robust Data STructures - An Introduction. 161-173 - Walid A. Najjar, Jean-Luc Gaudiot:
Network Resilience: A Measure of Network Fault Tolerance. 174-181 - Tein-Hsiang Lin, Kang G. Shin:
Location of a Faulty Module in a Computing System. 182-194 - Sampath Rangarajan, Donald S. Fussell, Miroslaw Malek:
Built-In Testing of Integrated Circuit Wafers. 195-205 - David M. Nicol, Paul F. Reynolds Jr.:
Optimal Dynamic Remapping of Data Parallel Computations. 206-219 - René David, Antoine Fuentes:
Fault Diagnosis of RAM's from Random Testing Experiments. 220-229 - V. Krishnamoorthy, Krishnaiyan Thulasiraman, M. N. S. Swamy:
Incremental Distance and Diameter Sequences of a Graph: New Measures of Network Performance. 230-237 - Merrill E. Isenman, Dennis E. Shasha:
Performance and Architectural Issues for String Matching. 238-250 - Binay Sugla, David A. Carlson:
Extreme Area-Time Tradeoffs in VLSI. 251-257
- Charles C. Wang, Dingyi Pei:
A VLSI DEsign for Computing Exponentiations in GF(2^m) and Its Application to Generate Pseudorandom Number Sequences. 258-266 - Ferng-Ching Lin, Kung Chen:
On the Design of a Unidirectional Systolic Array for Key Enumeration. 266-267 - Amitava Majumdar, Cauligi S. Raghavendra, Melvin A. Breuer:
Fault Tolerance in Linear Systolic Arrays Using Time Redundancy. 269-276 - Robert Cypher, Jorge L. C. Sanz, L. Snyder:
Algorithms for Image Component Labeling on SIMD Mesh-Connected Computers. 276-281 - Yigal Brandman, Alon Orlitsky, John L. Hennessy:
A Spectral Lower Bound Techniqye for the Size of Decision Trees and Two Level AND/OR Circuits. 282-287 - René David:
Comments on "Signature Analysis for Multiple Output Circuits". 287-288
Volume 39, Number 3, March 1990
- Ahmed E. Kamal, V. Carl Hamacher:
Utilizing Bandwidth Sharing in the Slotted Ring. 289-299 - Arvind, Rishiyur S. Nikhil:
Executing a Program on the MIT Tagged-Token Dataflow Architecture. 300-318 - Hyunsoo Yoon, Kyungsook Y. Lee, Ming T. Liu:
Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems. 319-327 - Mahadev Satyanarayanan, Ellen H. Siegel:
Parallel Communication in a Large Distributed Environment. 329-348 - Gurindar S. Sohi:
Instruction Issue Logic for High-Performance Interruptible, Multiple Functional Unit, Pipelines Computers. 349-359 - Stanislaw J. Piestrak:
Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes. 360-374 - Carsten Vogt:
A Buffer-Based Method for storage Allocation in an Object-Oriented System. 375-383
- Michael J. Quinn:
Analysis and Implementation of Branch-and Bound Algorithms on a Hypercube Multicomputer. 384-387 - Jien-Chung Lo, Suchai Thanawastien:
On the Design of Combinational Totally Self-Checking I-out-of3 Code Checkers. 387-393 - Wei-Ming Lin, Viktor K. Prasanna:
A Note on the Linear Transformation Method for Systolic Array Design. 393-399 - Sanjeev Saxena, P. C. P. Bhatt, V. C. Prasad:
Efficient VLSI Parallel Algorithm for Delaunay Triangulation on Orthogonal Tree Network in Two and Three Dimensions. 400-404 - Bong-Rad Choi, Kyu Ho Park, Myunghwan Kim:
An Improved Hardware Implementation of the Fault-Tolerant Clock Synchronization Algorithm for Large Multiprocessor Systems. 404-407 - Antonis M. Paschalis, Costas Efstathiou, Constantine Halatsis:
An Efficient TSC 1-out-of-3 Code Checker. 407-411 - Sung Je Hong:
The Design of a Testable Parallel Multiplier. 411-416
Volume 39, Number 4, April 1990
- Régis Leveugle, Gabriele Saucier:
Optimized Synthesis of Concurrently Checked Controllers. 419-425 - V. S. S. Nair, Jacob A. Abraham:
Real-Number Codes for Bault-Tolerant Matrix Operations On Processor Arrays. 426-435 - Vijay Balasubramanian, Prithviraj Banerjee:
Compiler-Assisted Synthesis of Algorithm-Based Checking in Multiprocessors. 436-446 - Mahadev Satyanarayanan, James J. Kistler, Puneet Kumar, Maria E. Okasaki, Ellen H. Siegel, David C. Steere:
Coda: A Highly Available File System for a Distributed Workstation Environment. 447-459 - Kun-Lung Wu, W. Kent Fuchs:
Recoverable Distributed Shared Virtual Memory. 460-469 - Dong Sam Ha, Vijay P. Kumar:
On the Design of High-Yield Reconfigurable PLA's. 470-479 - Vwani P. Roychowdhury, Jehoshua Bruck, Thomas Kailath:
Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays. 480-489 - Shantanu Dutt, John P. Hayes:
On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures. 490-503 - Jean Arlat, Karama Kanoun, Jean-Claude Laprie:
Dependability Modeling and Evaluation of Software Fault-Tolerant Systems. 504-513 - Parameswaran Ramanathan, Dilip D. Kandlur, Kang G. Shin:
Hardware-Assisted Software Clock Synchronization for Homogeneous Distributed Systems. 514-524 - Ravishankar K. Iyer, Luke T. Young, P. V. Krishna Iyer:
Automatic Recognition of Intermittent Failures: An Experimental Study of Field Data. 525-537
- Rajesh Gupta, Rajiv Gupta, Melvin A. Breuer:
The BALLAST Methodology for Structured Partial Scan Design. 538-544 - Kwang-Ting Cheng, Vishwani D. Agrawal:
A Partial Scan Method for Sequential Circuits with Feedback. 544-549 - Yuval Tamir, Marc Tremblay:
High-Performance Fault-Tolerant VLSI Systems Using Micro Rollback. 548-554 - Nirmal R. Saxena, Edward J. McCluskey:
Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums. 554-559 - Ming-Feng Chang, Weiping Shi, W. Kent Fuchs:
Optimal Diagnosis Procedures for k-out-of-n Structures. 559-564 - Mengly Chean, José A. B. Fortes:
The Full-Use-of-Suitable-Spares (FUSS) Approach to Hardware Reconfiguration for Fault-Tolerant Processor Arrays. 564-571 - Meera Balakrishnan, Cauligi S. Raghavendra:
On Reliability Modeling of Closed Fault-Tolerant Computer Systems. 571-575 - James H. Barton, Edward W. Czeck, Zary Segall, Daniel P. Siewiorek:
Fault Injection Experiments Using FIAT. 575-582 - Sharad C. Seth, Vishwani D. Agrawal, Hassan Farhat:
A Statistical Theory of Digital Circuit Testability. 582-586 - Dhiraj K. Pradhan, Sandeep K. Gupta, Mark G. Karpovsky:
Aliasing Probability for Multiple Input Signature Analyzer. 586-591 - Larry A. Dunning, Gur Dial, Murali R. Varanasi:
Unidirectional Byte Error Detecting Codes for Computer Memory Systems. 592-595
Volume 39, Number 5, May 1990
- Meiliu Lu, Du Zhang, Tadao Murata:
Analysis of Self-Stabilizing Clock Synchronization by Means of Stochastic Petri Nets. 597-604 - Franco P. Preparata, Jean Vuillemin:
Practical Cellular Dividers. 605-614 - Dipak Ghosal, Laxmi N. Bhuyan:
Performance Evaluation of a Dataflow Architecture. 615-627 - Thomas L. Casavant, Jon G. Kuhl:
A Communicating Finite Automata Approach to Modeling Distributed Computation and Its Application to Distributed Decision-Making. 628-639 - Cheng-Wen Wu, Peter R. Cappello:
Easily Testable Iterative Logic Arrays. 640-652 - Praxetes Canutes Mathias, Lalit M. Patnaik:
Systolic Evaluation of Polynomial Expressions. 653-665 - Belle W. Y. Wei, Clark D. Thompson:
Area-Time Optimal Adder Design. 666-675 - Hon Fung Li, David K. Probst:
Optimal VLSI Dictionary Machines Without Compress Instructions. 676-693
- Wei-Kuan Shih, Sun Wu, Yue-Sun Kuo:
Unifying Maximum Cut and Minimum Cut of a Planar Graph. 694-697 - Spira Matic:
Emulation of Hypercube Architecture on Nearest-Neighbor Mesh-Connected Processing Elements. 698-700 - Daniel J. Rosenkrantz:
Half-Hot State Assignments for Finite State Machines. 700-702 - Mostafa I. H. Abd-El-Barr, Zvonko G. Vranesic:
Cost Reduction in the CCD Realization of MVMT Function. 702-706 - William Gale, Sumit Das, Clement T. Yu:
Improvements to an Algorithm for Equipartitioning. 706-710 - Steven J. Friedman, Kenneth J. Supowit:
Finding the Optimal Variable Ordering for Binary Decision Diagrams. 710-713 - Richard Beigel, John Gill:
Sorting n Objects with a K-Sorter. 714-716 - Heuey Ling:
An Approach to Implementing Multiplication with Small Tables. 717-718 - Paolo Ancilotti, Beatrice Lazzerini, Cosimo Antonio Prete, Maurizio Sacchi:
A Distributed Commit Protocol for a Multicomputer System. 718-724
Volume 39, Number 6, June 1990
- Milos D. Ercegovac, Tomás Lang:
Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD. 725-740 - Shiow-Chen Shyu, Victor O. K. Li:
Performance Analysis of Static Locking in Distributed Database Systems. 741-751 - Sandip Kundu, Sudhakar M. Reddy:
On Symmetric Error Correcting and All Unidirectional Error Detecting Codes. 752-761 - Hideo Fujiwara:
Computational Complexity of Controllability/Observability Problems for Combinational Circuits. 762-767 - Mamoru Sasaki, Takahiro Inoue, Yuji Shirai, Fumio Ueno:
Fuzzy Multiple-Input Maximum and Minimum Circuits in Current Mode and Their Analyses Using Bounded-Difference Equations. 768-774 - William J. Dally:
Performance Analysis of k-Ary n-Cube Interconnection Networks. 775-785 - Sivarama P. Dandamudi, Derek L. Eager:
Hierarchical Interconnection Networks for Multicomputer Systems. 786-797 - Arthur F. Champernowne, Louis B. Bushard, John T. Rusterholz, John R. Schomburg:
Latch-to-Latch Timing Rules. 798-808 - Robert Michael Owens, Mary Jane Irwin:
Being Stingy with Multipliers. 809-818 - John N. Daigle, Robert B. Kuehl, Joseph D. Langford:
Queuing Analysis of an Optical Disk Jukebox Based Office System. 819-828
- Abdou Youssef, Bruce W. Arden:
Equivalence Between Functionality and Topology of Log N-Stage Banyan Networks. 829-832 - Krishna R. Pattipati, Samir A. Shah:
On the Computational Aspects of Performability Models of Fault-Tolerant Computer Systems. 832-836 - Bruce L. Montgomery, B. V. K. Vijaya Kumar:
Systematic Random Error Correcting and All Undirectional Error Detecting Codes. 836-840 - Edmundo de Souza e Silva, Richard R. Muntz:
A Note on the Computational Cost of the Linearizer Algorithm for Queueing Networks. 840-842 - Jon T. Butler, Kriss A. Schueller:
On the Equivalence of Cost Functions in the Design of Circuits by Costtable. 842-844 - Xumin Nie, David A. Plaisted:
Experimental Results on Subgoal Reordering. 845-848 - Chin-Wen Ho, Richard C. T. Lee:
A Parallel Algorithm for Solving Sparse Triangular Systems. 848-852
Volume 39, Number 7, July 1990
- Flavio Bonomi:
On Job Assignment for a Parallel System of Processor Sharing Queues. 858-869 - Kang G. Shin:
Minimal Order Loop-Free Routing Strategy. 870-881 - Ferenc Belik:
An Efficient Deadlock Avoidance Rechnique. 882-888 - Hideharu Amano, Taisuke Boku, Tomohiro Kudoh:
(SM)²-II: A Large-Scale Multiprocessor for Sparse Matrix Calculations. 889-905 - Krishna Kant:
Performance Analysis of Real-Time Software Supporting Fault-Tolerant Operation. 906-918 - Zhixi Fang, Peiyi Tang, Pen-Chung Yew, Chuan-Qi Zhu:
Dynamic Processor Self-Scheduling for General Parallel Nested Loops. 919-929 - Lindsay Kleeman:
The Jitter Model for Metastability and Its Application to Redundant Synchronizers. 930-942
- Che-Liang Yang:
Constructing Optimal Procedures for Testing Series Systems. 943-945 - John P. Fishburn:
Clock Skew Optimization. 945-951 - Wang-Chan Wong, Tatsuya Suda, Lubomir Bic:
Performance Analysis of a Message-Oriented Knowledge-Base. 951-957 - Jia-Shung Wang, Richard C. T. Lee:
An Efficient Channel Routing Algorithm to Yield an Optimal Solution. 957-962 - Shing-Tsaan Huang:
Notes on Shuffle/Exchange Type Permutation Sets. 962-965 - Kyungsook Y. Lee, Hyunsoo Yoon:
The B-Network: A Multistage Interconnection Network with Backward Links. 966-969 - Nirmal R. Saxena, Edward J. McCluskey:
Analysis of Checksums, Extended-Precision Checksums, and Cyclic Redundancy Checks. 969-975 - Ibrahim H. Önyüksel, Keki B. Irani:
Markovian Queueing Network Models for Performance Analysis of a Single-Bus Multiprocessor System. 975-980
Volume 39, Number 8, August 1990
- Pak K. Chan, Martine D. F. Schlag:
Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip. 983-992 - Tony M. Carter, James E. Robertson:
The Set Theory of Arithmetic Decomposition. 993-1005 - Homayoon Sam, Arupratan Gupta:
A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations. 1006-1015 - Milos D. Ercegovac, Tomás Lang:
Radix-4 Square Root Without Initial PLA. 1016-1024