IEEE Transactions on Computers, Volume 35

Volume 35, Number 1, January 1986

• 
  Dan I. Moldovan, José A. B. Fortes:
  Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays. 1-12
• 
  Anastasios Vergis, Kenneth Steiglitz:
  Testability Conditions for Bilateral Arrays of Combinational Cells. 13-22
• 
  Iiro Hartimo, Klaus Kronlöf, Olli Simula, Jorma Skyttä:
  DFSP: A Data Flow Signal Processor. 23-33
• 
  Avinoam Bilgory, Daniel Gajski:
  A Heuristic for Suffix Solutions. 34-42
• 
  David Lee Tuomenoksa, Howard Jay Siegel:
  Determining an Optimal Secondary Storage Service Rate for the PASM Control System. 43-53
• 
  Peter G. Harrison:
  An Enhanced Approximation by Pair-Wise Analysis of Servers for Time Delay Distributions in Queueing Networks. 54-61

Correspondence

• 
  Alok Aggarwal:
  Optimal Bounds for Finding Maximum on Array of Processors with k Global Buses. 62-64
• 
  Jacob Savir:
  The Bidirectional Double Latch (BDDL). 65-66
• 
  J. Calvo, J. I. Acha, Manuel Valencia:
  Asynchronous Modular Arbiter. 67-70
• 
  Füsun Özgüner:
  Deductive Fault Simulation of Internal Faults of Inverter-Free Circuits and Programmable Logic Arrays. 70-73
• 
  Michael Journeau:
  A Note on the Restricted Range Cutting Algorithm. 73
• 
  Concettina Guerra:
  Systolic Algorithms for Local Operations on Images. 73-77
• 
  Louise Trevillyan, William H. Joyner Jr., C. Leonard Berman:
  Global Flow Analysis in Automatic Logic Design. 77-81
• 
  Janusz Rajski, Jerzy Tyszer:
  The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's. 81-85
• 
  Bhargab B. Bhattacharya, Bidyut Gupta:
  On the Impossible Class of Faulty Functions in Logic Networks Under Short Circuit Faults. 85-90
• 
  Abhijit Sengupta, Arunabha Sen, Subir Bandyopadhyay:
  On System Diagnosability in the Presence of Hybrid Faults. 90-93
• 
  Israel Koren:
  Comments on "The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors". 93-94

Volume 35, Number 2, February 1986

• 
  David A. Rich:
  A Survey of Multivalued Memories. 99-106
• 
  John P. Hayes:
  Uncertainty, Energy, and Multiple-Valued Logics. 107-114
• 
  Akira Maruoka:
  Complexity Based on Partitioning of Boolean Circuits and Their Relation to Multivalued Circuits. 115-123
• 
  Mostafa H. Abd-El-Barr, Safwat G. Zaky, Zvonko G. Vranesic:
  Synthesis of Multivalued Multithreshold Functions for CCD Implementation. 124-133
• 
  Philipp W. Besslich:
  Heuristic Minimization of MVL Functions: A Direct Cover Approach. 134-144
• 
  Terrance L. Huntsberger, Chandraleka Rangarajan, Sadali N. Jayaramamurthy:
  Representation of Uncertainty in Computer Vision Using Fuzzy Sets. 145-156

Correspondence

• 
  James L. Mangin, K. Wayne Current:
  Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder Circuits. 157-161
• 
  Takeshi Yamakawa, Tsutomu Miki:
  The Current Mode Fuzzy Logic Integrated Circuits Fabricated by the Standard CMOS Process. 161-167
• 
  Mou Hu, Kenneth C. Smith:
  Ternary Scan Design for VLSI Testability. 167-170
• 
  Abhijit Sengupta, Arunabha Sen:
  On the Diagnosability of a General Model of System with Three-Valued Test Outcomes. 170-173
• 
  Corina Reischer, Dan A. Simovici:
  Iteration Properties of Multivalued Switching Functions. 173-178
• 
  Masao Mukaidono:
  Regular Ternary Logic Functions - Ternary Logic Functions Suitable for Treating Ambiguity. 179-183
• 
  Claudio Moraga:
  Design of a Multiple-Valued Systolic System for the Computation of the Chrestenson Spectrum. 183-188

Volume 35, Number 3, March 1986

• 
  I. V. Ramakrishnan, Donald S. Fussell, Abraham Silberschatz:
  Mapping Homogeneous Graphs on Linear Arrays. 189-209
• 
  Rina Dechter, Leonard Kleinrock:
  Broadcast Communications and Distributed Algorithms. 210-219
• 
  Donald F. Towsley:
  Approximate Models of Multiple Bus Multiprocessor Systems. 220-228
• 
  Lalit M. Patnaik, R. Govindarajan, N. S. Ramadoss:
  Design and Performance Evaluation of EXMAN: An EXtended MANchester Data Flow Computer. 229-244
• 
  François Baccelli, Philippe Mussi:
  An Asynchronous Parallel Interpreter for Arithmetic Expressions and Its Evaluation. 245-256
• 
  Svetlana P. Kartashev, Steven I. Kartashev:
  Data Exchange Optimization in Reconfigurable Binary Trees. 257-273

Correspondence

• 
  Daniel Brand:
  Detecting Sneak Paths in Transistor Networks. 274-278
• 
  C. V. Ramamoorthy, Y. W. Eva Ma:
  Optimal Recopnfiguration Strategies for Reconfigurable Computer Systems with no Repair. 278-280
• 
  Sumanta Guha, Arunabha Sen:
  On Fault-Tolerant Distributor Communication Architecure. 281-283
• 
  Liam M. Casey:
  Comments on "The Design of a Reliable Remote Procedure Call Mechanism". 283-284

Volume 35, Number 4, April 1986

• 
  David J. Taylor, Carl-Johan H. Seger:
  Robust Storage Structures for Crash Recovery. 288-295
• 
  Prithviraj Banerjee, Jacob A. Abraham:
  Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems. 296-306
• 
  Cauligi S. Raghavendra, Anujan Varma:
  Fault-Tolerant Multiprocessors with Redundant-Path Interconnection Networks. 307-316
• 
  Nirmal R. Saxena, John P. Robinson:
  Accumulator Compression Testing. 317-321
• 
  Edmundo de Souza e Silva, H. Richard Gail:
  Calculating Cumulative Operational Time Distributions of Rpairable Computer Systems. 302-332
• 
  Mark Smotherman, Robert Geist, Kishor S. Trivedi:
  Provably Conservative Approximations to Complex Reliability Models. 333-338
• 
  Thijs Krol:
  (N, K) Concept Fault Tolerance. 339-349

Correspondence

• 
  Bella Bose:
  Burst Unidirectional Error-Detecting Codes. 350-353
• 
  Anton T. Dahbura:
  An Efficient Algorithm for Identifying the Most Likely Fault Set in a Probabilistically Diagnosable System. 354-356
• 
  A. S. Mahmudul Hassan, Vinod K. Agarwal:
  A Fault-Tolerant Modular Architecture for Binary Trees. 356-361
• 
  Magdy S. Abadir, Melvin A. Breuer:
  Test Schedules for VLSI Circuits Having Built-In Test Hardware. 361-367
• 
  Laung-Terng Wang, Edward J. McCluskey:
  Condensed Linear Feedback Shift Register (LFSR) Testing - A Pseudoexhaustive Test Technique. 367-370
• 
  Kang G. Shin, Yann-Hang Lee:
  Measurement and Application of Fault Latency. 370-375
• 
  Magdy S. Abadir, Hassan K. Reghbati:
  Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams. 375-379
• 
  Saied Bozorgui-Nesbat, Edward J. McCluskey:
  Lower Overhead Design for Testability of Programmable Logic Arrays. 379-383
• 
  Kewal K. Saluja, Ramaswami Dandapani:
  An Alternative to Scan Design Methods for Sequential Machines. 384-388

Volume 35, Number 5, May 1986

• 
  Jacek Blazewicz, Mieczyslaw Drabowski, Jan Weglarz:
  Scheduling Multiprocessor Tasks to Minimize Schedule Length. 389-393
• 
  Dimitris Nikolos, Nikolaos Gaitanis, George Philokyprou:
  Systematic t-Error Correcting/All Unidirectional Error Detecting Codes. 394-402
• 
  Jeffrey Scott Vitter, Roger A. Simons:
  New Classes for Parallel Complexity: A Study of Unification and Other Complete Problems for P. 403-418
• 
  Edmundo de Souza e Silva, Stephen S. Lavenberg, Richard R. Muntz:
  A Clustering Approximation Technique for Queueing Network Models with a Large Number of Chains. 419-430
• 
  H. V. Jagadish, Robert G. Mathews, Thomas Kailath, John A. Newkirk:
  A Study of Pipelining in Computing Arrays. 431-440
• 
  Ivor P. Page, Jeff Hagins:
  Improving the Performance of Buddy Systems. 441-447
• 
  C. Mani Krishna, Kang G. Shin:
  On Scheduling Tasks with a Quick Recovery from Failure. 448-455
• 
  Wayne A. Davis, De-Lei Lee:
  Fas Search Algorithms for Associative Memories. 456-461
• 
  Vijaya Ramachandran:
  Algorithmic Aspects of MOS VLSI Switch-Level Simulation with Race Detection. 462-475

Correspondence

• 
  J. Paul Roth:
  Minimization by the D Algorithm. 476-478
• 
  J. J. Thomas, J. M. Keller, G. N. Larsen:
  The Calculation of Multiplicative Inverses Over GF(P) Efficiently Where P is a Mersenne Prime. 478-482
• 
  Hongyuan Wang, Samuel C. Lee:
  Comments on "Sign/Logarithm Arithmetic for FFT Implementation''. 482-484

Volume 35, Number 6, June 1986

• 
  Jean-Luc Gaudiot:
  Structure Handling in Data-Flow Systems. 489-502
• 
  Che-Liang Yang, Gerald M. Masson:
  A Fault Identification Algorithm for t_i-Diagnosable Systems. 503-510
• 
  Ravishankar K. Iyer, David J. Rossetti:
  A Measurement-Based Model for Workload Dependence of CPU Errors. 511-519
• 
  Walid A. Abu-Sufah, Harlan E. Husmann, David J. Kuck:
  On Input/Output Speedup in Tightly Coupled Multiprocessors. 520-530
• 
  Oscar H. Ibarra, Sam M. Kim, Michael A. Palis:
  Designing Systolic Algorithms Using Sequential Machines. 531-542
• 
  Teofilo F. Gonzalez, Sing-Ling Lee:
  Routing Multiterminal Nets Around a Rectangle. 543-549
• 
  Yahiko Kambayashi, Saburo Muroga:
  Properties of Wired Logic. 550-563

Correspondence

• 
  Timothy C. K. Chou, Jacob A. Abraham:
  Distributed Control of Computer Systems. 564-567
• 
  Guo-Jie Li, Benjamin W. Wah:
  Coping with Anomalies in Parallel Branch-and-Bound Algorithms. 568-573
• 
  Manoj Kumar, J. Robert Jump:
  Performance of Unbuffered Shuffle-Exchange Networks. 573-578
• 
  Luigi Ciminiera, Angelo Serra:
  A Connecting Network with Fault Tolerance Capabilities. 578-580

Volume 35, Number 7, July 1986

• 
  Bezalel Gavish, Hasan Pirkul:
  Computer and Database Location in Distributed Computer Systems. 583-590
• 
  Shing-Tsaan Huang, Satish K. Tripathi:
  Finite State Model and Compatibility Theory: New Analysis Tools for Permutation Networks. 591-601
• 
  John P. Hayes:
  Pseudo-Boolean Logic Circuits. 602-612
• 
  Tony Cheung, James Smith:
  A Simulation Study of the CRAY X-MP Memory System. 613-622
• 
  Wil J. van Gils:
  A Triple Modular Redundancy Technique Providing Multiple-Bit Error Protection Without Using Extra Redundancy. 623-631
• 
  Charles E. McDowell, William F. Appelbe:
  Processor Scheduling for Linearly Connected Parallel Processors. 632-638

Correspondence

• 
  Che-Liang Yang, Gerald M. Masson, Richard A. Leonetti:
  On Fault Isolation and Identification in t₁/t₁-Diagnosable Systems. 639-643
• 
  Lindsay Kleeman, Antonio Cantoni:
  Can Redundancy and Masking Improve the Performance of Synchronizers? 643-646
• 
  C. L. Chen:
  Byte-Oriented Error-Correcting Codes for Semiconductor Memory Systems. 646-648
• 
  Mike Sousa, Fred J. Taylor:
  Complex Integer to Complex Residue Encoding. 648-650
• 
  Victor Konrad:
  Efficient Computation of the Maximum of the Sum of Two Sequences and Applications. 651-653
• 
  Paul H. Bardell, William H. McAnney:
  Pseudorandom Arrays for Built-In Tests. 653-658
• 
  Kewal K. Saluja, Ramaswami Dandapani:
  Testable Design of Single-Output Sequential Machines Using Checking Experiments. 658-662
• 
  Cauligi S. Raghavendra, Viktor K. Prasanna:
  Permutations on Illiac IV-Type Networks. 663-669
• 
  Jong Won Park:
  An Efficient Memory System for Image Processing. 669-674

Volume 35, Number 8, August 1986

• 
  Randal E. Bryant:
  Graph-Based Algorithms for Boolean Function Manipulation. 677-691
• 
  James E. Smith, Shlomo Weiss, Nicholas Y. Pang:
  A Simulation Study of Decoupled Architecture Computers. 692-702
• 
  Israel Koren, Zahava Koren, Stephen Y. H. Su:
  Analysis of a Class of Recovery Procedures. 703-712
• 
  Shinji Nakamura:
  Algorithms for Iterative Array Multiplication. 713-719
• 
  Makoto Kobayashi:
  An Empirical Study of Task Switching Locality in MVS. 720-731
• 
  Andrzej Hlawiczka:
  Compression of Three-State Data Serial Streams by Means of a Parallel LFSR Signature Analyzer. 732-741
• 
  Sudhakar M. Reddy, Madhukar K. Reddy:
  Testable Realizations for FET Stuck-Open Faults CMOS Combinational Logic Circuits. 742-754

Correspondence

• 
  Ajit Pal:
  An Algorithm for Optimal Logic Design Using Multiplexers. 755-757
• 
  Shahid H. Bokhari, A. D. Raza:
  Reducing the Diameters of Computer Networks. 757-761
• 
  C. McMullen, J. Shearer:
  Prime Implicants, Minimum Covers, and the Complexity of Logic Simplification. 761-762
• 
  N. B. Chakraborti, John S. Soundararajan, A. L. Narasimha Reddy:
  An Implementation of Mixed-Radix Conversion for Residue Number Applications. 762-764
• 
  Yung H. Tsin:
  Finding Lowest Common Ancestors in Parallel. 764-769
• 
  Miron Abramovici, Premachandran R. Menon, David T. Miller:
  Checkpoint Faults are not Sufficient Target Faults for Test Generation. 769-771

Volume 35, Number 9, September 1986

• 
  Vijay K. Vaishnavi:
  On the Height of Multidimensional Height-Balanced Trees. 773-780
• 
  Irving S. Reed, Trieu-Kien Truong, Jørn M. Jensen, In-Shek Hsu:
  The VLSI Design of an Error-Trellis Syndrome Decoder for Certain Convolutional Codes. 781-789
• 
  Chaitanya K. Baru, Stanley Y. W. Su:
  The Architecture of SM3: A Dynamically Partitionable Multicomputer System. 790-802
• 
  Andrea Bobbio, Kishor S. Trivedi:
  An Aggregation Technique for the Transient Analysis of Stiff Markov Chains. 803-814
• 
  Ramón D. Acosta, Jacob Kjelstrup, Hwa C. Torng:
  An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors. 815-828

Correspondence

• 
  M. M. Mirsalehi, Thomas K. Gaylord:
  Comments on "Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach". 829-830
• 
  René David:
  Signature Analysis for Multiple-Output Circuits. 830-837
• 
  Nicholas F. Maxemchuk, Anton T. Dahbura:
  Optimal Diagnosable System Design Using Full-Difference Triangles. 837-839
• 
  Robert B. Hagmann:
  Crash Recovery Scheme for a Memory-Resident Database System. 839-843
• 
  Mikhail J. Atallah, Susanne E. Hambrusch:
  Optimal Rotation Problems in Channel Routing. 843-847
• 
  Tang Jian:
  An O(2^0.304n) Algorithm for Solving Maximum Independent Set Problem. 847-851

Volume 35, Number 10, October 1986

• 
  Dominique Snyers, André Thayse:
  Algorithmic State Machine Design and Automatic Theorem Proving: Dual Approaches to the Same Activity. 853-861
• 
  Kozo Kinoshita, Kewal K. Saluja:
  Built-In Testing of Memory Using an On-Chip Compact Testing Scheme. 862-870
• 
  Raif M. Yanney, John P. Hayes:
  Distributed Recovery in Fault-Tolerant Multiprocessor Networks. 871-879
• 
  Stephen H. Unger, Chung-Jen Tan:
  Clocking Schemes for High-Speed Digital Systems. 880-895
• 
  Tom Rhyne, Noel R. Strader II:
  A Signed Bit-Sequential Multiplier. 896-901

Correspondence

• 
  Balakrishna R. Iyer, Lorenzo Donatiello, Philip Heidelberger:
  Analysis of Performability for Stochastic Models of Fault-Tolerant Systems. 902-907
• 
  James R. Goodman, Honesty C. Young:
  Comments on "A Massive Memory Machine". 907-910
• 
  Woei Lin, Chuan-lin Wu:
  Reconfiguration Procedures for a Polymorphic and Partitionable Multiprocessor. 910-916
• 
  Gregory E. Bridges, Werner Pries, Robert D. McLeod, M. Yunik, P. Glenn Gulak, Howard C. Card:
  Dual Systolic Architectures for VLSI Digital Signal Processing Systems. 916-923
• 
  Elena Lodi, Linda Pagli:
  A VLSI Solution to the Vertical Segment Visibility Problem. 923-928
• 
  Raouf N. Gorgui-Naguib, Robert A. King:
  Comments on "Matrix Processors Using p-Adic Arithmetic for Exact Linear Computations". 928-931

Volume 35, Number 11, November 1986

• 
  Melvin A. Breuer, Asad A. Ismaeel:
  Roving Emulation as a Fault Detection Mechanism. 933-939
• 
  Krishna M. Kavi, Bill P. Buckles, U. Narayan Bhat:
  A Formal Definition of Data Flow Graph Models. 940-948
• 
  Vincenza Carchiolo, Alberto Faro, Orazio Mirabella, Giuseppe Pappalardo, Giuseppe Scollo:
  A LOTOS Specification of the PROWAY Highway Service. 949-968
• 
  Tony F. Chan, Yousef Saad:
  Multigrid Algorithms on the Hypercube Multiprocessor. 969-977
• 
  Michelle Y. Kim:
  Synchronized Disk Interleaving. 978-988

Correspondence

• 
  Peter J. Varman, I. V. Ramakrishnan:
  Synthesis of an Optimal Family of Matrix Multiplication Algorithms on Linear Arrays. 989-996
•