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ORCIDSachin S. Sapatnekar
Person information
- affiliation: University of Minnesota, USA
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Books and Theses
- 2007
[b3]Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar:
Routing Congestion in VLSI Circuits - Estimation and Optimization. Series on Integrated Circuits and Systems, Springer 2007, ISBN 978-0-387-30037-5, pp. I-XIV, 1-248- 2004
- [b2]Sachin S. Sapatnekar:
Timing. Kluwer 2004, ISBN 978-1-4020-7671-8, pp. I-IX, 1-294 - 1992
- [b1]Sachin S. Sapatnekar:
A Convex Programming Approach to Problems in VLSI Design. University of Illinois Urbana-Champaign, USA, 1992
Journal Articles
- 2024
- [j136]Vidya A. Chhabria
, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar:
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route. ACM Trans. Design Autom. Electr. Syst. 29(1): 18:1-18:25 (2024) - 2023
- [j135]Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar:
Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2782-2795 (2023) - [j134]Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar:
GNN-Based Hierarchical Annotation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2801-2814 (2023) - [j133]Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Ziqing Zeng, Sachin S. Sapatnekar:
A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4844-4857 (2023) - [j132]Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar:
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks. ACM Trans. Design Autom. Electr. Syst. 28(1): 3:1-3:27 (2023) - [j131]Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
Performance-driven Wire Sizing for Analog Integrated Circuits. ACM Trans. Design Autom. Electr. Syst. 28(2): 19:1-19:23 (2023) - [j130]Ramprasath Srinivasa Gopalakrishnan, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar:
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. ACM Trans. Design Autom. Electr. Syst. 28(5): 69:1-69:25 (2023) - 2022
- [j129]Vidya A. Chhabria, Sachin S. Sapatnekar:
OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3515-3528 (2022) - [j128]Salonik Resch, S. Karen Khatamifard, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, M. Hüsrev Cilasun, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions. ACM Trans. Embed. Comput. Syst. 21(5): 57:1-57:36 (2022) - [j127]Zamshed I. Chowdhury, S. Karen Khatamifard, Salonik Resch, M. Hüsrev Cilasun, Zhengyang Zhao, Masoud Zabihi, Meisam Razaviyayn, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
CRAM-Seq: Accelerating RNA-Seq Abundance Quantification Using Computational RAM. IEEE Trans. Emerg. Top. Comput. 10(4): 2055-2071 (2022) - 2021
- [j126]Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar:
ALIGN: A System for Automating Analog Layout. IEEE Des. Test 38(2): 8-18 (2021) - [j125]Luke R. Everson, Sachin S. Sapatnekar, Chris H. Kim:
A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control. IEEE J. Solid State Circuits 56(7): 2281-2290 (2021) - [j124]M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Keshab K. Parhi, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
Spiking Neural Networks in Spintronic Computational RAM. ACM Trans. Archit. Code Optim. 18(4): 59:1-59:21 (2021) - [j123]Farhana Sharmin Snigdha, Susmita Dey Manasi, Jiang Hu, Sachin S. Sapatnekar:
SeFAct2: Selective Feature Activation for Energy-Efficient CNNs Using Optimized Thresholds. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(7): 1423-1436 (2021) - 2020
- [j122]Salonik Resch, S. Karen Khatamifard, Zamshed Iqbal Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
PIMBALL: Binary Neural Networks in Spintronic Memory. ACM Trans. Archit. Code Optim. 16(4): 41:1-41:26 (2020) - [j121]Qianqian Fan, David J. Lilja, Sachin S. Sapatnekar:
Adaptive-Length Coding of Image Data for Low-Cost Approximate Storage. IEEE Trans. Computers 69(2): 239-252 (2020) - [j120]Susmita Dey Manasi, Farhana Sharmin Snigdha, Sachin S. Sapatnekar:
NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile Clients. IEEE Trans. Very Large Scale Integr. Syst. 28(8): 1844-1857 (2020) - 2019
- [j119]Masoud Zabihi, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar:
In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping. IEEE Trans. Computers 68(8): 1159-1173 (2019) - [j118]Deepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S. Sapatnekar:
An Analytical Approach for Error PMF Characterization in Approximate Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(1): 70-83 (2019) - [j117]Farhana Sharmin Snigdha, Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar:
Dynamic Approximation of JPEG Hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 295-308 (2019) - [j116]Tengtao Li, Sachin S. Sapatnekar:
Stress-Induced Performance Shifts in 3D DRAMs. ACM Trans. Design Autom. Electr. Syst. 24(5): 51:1-51:21 (2019) - 2018
- [j115]Zamshed I. Chowdhury, Jonathan D. Harms, S. Karen Khatamifard, Masoud Zabihi, Yang Lv, Andrew Lyle, Sachin S. Sapatnekar, Ulya R. Karpuzcu, Jianping Wang:
Efficient In-Memory Processing Using Spintronics. IEEE Comput. Archit. Lett. 17(1): 42-46 (2018) - [j114]Wenbin Xu, Sachin S. Sapatnekar, Jiang Hu:
A Simple Yet Efficient Accuracy-Configurable Adder Design. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1112-1125 (2018) - [j113]Sravan K. Marella, Sachin S. Sapatnekar:
Circuit Performance Shifts Due to Layout-Dependent Stress in Planar and 3D-ICs. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2907-2920 (2018) - 2017
- [j112]Vivek Mishra, Sachin S. Sapatnekar:
Probabilistic Wire Resistance Degradation Due to Electromigration in Power Grids. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(4): 628-640 (2017) - [j111]Deepashree Sengupta, Sachin S. Sapatnekar:
Estimating Circuit Aging Due to BTI and HCI Using Ring-Oscillator-Based Sensors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(10): 1688-1701 (2017) - [j110]Palkesh Jain, Vivek Mishra, Sachin S. Sapatnekar:
Fast Stochastic Analysis of Electromigration in Power Distribution Networks. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2512-2524 (2017) - 2016
- [j109]Meghna G. Mankalale, Sachin S. Sapatnekar:
Optimized Standard Cells for All-Spin Logic. ACM J. Emerg. Technol. Comput. Syst. 13(2): 21:1-21:22 (2016) - [j108]Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar:
Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(2): 220-231 (2016) - [j107]Palkesh Jain, Jordi Cortadella, Sachin S. Sapatnekar:
A Fast and Retargetable Framework for Logic-IP-Internal Electromigration Assessment Comprehending Advanced Waveform Effects. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2345-2358 (2016) - 2015
- [j106]Jongyeon Kim, Ayan Paul, Paul A. Crowell, Steven J. Koester, Sachin S. Sapatnekar, Jianping Wang, Chris H. Kim:
Spin-Based Computing: Device Concepts, Current Status, and a Case Study on a High-Performance Microprocessor. Proc. IEEE 103(1): 106-130 (2015) - [j105]Jordi Cortadella, Marc Galceran Oms, Michael Kishinevsky, Sachin S. Sapatnekar:
RTL Synthesis: From Logic Synthesis to Automatic Pipelining. Proc. IEEE 103(11): 2061-2075 (2015) - [j104]Sravan K. Marella, Sachin S. Sapatnekar:
A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1308-1321 (2015) - 2014
- [j103]Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar:
Techniques for scalable and effective routability evaluation. ACM Trans. Design Autom. Electr. Syst. 19(2): 17:1-17:37 (2014) - [j102]Baktash Boghrati, Sachin S. Sapatnekar:
Incremental Analysis of Power Grids Using Backward Random Walks. ACM Trans. Design Autom. Electr. Syst. 19(3): 31:1-31:29 (2014) - [j101]Saket Gupta, Sachin S. Sapatnekar:
Variation-Aware Variable Latency Design. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1106-1117 (2014) - [j100]Pingqiang Zhou, Ayan Paul, Chris H. Kim, Sachin S. Sapatnekar:
Distributed On-Chip Switched-Capacitor DC-DC Converters Supporting DVFS in Multicore Systems. IEEE Trans. Very Large Scale Integr. Syst. 22(9): 1954-1967 (2014) - [j99]Jianxin Fang, Sachin S. Sapatnekar:
Incorporating Hot-Carrier Injection Effects Into Timing Analysis for Large Circuits. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2738-2751 (2014) - 2013
- [j98]Sachin S. Sapatnekar:
Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 1 (2013) - [j97]Sachin S. Sapatnekar:
Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(12): 1837-1838 (2013) - [j96]Saket Gupta, Sachin S. Sapatnekar:
Employing circadian rhythms to enhance power and reliability. ACM Trans. Design Autom. Electr. Syst. 18(3): 38:1-38:23 (2013) - 2012
- [j95]John Keane, Chris H. Kim, Qunzeng Liu, Sachin S. Sapatnekar:
Process and Reliability Sensors for Nanoscale CMOS. IEEE Des. Test Comput. 29(5): 8-17 (2012) - [j94]Sachin S. Sapatnekar:
Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(1): 1 (2012) - [j93]Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar:
Optimized 3D Network-on-Chip Design Using Simulated Allocation. ACM Trans. Design Autom. Electr. Syst. 17(2): 12:1-12:19 (2012) - [j92]Haifeng Qian, Sachin S. Sapatnekar, Eren Kursun:
Fast poisson solvers for thermal analysis. ACM Trans. Design Autom. Electr. Syst. 17(3): 32:1-32:23 (2012) - [j91]Jianxin Fang, Sachin S. Sapatnekar:
Scalable Methods for Analyzing the Circuit Failure Probability Due to Gate Oxide Breakdown. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 1960-1973 (2012) - [j90]Saket Gupta, Sachin S. Sapatnekar:
Compact Current Source Models for Timing Analysis Under Temperature and Body Bias Variations. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 2104-2117 (2012) - 2011
- [j89]Sachin S. Sapatnekar:
Overcoming Variations in Nanometer-Scale Technologies. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(1): 5-18 (2011) - [j88]Sachin S. Sapatnekar:
Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(1): 1 (2011) - [j87]Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 603-614 (2011) - 2010
- [j86]Sachin S. Sapatnekar:
Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(1): 1 (2010) - [j85]Qunzeng Liu, Sachin S. Sapatnekar:
Capturing Post-Silicon Variations Using a Representative Critical Path. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 211-222 (2010) - 2009
- [j84]Sachin S. Sapatnekar:
Technical perspective - Where the chips may fall. Commun. ACM 52(8): 94 (2009) - [j83]Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar:
Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity. IEEE Des. Test Comput. 26(5): 15-25 (2009) - [j82]Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan:
Fast and Accurate Statistical Criticality Computation Under Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 350-363 (2009) - [j81]Qunzeng Liu, Sachin S. Sapatnekar:
A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8): 1201-1212 (2009) - [j80]Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang:
A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(9): 1295-1306 (2009) - 2008
- [j79]Sachin S. Sapatnekar:
Building your yield of dreams. IEEE Des. Test Comput. 25(2): 194-195 (2008) - [j78]Sachin S. Sapatnekar:
Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)]. IEEE Des. Test Comput. 25(5): 496-497 (2008) - [j77]Yong Zhan, Sanjay V. Kumar, Sachin S. Sapatnekar:
Thermally Aware Design. Found. Trends Electron. Des. Autom. 2(3): 255-370 (2008) - [j76]Tianpei Zhang, Sachin S. Sapatnekar:
Buffering global interconnects in structured ASIC design. Integr. 41(2): 171-182 (2008) - [j75]Sachin S. Sapatnekar:
Variability and Statistical Design. IPSJ Trans. Syst. LSI Des. Methodol. 1: 18-32 (2008) - [j74]Yong Zhan, Sachin S. Sapatnekar:
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery. ACM J. Emerg. Technol. Comput. Syst. 4(4): 18:1-18:20 (2008) - [j73]Haifeng Qian, Sachin S. Sapatnekar:
Stochastic Preconditioning for Diagonally Dominant Matrices. SIAM J. Sci. Comput. 30(3): 1178-1204 (2008) - [j72]Shrirang K. Karandikar, Sachin S. Sapatnekar:
Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 45-58 (2008) - [j71]Jaskirat Singh, Sachin S. Sapatnekar:
A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 160-173 (2008) - [j70]Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar:
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2): 295-308 (2008) - [j69]Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim:
Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property. IEEE Trans. Very Large Scale Integr. Syst. 16(2): 206-209 (2008) - [j68]Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
Body Bias Voltage Computations for Process and Temperature Compensation. IEEE Trans. Very Large Scale Integr. Syst. 16(3): 249-262 (2008) - [j67]John Keane, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim:
Stack Sizing for Optimal Current Drivability in Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. 16(5): 598-602 (2008) - 2007
- [j66]Sachin S. Sapatnekar:
Book Review: An Assay of Biochips. IEEE Des. Test Comput. 24(4): 402-403 (2007) - [j65]Sachin S. Sapatnekar, Leon Stok:
DAC Highlights. IEEE Des. Test Comput. 24(5): 502-504 (2007) - [j64]Krishnendu Chakrabarty, Sachin S. Sapatnekar:
Editorial to special issue DAC 2006. ACM J. Emerg. Technol. Comput. Syst. 3(3): 11 (2007) - [j63]Gustavo de Veciana, Marcello Lajolo, Chen He, Enrico Macii, Sachin S. Sapatnekar:
In Memoriam: Margarida F. Jacome. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1549-1550 (2007) - [j62]Yong Zhan, Sachin S. Sapatnekar:
High-Efficiency Green Function-Based Thermal Simulation Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1661-1675 (2007) - [j61]Hongliang Chang, Sachin S. Sapatnekar:
Prediction of leakage power under process uncertainties. ACM Trans. Design Autom. Electr. Syst. 12(2): 12 (2007) - [j60]Tianpei Zhang, Sachin S. Sapatnekar:
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 624-636 (2007) - 2006
- [j59]Sachin S. Sapatnekar, Grant Martin:
DAC Highlights. IEEE Des. Test Comput. 23(3): 182-184 (2006) - [j58]Sachin S. Sapatnekar:
Book Reviews: Plumbing the Depths of Leakage. IEEE Des. Test Comput. 23(4): 318-319 (2006) - [j57]Jeng-Liang Tsai, Charlie Chung-Ping Chen, Guoqiang Chen, Brent Goplen, Haifeng Qian, Yong Zhan, Sung-Mo Kang, Martin D. F. Wong, Sachin S. Sapatnekar:
Temperature-Aware Placement for SOCs. Proc. IEEE 94(8): 1502-1518 (2006) - [j56]Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar:
Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 625-636 (2006) - [j55]Jaskirat Singh, Sachin S. Sapatnekar:
Partition-Based Algorithm for Power Grid Design Using Locality. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 664-677 (2006) - [j54]Brent Goplen, Sachin S. Sapatnekar:
Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 692-709 (2006) - [j53]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze:
Accurate estimation of global buffer delay within a floorplan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1140-1145 (2006) - 2005
- [j52]Sachin S. Sapatnekar:
An EDA compendium. IEEE Des. Test Comput. 22(1): 74-75 (2005) - [j51]Sachin S. Sapatnekar:
Empowering the designer. IEEE Des. Test Comput. 22(3): 280-281 (2005) - [j50]Sachin S. Sapatnekar, Kevin J. Nowka:
Guest Editors' Introduction: New Dimensions in 3D Integration. IEEE Des. Test Comput. 22(6): 496-497 (2005) - [j49]Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar:
Placement and Routing in 3D Integrated Circuits. IEEE Des. Test Comput. 22(6): 520-531 (2005) - [j48]Sachin S. Sapatnekar:
Designing "Vary" Good Circuitry. IEEE Des. Test Comput. 22(6): 596-597 (2005) - [j47]Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar:
Early-stage power grid analysis for uncertain working modes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 676-682 (2005) - [j46]Jaskirat Singh, Sachin S. Sapatnekar:
Congestion-aware topology optimization of structured power/ground networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 683-695 (2005) - [j45]Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang:
A predictive distributed congestion metric with application to technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 696-710 (2005) - [j44]Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar:
Power grid analysis using random walks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(8): 1204-1224 (2005) - [j43]Hongliang Chang, Sachin S. Sapatnekar:
Statistical timing analysis under spatial correlations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9): 1467-1482 (2005) - [j42]Rupesh S. Shelar, Sachin S. Sapatnekar:
BDD decomposition for delay oriented pass transistor logic synthesis. IEEE Trans. Very Large Scale Integr. Syst. 13(8): 957-970 (2005) - [j41]Shrirang K. Karandikar, Sachin S. Sapatnekar:
Fast comparisons of circuit implementations. IEEE Trans. Very Large Scale Integr. Syst. 13(12): 1329-1339 (2005) - [j40]Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar:
Gate oxide leakage and delay tradeoffs for dual-Tox circuits. IEEE Trans. Very Large Scale Integr. Syst. 13(12): 1362-1375 (2005) - 2004
- [j39]Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif:
A methodology for the simultaneous design of supply and signal networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1614-1624 (2004) - [j38]Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi:
A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints. ACM Trans. Design Autom. Electr. Syst. 9(3): 273-289 (2004) - 2003
- [j37]Sachin S. Sapatnekar, Haihua Su:
Analysis and Optimization of Power Grids. IEEE Des. Test Comput. 20(3): 7-15 (2003) - [j36]Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar:
Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 49-66 (2003) - [j35]Charles J. Alpert, Sachin S. Sapatnekar:
Guest editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 385-386 (2003) - [j34]Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif:
Optimal decoupling capacitor sizing and placement for standard-cell layout designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 428-436 (2003) - [j33]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia:
A practical methodology for early buffer and wire resource allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 573-583 (2003) - [j32]Haihua Su, Kaushik Gala, Sachin S. Sapatnekar:
Analysis and optimization of structured power/ground networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1533-1544 (2003) - [j31]Shrirang K. Karandikar, Sachin S. Sapatnekar:
Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect. IEEE Trans. Very Large Scale Integr. Syst. 11(6): 1094-1105 (2003) - 2002
- [j30]Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert:
Probability-driven routing in a datapath environment. Integr. 31(2): 159-182 (2002) - [j29]Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw:
Hierarchical analysis of power distribution networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 159-168 (2002) - [j28]Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi:
Fast and exact transistor sizing based on iterative relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(5): 568-581 (2002) - [j27]Jiang Hu, Sachin S. Sapatnekar:
A timing-constrained simultaneous global routing algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(9): 1025-1036 (2002) - [j26]Min Zhao, Sachin S. Sapatnekar:
Technology mapping algorithms for domino logic. ACM Trans. Design Autom. Electr. Syst. 7(2): 306-335 (2002) - [j25]Jatuchai Pangjun, Sachin S. Sapatnekar:
Low-power clock distribution using multiple voltages and reduced swings. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 309-318 (2002) - [j24]Haitian Hu, Sachin S. Sapatnekar:
Efficient inductance extraction using circuit-aware techniques. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 746-761 (2002) - [j23]Jiang Hu, Sachin S. Sapatnekar:
Performance Driven Global Routing Through Gradual Refinement. VLSI Design 15(3): 595-604 (2002) - 2001
- [j22]Jiang Hu, Sachin S. Sapatnekar:
A survey on multi-net global routing for integrated circuits. Integr. 31(1): 1-49 (2001) - [j21]Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar:
Steiner tree optimization for buffers, blockages, and bays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(4): 556-562 (2001) - [j20]Martin Kuhlmann, Sachin S. Sapatnekar:
Exact and efficient crosstalk estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(7): 858-866 (2001) - [j19]Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji:
Technology mapping for high-performance static CMOS and pass transistor logic designs. IEEE Trans. Very Large Scale Integr. Syst. 9(5): 577-589 (2001) - 2000
- [j18]Jiang Hu, Sachin S. Sapatnekar:
Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(4): 446-458 (2000) - [j17]Sachin S. Sapatnekar:
A timing model incorporating the effect of crosstalk on delay andits application to optimal channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(5): 550-559 (2000) - [j16]Kishore Kasamsetty, Mahesh Ketkar, Sachin S. Sapatnekar:
A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(7): 779-788 (2000) - [j15]Min Zhao, Sachin S. Sapatnekar:
Timing-driven partitioning and timing optimization of mixedstatic-domino implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11): 1322-1336 (2000) - [j14]Sachin S. Sapatnekar, Weitong Chuang:
Power-delay optimizations in gate sizing. ACM Trans. Design Autom. Electr. Syst. 5(1): 98-114 (2000) - 1999
- [j13]Naresh Maheshwari, Sachin S. Sapatnekar:
Retiming control logic. Integr. 28(1): 33-53 (1999) - [j12]Huibo Hou, Jiang Hu, Sachin S. Sapatnekar:
Non-Hanan routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4): 436-444 (1999) - [j11]Naresh Maheshwari, Sachin S. Sapatnekar:
Optimizing large multiphase level-clocked circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1249-1264 (1999) - 1998
- [j10]Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn:
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2): 173-182 (1998) - [j9]Naresh Maheshwari, Sachin S. Sapatnekar:
Efficient retiming of large circuits. IEEE Trans. Very Large Scale Integr. Syst. 6(1): 74-83 (1998) - [j8]Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim:
Interleaving buffer insertion and transistor sizing into a single optimization. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 625-633 (1998) - 1997
- [j7]Shankar Ramaswamy, Sachin S. Sapatnekar, Prithviraj Banerjee:
A Framework for Exploiting Task and Data Parallelism on Distributed Memory Multicomputers. IEEE Trans. Parallel Distributed Syst. 8(11): 1098-1116 (1997) - 1996
- [j6]Sachin S. Sapatnekar:
Wire sizing as a convex optimization problem: exploring the area-delay tradeoff. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8): 1001-1011 (1996) - [j5]Piyush K. Sancheti, Sachin S. Sapatnekar:
Optimal design of macrocells for low power and high speed. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9): 1160-1166 (1996) - [j4]Sachin S. Sapatnekar, Rahul B. Deokar:
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10): 1237-1248 (1996) - 1995
- [j3]Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj:
Timing and area optimization for standard-cell VLSI circuit design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3): 308-320 (1995) - 1994
- [j2]Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang:
Convexity-based algorithms for design centering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(12): 1536-1549 (1994) - 1993
- [j1]Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang:
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(11): 1621-1634 (1993)
Conference and Workshop Papers
- 2024
- [c260]Kishor Kunal, Jitesh Poojary, S. Ramprasath, Ramesh Harjani, Sachin S. Sapatnekar:
Automated synthesis of mixed-signal ML inference hardware under accuracy constraints. ASPDAC 2024: 478-483 - [c259]Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar:
Reinforcing the Connection between Analog Design and EDA (Invited Paper). ASPDAC 2024: 665-670 - [c258]Zamshed I. Chowdhury, Hüsrev Cilasun, Salonik Resch, Masoud Zabihi, Yang Lv, Brandon Zink, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
On Gate Flip Errors in Computing-In-Memory. DATE 2024: 1-6 - [c257]Chetan Choppali Sudarshan, Nikhil Matkar, Sarma B. K. Vrudhula, Sachin S. Sapatnekar, Vidya A. Chhabria:
ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI. HPCA 2024: 671-685 - [c256]Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Yang Lv, Brandon Zink, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
On Error Correction for Nonvolatile Processing-In-Memory. ISCA 2024: 678-692 - [c255]Shiyu Guo, Sachin S. Sapatnekar, Jie Gu:
2.5 A 28nm Physical-Based Ray-Tracing Rendering Processor for Photorealistic Augmented Reality with Inverse Rendering and Background Clustering for Mobile Devices. ISSCC 2024: 44-46 - [c254]Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Rongjian Liang, Haoxing Ren, Sachin S. Sapatnekar, Bing-Yue Wu:
OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education. VTS 2024: 1-4 - 2023
- [c253]Susmita Dey Manasi, Suvadeep Banerjee, Abhijit Davare, Anton A. Sorokin, Steven M. Burns, Desmond A. Kirkpatrick, Sachin S. Sapatnekar:
Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN Accelerators. ASP-DAC 2023: 475-482 - [c252]Sumanth Kamineni, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar, Benton H. Calhoun:
AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells. DATE 2023: 1-6 - [c251]Nibedita Karmokar, Ramesh Harjani, Sachin S. Sapatnekar:
Minimum Unit Capacitance Calculation for Binary-Weighted Capacitor Arrays. DATE 2023: 1-2 - [c250]Ziqing Zeng, Sachin S. Sapatnekar:
Energy-efficient Hardware Acceleration of Shallow Machine Learning Applications. DATE 2023: 1-6 - [c249]Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Ramprasath S, Kishor Kunal, Sachin S. Sapatnekar, Ramesh Harjani:
Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology. ESSDERC 2023: 69-72 - [c248]Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestoras E. Evmorfopoulos, Sachin S. Sapatnekar:
Frequency-Domain Transient Electromigration Analysis Using Circuit Theory. ICCAD 2023: 1-8 - [c247]Salonik Resch, Hüsrev Cilasun, Masoud Zabihi, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
PimCity: A Compute in Memory Substrate featuring both Row and Column Parallel Computing. ICRC 2023: 1-10 - [c246]Salonik Resch, M. Hüsrev Cilasun, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
On Endurance of Processing in (Nonvolatile) Memory. ISCA 2023: 79:1-79:13 - [c245]Sudipta Mondal, Ramprasath S, Ziqing Zeng, Kishor Kunal, Sachin S. Sapatnekar:
A Multicore GNN Training Accelerator. ISLPED 2023: 1-6 - [c244]Sachin S. Sapatnekar:
The ALIGN Automated Analog Layout Engine: Progress, Learnings, and Open Issues. ISPD 2023: 101-102 - [c243]Nestor E. Evmorfopoulos, Mohammad Abdullah Al Shohel, Olympia Axelou, Pavlos Stoikos, Vidya A. Chhabria, Sachin S. Sapatnekar:
Recent Progress in the Analysis of Electromigration and Stress Migration in Large Multisegment Interconnects. ISPD 2023: 115-123 - [c242]Vidya A. Chhabria, Sachin S. Sapatnekar:
Analysis of Pattern-dependent Rapid Thermal Annealing Effects on SRAM Design. ISQED 2023: 1-7 - [c241]Yishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. MLCAD 2023: 1-6 - 2022
- [c240]Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar:
Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead. ASP-DAC 2022: 114-121 - [c239]Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Sachin S. Sapatnekar:
GNNIE: GNN inference engine with load-balancing and graph-specific caching. DAC 2022: 565-570 - [c238]Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar:
A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. DATE 2022: 148-153 - [c237]Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
Are Analytical Techniques Worthwhile for Analog IC Placement? DATE 2022: 154-159 - [c236]Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar:
Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. DATE 2022: 166-171 - [c235]Olympia Axelou, Nestor E. Evmorfopoulos, George Floros, George I. Stamoulis, Sachin S. Sapatnekar:
A Novel Semi-Analytical Approach for Fast Electromigration Stress Analysis in Multi-Segment Interconnects. ICCAD 2022: 27:1-27:7 - [c234]Sachin S. Sapatnekar:
EDAML 2022 Invited Speaker 7: Analog and Digital Circuit and Layout Optimization using Machine Learning. IPDPS Workshops 2022: 1188 - [c233]Ramprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar:
Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. ISPD 2022: 159-166 - [c232]Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar:
From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction. MLCAD 2022: 7-14 - [c231]Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng:
Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms. MLCAD 2022: 119-126 - 2021
- [c230]Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar:
Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. ASP-DAC 2021: 158-163 - [c229]Susmita Dey Manasi, Sachin S. Sapatnekar:
DeepOpt: Optimized Scheduling of CNN Workloads for ASIC-based Systolic Deep Learning Accelerators. ASP-DAC 2021: 235-241 - [c228]Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar:
Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks. ASP-DAC 2021: 690-696 - [c227]Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar:
A New, Computationally Efficient "Blech Criterion" for Immortality in General Interconnects. DAC 2021: 913-918 - [c226]Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar:
Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. DATE 2021: 1224-1229 - [c225]Meghna Madhusudan, Arvind K. Sharma, Yaguang Li, Jiang Hu, Sachin S. Sapatnekar, Ramesh Hajiani:
Analog Layout Generation using Optimized Primitives. DATE 2021: 1234-1239 - [c224]Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar:
MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification. DATE 2021: 1825-1828 - [c223]Zamshed I. Chowdhury, Salonik Resch, M. Hüsrev Cilasun, Zhengyang Zhao, Masoud Zabihi, Sachin S. Sapatnekar, Jianping Wang, Ulya R. Karpuzcu:
CAMeleon: Reconfigurable B(T)CAM in Computational RAM. ACM Great Lakes Symposium on VLSI 2021: 57-63 - [c222]Vidya A. Chhabria, Kishor Kunal, Masoud Zabihi, Sachin S. Sapatnekar:
BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology. ICCAD 2021: 1-8 - [c221]Hadi Esmaeilzadeh, Soroush Ghodrati, Jie Gu, Shiyu Guo, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Rohan Mahapatra, Susmita Dey Manasi, Edwin Mascarenhas, Sachin S. Sapatnekar, Ravi Varadarajan, Zhiang Wang, Hanyang Xu, Brahmendra Reddy Yatham, Ziqing Zeng:
VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis. ICCAD 2021: 1-7 - [c220]Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen:
From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD 2021: 1-9 - [c219]Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar:
Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. ICCAD 2021: 1-9 - [c218]Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestor E. Evmorfopoulos, Sachin S. Sapatnekar:
Analytical Modeling of Transient Electromigration Stress based on Boundary Reflections. ICCAD 2021: 1-8 - [c217]Tonmoy Dhar, Jitesh Poojary, Ramesh Harjani, Sachin S. Sapatnekar:
Aging of Current DACs and its Impact in Equalizer Circuits. IRPS 2021: 1-6 - [c216]Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar:
Machine Learning Techniques in Analog Layout Automation. ISPD 2021: 71-72 - [c215]Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing. MLCAD 2021: 1-6 - [c214]M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
Seeds of SEED: H-CRAM: In-memory Homomorphic Search Accelerator using Spintronic Computational RAM. SEED 2021: 70-75 - 2020
- [c213]Vidya A. Chhabria, Andrew B. Kahng, Minsoo Kim, Uday Mallappa, Sachin S. Sapatnekar, Bangqi Xu:
Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques. ASP-DAC 2020: 44-49 - [c212]M. Hüsrev Cilasun, Salonik Resch, Zamshed Iqbal Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
CRAFFT: High Resolution FFT Accelerator In Spintronic Computational RAM. DAC 2020: 1-6 - [c211]Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar:
GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. DATE 2020: 55-60 - [c210]Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar:
The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). ICCAD 2020: 54:1-54:2 - [c209]Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar:
A general approach for identifying hierarchical symmetry constraints for analog circuit layout. ICCAD 2020: 120:1-120:8 - [c208]Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
A Customized Graph Neural Network Model for Guiding Analog IC Placement. ICCAD 2020: 135:1-135:9 - [c207]Kishor Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Sachin S. Sapatnekar:
Learning from Experience: Applying ML to Analog Circuit Design. ISPD 2020: 55 - [c206]Tengtao Li, Sachin S. Sapatnekar:
Stress-Induced Performance Shifts in Flexible System-in-Foils Using Ultra-Thin Chips. ISQED 2020: 237-242 - [c205]Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
Exploring a Machine Learning Approach to Performance Driven Analog IC Placement. ISVLSI 2020: 24-29 - [c204]Salonik Resch, S. Karen Khatamifard, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, M. Hüsrev Cilasun, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
MOUSE: Inference In Non-volatile Memory for Energy Harvesting Applications. MICRO 2020: 400-414 - 2019
- [c203]Farhana Sharmin Snigdha, Ibrahim Ahmed, Susmita Dey Manasi, Meghna G. Mankalale, Jiang Hu, Sachin S. Sapatnekar:
SeFAct: selective feature activation and early classification for CNNs. ASP-DAC 2019: 487-492 - [c202]Tutu Ajayi, Vidya A. Chhabria, Mateus Fogaça, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Minsoo Kim, Jeongsup Lee, Uday Mallappa, Marina Neseem, Geraldo Pradipta, Sherief Reda, Mehdi Saligane, Sachin S. Sapatnekar, Carl Sechen, Mohamed Shalan, William Swartz, Lutong Wang, Zhehong Wang, Mingyu Woo, Bangqi Xu:
Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project. DAC 2019: 76 - [c201]Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar:
ALIGN: Open-Source Analog Layout Automation from the Ground Up. DAC 2019: 77 - [c200]Robert Perricone, Zhaoxin Liang, Meghna G. Mankalale, Michael T. Niemier, Sachin S. Sapatnekar, Jianping Wang, Xiaobo Sharon Hu:
An Energy Efficient Non-Volatile Flip-Flop based on CoMET Technology. DATE 2019: 390-395 - [c199]Masoud Zabihi, Zhengyang Zhao, Zamshed I. Chowdhury, Salonik Resch, Mahendra DC, Thomas Peterson, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar:
True In-memory Computing with the CRAM: From Technology to Applications. ACM Great Lakes Symposium on VLSI 2019: 379 - [c198]Qianqian Fan, David J. Lilja, Sachin S. Sapatnekar:
Using DCT-based Approximate Communication to Improve MPI Performance in Parallel Clusters. IPCCC 2019: 1-10 - [c197]Tonmoy Dhar, Sachin S. Sapatnekar:
Reliability Analysis of a Delay-Locked Loop Under HCI and BTI Degradation. IRPS 2019: 1-6 - [c196]Sachin S. Sapatnekar:
Electromigration-Aware Interconnect Design. ISPD 2019: 83-90 - [c195]Chaofan Li, Sachin S. Sapatnekar, Jiang Hu:
Fast Mapping-Based High-Level Synthesis of Pipelined Circuits. ISQED 2019: 33-38 - [c194]Masoud Zabihi, Zhengyang Zhao, D. C. Mahendra, Zamshed I. Chowdhury, Salonik Resch, Thomas Peterson, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar:
Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform. ISQED 2019: 52-57 - [c193]Vidya A. Chhabria, Sachin S. Sapatnekar:
Impact of Self-heating on Performance and Reliability in FinFET and GAAFET Designs. ISQED 2019: 235-240 - [c192]Luke R. Everson, Sachin S. Sapatnekar, Chris H. Kim:
A 40×40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient Control. ISSCC 2019: 50-52 - [c191]Lin Huang, I-Hong Hou, Sachin S. Sapatnekar, Jiang Hu:
Improving QoS for Global Dual-Criticality Scheduling on Multiprocessors. RTCSA 2019: 1-11 - 2018
- [c190]Lin Huang, Youmeng Li, Sachin S. Sapatnekar, Jiang Hu:
Using imprecise computing for improved non-preemptive real-time scheduling. DAC 2018: 71:1-71:6 - [c189]Shubham Jain, Sachin S. Sapatnekar, Jianping Wang, Kaushik Roy, Anand Raghunathan:
Computing-in-memory with spintronics. DATE 2018: 1640-1645 - [c188]Tengtao Li, Sachin S. Sapatnekar:
Strain-aware performance evaluation and correction for OTFT-based flexible displays. ICCAD 2018: 40 - [c187]Lin Huang, I-Hong Hou, Sachin S. Sapatnekar, Jiang Hu:
Graceful Degradation of Low-Criticality Tasks in Multiprocessor Dual-Criticality Systems. RTNS 2018: 159-169 - [c186]Marcel Urban, Sachin S. Sapatnekar, Richard Shi:
Plenaries. SMACD 2018: 1-2 - 2017
- [c185]Chaofan Li, Deepashree Sengupta, Farhana Sharmin Snigdha, Wenbin Xu, Jiang Hu, Sachin S. Sapatnekar:
A quantifiable approach to approximate computing: special session. CASES 2017: 1:1-1:2 - [c184]Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami:
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. DAC 2017: 16:1-16:6 - [c183]Vivek Mishra, Palkesh Jain, Sravan K. Marella, Sachin S. Sapatnekar:
Incorporating the Role of Stress on Electromigration in Power Grids with Via Arrays. DAC 2017: 21:1-21:6 - [c182]Deepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S. Sapatnekar:
SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits. DAC 2017: 72:1-72:6 - [c181]Robert Perricone, Ibrahim Ahmed, Zhaoxin Liang, Meghna G. Mankalale, Xiaobo Sharon Hu, Chris H. Kim, Michael T. Niemier, Sachin S. Sapatnekar, Jianping Wang:
Advanced spintronic memory and logic for non-volatile processors. DATE 2017: 972-977 - [c180]Tengtao Li, Sachin S. Sapatnekar:
Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs. ICCAD 2017: 645-650 - [c179]Wenbin Xu, Sachin S. Sapatnekar, Jiang Hu:
A simple yet efficient accuracy configurable adder design. ISLPED 2017: 1-6 - [c178]Qianqian Fan, Sachin S. Sapatnekar, David J. Lilja:
Cost-quality trade-offs of approximate memory repair mechanisms for image data. ISQED 2017: 438-444 - 2016
- [c177]Zhaoxin Liang, Meghna G. Mankalale, Brandon Del Bel, Sachin S. Sapatnekar:
Logic and memory design using spin-based circuits. ASP-DAC 2016: 103-108 - [c176]Jordi Cortadella, Marc Lupon, Alberto Moreno, Antoni Roca, Sachin S. Sapatnekar:
Ring Oscillator Clocks and Margins. ASYNC 2016: 19-26 - [c175]Deepashree Sengupta, Vivek Mishra, Sachin S. Sapatnekar:
Invited - Optimizing device reliability effects at the intersection of physics, circuits, and architecture. DAC 2016: 31:1-31:6 - [c174]Vivek Mishra, Sachin S. Sapatnekar:
Predicting electromigration mortality under temperature and product lifetime specifications. DAC 2016: 43:1-43:6 - [c173]Farhana Sharmin Snigdha, Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar:
Optimal design of JPEG hardware under the approximate computing paradigm. DAC 2016: 106:1-106:6 - [c172]Chaofan Li, Sachin S. Sapatnekar, Jiang Hu:
Control synthesis and delay sensor deployment for efficient ASV designs. ICCAD 2016: 64 - 2015
- [c171]Palkesh Jain, Sachin S. Sapatnekar, Jordi Cortadella:
A retargetable and accurate methodology for logic-IP-internal electromigration assessment. ASP-DAC 2015: 346-351 - [c170]Chaofan Li, Wei Luo, Sachin S. Sapatnekar, Jiang Hu:
Joint precision optimization and high level synthesis for approximate computing. DAC 2015: 104:1-104:6 - [c169]Deepashree Sengupta, Sachin S. Sapatnekar:
FEMTO: Fast Error Analysis in Multipliers through Topological Traversal. ICCAD 2015: 294-299 - [c168]Sravan K. Marella, Amit Ranjan Trivedi, Saibal Mukhopadhyay, Sachin S. Sapatnekar:
Optimization of FinFET-based circuits using a dual gate pitch technique. ICCAD 2015: 758-763 - [c167]Jordi Cortadella, Luciano Lavagno, Pedro Lopez, Marc Lupon, Alberto Moreno, Antoni Roca, Sachin S. Sapatnekar:
Reactive clocks with variability-tracking jitter. ICCD 2015: 511-518 - [c166]Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar:
Impact on performance, power, area and wirelength using electromigration-aware cells. ICECS 2015: 129-132 - [c165]Palkesh Jain, Sachin S. Sapatnekar, Jordi Cortadella:
Stochastic and topologically aware electromigration analysis for clock skew. IRPS 2015: 3 - [c164]Vivek Mishra, Sachin S. Sapatnekar:
Circuit delay variability due to wire resistance evolution under AC electromigration. IRPS 2015: 3 - [c163]Gracieli Posser, Lucas de Paris, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar:
Reducing the signal Electromigration effects on different logic gates by cell layout optimization. LASCAS 2015: 1-4 - 2014
- [c162]Deepashree Sengupta, Sachin S. Sapatnekar:
Predicting circuit aging using ring oscillators. ASP-DAC 2014: 430-435 - [c161]Brandon Del Bel, Jongyeon Kim, Chris H. Kim, Sachin S. Sapatnekar:
Improving STT-MRAM density through multibit error correction. DATE 2014: 1-6 - [c160]Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar:
A systematic approach for analyzing and optimizing cell-internal signal electromigration. ICCAD 2014: 486-491 - [c159]Deepashree Sengupta, Sachin S. Sapatnekar:
ReSCALE: recalibrating sensor circuits for aging and lifetime estimation under BTI. ICCAD 2014: 492-497 - [c158]Gracieli Posser, Vivek Mishra, Ricardo Augusto da Luz Reis, Sachin S. Sapatnekar:
Analyzing the electromigration effects on different metal layers and different wire lengths. ICECS 2014: 682-685 - [c157]Jieming Yin, Pingqiang Zhou, Sachin S. Sapatnekar, Antonia Zhai:
Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for Heterogeneous Multicore Systems. IPDPS 2014: 293-303 - [c156]Ayan Paul, Chaitanya Kshirsagar, Sachin S. Sapatnekar, Steven J. Koester, Chris H. Kim:
Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations. VLSID 2014: 399-404 - 2013
- [c155]Vivek Mishra, Sachin S. Sapatnekar:
The impact of electromigration in copper interconnects on power grid integrity. DAC 2013: 88:1-88:6 - [c154]Pingqiang Zhou, Vivek Mishra, Sachin S. Sapatnekar:
Placement optimization of power supply pads based on locality. DATE 2013: 1655-1660 - [c153]Yaoguang Wei, Zhuo Li, Cliff C. N. Sze, Shiyan Hu, Charles J. Alpert, Sachin S. Sapatnekar:
CATALYST: planning layer directives for effective design closure. DATE 2013: 1873-1878 - [c152]Sravan K. Marella, Sachin S. Sapatnekar:
The impact of shallow trench isolation effects on circuit performance. ICCAD 2013: 289-294 - [c151]Sachin S. Sapatnekar:
What happens when circuits grow old: Aging issues in CMOS design. VLSI-DAT 2013: 1-2 - 2012
- [c150]Baktash Boghrati, Sachin S. Sapatnekar:
Incremental power network analysis using backward random walks. ASP-DAC 2012: 41-46 - [c149]Saket Gupta, Sachin S. Sapatnekar:
GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation. ASP-DAC 2012: 271-276 - [c148]Jianxin Fang, Sachin S. Sapatnekar:
The impact of hot carriers on timing in large circuits. ASP-DAC 2012: 591-596 - [c147]Saket Gupta, Sachin S. Sapatnekar:
BTI-aware design using variable latency units. ASP-DAC 2012: 775-780 - [c146]Ayan Paul, Matt Amrein, Saket Gupta, Arvind Vinod, Abhishek Arun, Sachin S. Sapatnekar, Chris H. Kim:
Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors. CICC 2012: 1-4 - [c145]Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar:
GLARE: global and local wiring aware routability evaluation. DAC 2012: 768-773 - [c144]Jianxin Fang, Saket Gupta, Sanjay V. Kumar, Sravan K. Marella, Vivek Mishra, Pingqiang Zhou, Sachin S. Sapatnekar:
Circuit reliability: From Physics to Architectures: Embedded tutorial paper. ICCAD 2012: 243-246 - [c143]Pingqiang Zhou, Won Ho Choi, Bongjin Kim, Chris H. Kim, Sachin S. Sapatnekar:
Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications. ICCAD 2012: 263-270 - [c142]Sravan K. Marella, Sanjay V. Kumar, Sachin S. Sapatnekar:
A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations. ICCAD 2012: 317-324 - [c141]N. Kumaraguruparan, H. Sivaramakrishnan, Sachin S. Sapatnekar:
Residential task scheduling under dynamic pricing using the multiple knapsack method. ISGT 2012: 1-6 - [c140]Jieming Yin, Pingqiang Zhou, Anup Holey, Sachin S. Sapatnekar, Antonia Zhai:
Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems. ISLPED 2012: 57-62 - 2011
- [c139]Jianxin Fang, Sachin S. Sapatnekar:
Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability. ASP-DAC 2011: 689-694 - [c138]Pingqiang Zhou, Dong Jiao, Chris H. Kim, Sachin S. Sapatnekar:
Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network. CICC 2011: 1-4 - [c137]Jaeha Kung, Inhak Han, Sachin S. Sapatnekar, Youngsoo Shin:
Thermal signature: a simple yet accurate thermal index for floorplan optimization. DAC 2011: 108-113 - [c136]Baktash Boghrati, Sachin S. Sapatnekar:
A scaled random walk solver for fast power grid analysis. DATE 2011: 38-43 - [c135]T. Kolpe, Antonia Zhai, Sachin S. Sapatnekar:
Enabling improved power management in multicore processors through clustered DVFS. DATE 2011: 293-298 - [c134]Sachin S. Sapatnekar:
The whys and hows of thermal management. ISLPED 2011: 283-284 - [c133]Pingqiang Zhou, Jieming Yin, Antonia Zhai, Sachin S. Sapatnekar:
NoC frequency scaling with flexible-pipeline routers. ISLPED 2011: 403-408 - 2010
- [c132]Saket Gupta, Sachin S. Sapatnekar:
Current source modeling in the presence of body bias. ASP-DAC 2010: 199-204 - [c131]Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar:
Application-specific 3D Network-on-Chip design using simulated allocation. ASP-DAC 2010: 517-522 - [c130]Yaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapatnekar:
Physical design techniques for optimizing RTA-induced variations. ASP-DAC 2010: 745-750 - [c129]Baktash Boghrati, Sachin S. Sapatnekar:
Incremental solution of power grids using random walks. ASP-DAC 2010: 757-762 - [c128]Haifeng Qian, Sachin S. Sapatnekar:
Fast Poisson solvers for thermal analysis. ICCAD 2010: 698-702 - [c127]Sachin S. Sapatnekar:
Adding a new dimension to physical design. ISPD 2010: 55 - [c126]Yaoguang Wei, Sachin S. Sapatnekar:
Dummy fill optimization for enhanced manufacturability. ISPD 2010: 97-104 - [c125]Jianxin Fang, Sachin S. Sapatnekar:
Scalable methods for the analysis and optimization of gate oxide breakdown. ISQED 2010: 638-645 - 2009
- [c124]Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar:
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors. ASP-DAC 2009: 179-184 - [c123]Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
Adaptive techniques for overcoming performance degradation due to aging in digital circuits. ASP-DAC 2009: 284-289 - [c122]Sachin S. Sapatnekar:
Addressing thermal and power delivery bottlenecks in 3D circuits. ASP-DAC 2009: 423-428 - [c121]Qunzeng Liu, Sachin S. Sapatnekar:
Synthesizing a representative critical path for post-silicon delay prediction. ISPD 2009: 183-190 - 2008
- [c120]Sachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou:
Reinventing EDA with manycore processors. DAC 2008: 126-127 - [c119]Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang:
A progressive-ILP based routing algorithm for cross-referencing biochips. DAC 2008: 284-289 - [c118]Sanjay V. Kumar, Chandramouli V. Kashyap, Sachin S. Sapatnekar:
A framework for block-based timing sensitivity analysis. DAC 2008: 688-693 - 2007
- [c117]Jie Gu, Sachin S. Sapatnekar, Chris H. Kim:
Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift. DAC 2007: 87-92 - [c116]Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
NBTI-Aware Synthesis of Digital Circuits. DAC 2007: 370-375 - [c115]Qunzeng Liu, Sachin S. Sapatnekar:
Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations. DAC 2007: 497-502 - [c114]Brent Goplen, Sachin S. Sapatnekar:
Placement of 3D ICs with Thermal and Interlayer Via Considerations. DAC 2007: 626-631 - [c113]Felipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis:
DAG based library-free technology mapping. ACM Great Lakes Symposium on VLSI 2007: 293-298 - [c112]Sachin S. Sapatnekar:
Computer-aided design of 3d integrated circuits. ACM Great Lakes Symposium on VLSI 2007: 317 - [c111]Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan:
Clustering based pruning for statistical criticality computation under process variations. ICCAD 2007: 340-343 - [c110]Dmitry Bufistov, Jordi Cortadella, Michael Kishinevsky, Sachin S. Sapatnekar:
A general model for performance optimization of sequential systems. ICCAD 2007: 362-369 - [c109]Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar:
Module assignment for pin-limited designs under the stacked-Vdd paradigm. ICCAD 2007: 656-659 - [c108]Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi:
Probabilistic Congestion Prediction with Partial Blockages. ISQED 2007: 841-846 - 2006
- [c107]Yong Zhan, Brent Goplen, Sachin S. Sapatnekar:
Electrothermal analysis and optimization techniques for nanoscale integrated circuits. ASP-DAC 2006: 219-222 - [c106]Tianpei Zhang, Yong Zhan, Sachin S. Sapatnekar:
Temperature-aware routing in 3D ICs. ASP-DAC 2006: 309-314 - [c105]Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. ASP-DAC 2006: 559-564 - [c104]Yong Zhan, Yan Feng, Sachin S. Sapatnekar:
A fixed-die floorplanning algorithm using an analytical approach. ASP-DAC 2006: 771-776 - [c103]Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim:
Width Quantization Aware FinFET Circuit Design. CICC 2006: 337-340 - [c102]Jaskirat Singh, Sachin S. Sapatnekar:
Statistical timing analysis with correlated non-gaussian parameters using independent component analysis. DAC 2006: 155-160 - [c101]John Keane, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim:
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. DAC 2006: 425-428 - [c100]Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
An analytical model for negative bias temperature instability. ICCAD 2006: 493-496 - [c99]Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar:
Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis. ISLPED 2006: 298-303 - [c98]Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar:
Comparing simulation techniques for microarchitecture-aware floorplanning. ISPASS 2006: 80-88 - [c97]Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar:
Tutorial II: Variability and Its Impact on Design. ISQED 2006: 5 - [c96]Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
Impact of NBTI on SRAM Read Stability and Design for Reliability. ISQED 2006: 210-218 - [c95]Leomar S. da Rosa Jr., Felipe S. Marques, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis:
Fast disjoint transistor networks from BDDs. SBCCI 2006: 137-142 - 2005
- [c94]Tianpei Zhang, Sachin S. Sapatnekar:
Buffering global interconnects in structured ASIC design. ASP-DAC 2005: 23-26 - [c93]Yong Zhan, Sachin S. Sapatnekar:
Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up. ASP-DAC 2005: 87-92 - [c92]Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, Sachin S. Sapatnekar:
Robust gate sizing by geometric programming. DAC 2005: 315-320 - [c91]Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar:
Net weighting to reduce repeater counts during placement. DAC 2005: 503-508 - [c90]Hongliang Chang, Sachin S. Sapatnekar:
Full-chip analysis of leakage power under process variations, including spatial correlations. DAC 2005: 523-528 - [c89]Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar:
Microarchitecture-aware floorplanning using a statistical design of experiments approach. DAC 2005: 579-584 - [c88]Felipe S. Marques, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis:
A new approach to the use of satisfiability in false path detection. ACM Great Lakes Symposium on VLSI 2005: 308-311 - [c87]Yong Zhan, Sachin S. Sapatnekar:
A high efficiency full-chip thermal simulation algorithm. ICCAD 2005: 635-638 - [c86]Haifeng Qian, Sachin S. Sapatnekar:
A hybrid linear equation solver and its application in quadratic placement. ICCAD 2005: 905-909 - [c85]Felipe Ribeiro Schneider, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis:
Exact lower bound for the number of switches in series to implement a combinational logic cell. ICCD 2005: 357-362 - [c84]Vidyasagar Nookala, Sachin S. Sapatnekar:
Designing optimized pipelined global interconnects: algorithms and methodology impact. ISCAS (1) 2005: 608-611 - [c83]Shrirang K. Karandikar, Sachin S. Sapatnekar:
Fast estimation of area-delay trade-offs in circuit sizing. ISCAS (4) 2005: 3575-3578 - [c82]Jaskirat Singh, Sachin S. Sapatnekar:
A fast algorithm for power grid design. ISPD 2005: 70-77 - [c81]Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar:
An efficient technology mapping algorithm targeting routing congestion under delay constraints. ISPD 2005: 137-144 - [c80]Brent Goplen, Sachin S. Sapatnekar:
Thermal via placement in 3D ICs. ISPD 2005: 167-174 - [c79]Sachin S. Sapatnekar, Jaijeet S. Roychowdhury, Ramesh Harjani:
High-Speed Interconnect Technology: On-Chip and Off-Chip. VLSI Design 2005: 7 - 2004
- [c78]Haifeng Qian, Sachin S. Sapatnekar:
Hierarchical random-walk algorithms for power grid analysis. ASP-DAC 2004: 499-504 - [c77]Yong Zhan, Ramesh Harjani, Sachin S. Sapatnekar:
On the selection of on-chip inductors for the optimal VCO design. CICC 2004: 277-280 - [c76]Vidyasagar Nookala, Sachin S. Sapatnekar:
A method for correcting the functionality of a wire-pipelined circuit. DAC 2004: 570-575 - [c75]Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar:
Tradeoffs between date oxide leakage and delay for dual Tox circuits. DAC 2004: 761-766 - [c74]Yong Zhan, Sachin S. Sapatnekar:
Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming. DATE 2004: 622-629 - [c73]Shrirang K. Karandikar, Sachin S. Sapatnekar:
Fast Comparisons of Circuit Implementations. DATE 2004: 910-915 - [c72]Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S. Sapatnekar:
A chip-level electrostatic discharge simulation strategy. ICCAD 2004: 315-318 - [c71]Shrirang K. Karandikar, Sachin S. Sapatnekar:
Logical effort based technology mapping. ICCAD 2004: 419-422 - [c70]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze:
Accurate estimation of global buffer delay within a floorplan. ICCAD 2004: 706-711 - [c69]Tianpei Zhang, Sachin S. Sapatnekar:
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. ICCD 2004: 93-98 - [c68]Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar:
Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits. ICCD 2004: 228-233 - [c67]Jaskirat Singh, Sachin S. Sapatnekar:
Topology optimization of structured power/ground networks. ISPD 2004: 116-123 - [c66]Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar:
Early-stage power grid analysis for uncertain working modes. ISPD 2004: 132-137 - [c65]Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang:
A predictive distributed congestion metric and its application to technology mapping. ISPD 2004: 210-217 - [c64]Hongliang Chang, Haifeng Qian, Sachin S. Sapatnekar:
The Certainty of Uncertainty: Randomness in Nanometer Design. PATMOS 2004: 36-47 - [c63]Sachin S. Sapatnekar:
High-Performance Power Grids For Nanometer Technologies. VLSI Design 2004: 839-844 - 2003
- [c62]Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar:
Random walks in a supply network. DAC 2003: 93-98 - [c61]Brent Goplen, Sachin S. Sapatnekar:
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach. ICCAD 2003: 86-90 - [c60]Hongliang Chang, Sachin S. Sapatnekar:
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal. ICCAD 2003: 621-626 - [c59]Venkatesan Rajappan, Sachin S. Sapatnekar:
An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk. ICCD 2003: 76- - [c58]Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar:
Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) 2003: 668-671 - [c57]Guoqiang Chen, Sachin S. Sapatnekar:
Partition-driven standard cell thermal placement. ISPD 2003: 75-80 - 2002
- [c56]Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif:
Congestion-driven codesign of power and signal networks. DAC 2002: 64-69 - [c55]Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar:
A precorrected-FFT method for simulating on-chip inductance. ICCAD 2002: 221-227 - [c54]Mahesh Ketkar, Sachin S. Sapatnekar:
Standby power optimization via transistor sizing and dual threshold voltage assignment. ICCAD 2002: 375-378 - [c53]Haitian Hu, Sachin S. Sapatnekar:
Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques. ICCD 2002: 434- - [c52]Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif:
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts. ISPD 2002: 68-73 - [c51]Rupesh S. Shelar, Sachin S. Sapatnekar:
Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits. IWLS 2002: 209-214 - [c50]Tianpei Zhang, Sachin S. Sapatnekar:
Optimized pin assignment for lower routing congestion after floorplanning phase. SLIP 2002: 17-21 - [c49]Rupesh S. Shelar, Sachin S. Sapatnekar:
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. ASP-DAC/VLSI Design 2002: 87-92 - 2001
- [c48]Haitian Hu, Sachin S. Sapatnekar:
Circuit-aware on-chip inductance extraction. CICC 2001: 245-248 - [c47]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia:
A Practical Methodology for Early Buffer and Wire Resource Allocation. DAC 2001: 189-194 - [c46]Min Zhao, Sachin S. Sapatnekar:
A New Structural Pattern Matching Algorithm for Technology Mapping. DAC 2001: 371-376 - [c45]Shrirang K. Karandikar, Sachin S. Sapatnekar:
Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect. DAC 2001: 377-382 - [c44]Haihua Su, Sachin S. Sapatnekar:
Hybrid Structured Clock Network Construction. ICCAD 2001: 333-336 - [c43]Rupesh S. Shelar, Sachin S. Sapatnekar:
Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits. ICCAD 2001: 449-452 - [c42]Jiang Hu, Sachin S. Sapatnekar:
Performance Driven Global Routing Through Gradual Refinement. ICCD 2001: 481-483 - [c41]Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar:
Steiner tree optimization for buffers. Blockages and bays. ISCAS (5) 2001: 399-402 - [c40]Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia:
Buffered Steiner trees for difficult instances. ISPD 2001: 4-9 - [c39]Noel Menezes, Sachin S. Sapatnekar:
Optimization and Analysis Techniques for the Deep Submicron Regime. VLSI Design 2001: 3-4 - 2000
- [c38]Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David T. Blaauw:
Hierarchical analysis of power distribution networks. DAC 2000: 150-155 - [c37]Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi:
MINFLOTRANSIT: min-cost flow based transistor sizing tool. DAC 2000: 649-664 - [c36]Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar:
Convex delay models for transistor sizing. DAC 2000: 655-660 - [c35]Jiang Hu, Sachin S. Sapatnekar:
A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. ICCAD 2000: 99-103 - [c34]Haihua Su, Kaushik Gala, Sachin S. Sapatnekar:
Fast Analysis and Optimization of Power/Ground Networks. ICCAD 2000: 477-480 - [c33]Min Zhao, Sachin S. Sapatnekar:
Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic. ISCAS 2000: 309-312 - [c32]Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert:
Datapath routing based on a decongestion metric. ISPD 2000: 122-127 - [c31]Sachin S. Sapatnekar:
Capturing the Effect of Crosstalk on Delay. VLSI Design 2000: 364-369 - 1999
- [c30]Jiang Hu, Sachin S. Sapatnekar:
FAR-DS: Full-Plane AWE Routing with Driver Sizing. DAC 1999: 84-89 - [c29]Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi:
Marsh: min-area retiming with setup and hold constraints. ICCAD 1999: 2-6 - [c28]Yanbin Jiang, Sachin S. Sapatnekar:
An integrated algorithm for combined placement and libraryless technology mapping. ICCAD 1999: 102-106 - [c27]Min Zhao, Sachin S. Sapatnekar:
Timing-driven partitioning for two-phase domino and mixed static/domino implementations. ICCAD 1999: 107-110 - [c26]Martin Kuhlmann, Sachin S. Sapatnekar, Keshab K. Parhi:
Efficient Crosstalk Estimation. ICCD 1999: 266- - [c25]Jatuchai Pangjun, Sachin S. Sapatnekar:
Clock distribution using multiple voltages. ISLPED 1999: 145-150 - [c24]Jiang Hu, Sachin S. Sapatnekar:
Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model. ISPD 1999: 133-138 - 1998
- [c23]Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim:
Combined transistor sizing with buffer insertion for timing optimization. CICC 1998: 605-608 - [c22]Naresh Maheshwari, Sachin S. Sapatnekar:
Efficient Minarea Retiming of Large Level-Clocked Circuits. DATE 1998: 840-845 - [c21]Min Zhao, Sachin S. Sapatnekar:
Technology mapping for domino logic. ICCAD 1998: 248-251 - [c20]Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji:
A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic. ICCD 1998: 276-281 - [c19]Huibo Hou, Sachin S. Sapatnekar:
Routing tree topology construction to meet interconnect timing constraints. ISPD 1998: 205-210 - 1997
- [c18]Naresh Maheshwari, Sachin S. Sapatnekar:
An Improved Algorithm for Minimum-Area Retiming. DAC 1997: 2-7 - [c17]Naresh Maheshwari, Sachin S. Sapatnekar:
Minimum area retiming with equivalent initial states. ICCAD 1997: 216-219 - [c16]Juho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar:
Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs. ISPD 1997: 130-135 - 1996
- [c15]Daksh Lehther, Sachin S. Sapatnekar:
Clock tree synthesis for multi-chip modules. ICCAD 1996: 50-53 - [c14]Naresh Maheshwari, Sachin S. Sapatnekar:
A Practical Algorithm for Retiming Level-Clocked Circuits. ICCD 1996: 440-445 - [c13]Jatan C. Shah, Sachin S. Sapatnekar:
Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs. VLSI Design 1996: 346-351 - 1995
- [c12]Rahul B. Deokar, Sachin S. Sapatnekar:
A Fresh Look at Retiming Via Clock Skew Optimization. DAC 1995: 310-315 - [c11]Sachin S. Sapatnekar, Weitong Chuang:
Power vs. delay in gate sizing: conflicting objectives? ICCAD 1995: 463-466 - [c10]Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn:
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. ICCAD 1995: 467-470 - [c9]Piyush K. Sancheti, Sachin S. Sapatnekar:
Layout Optimization Using Arbitrarily High Degree Posynomial Models. ISCAS 1995: 53-56 - 1994
- [c8]Sachin S. Sapatnekar:
RC Interconnect Optimization Under the Elmore Delay Model. DAC 1994: 387-391 - [c7]Shankar Ramaswamy, Sachin S. Sapatnekar, Prithviraj Banerjee:
A Convex Programming Approach for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers. ICPP (2) 1994: 116-125 - [c6]Jaewon Kim, Sung-Mo Kang, Sachin S. Sapatnekar:
High Performance CMOS Macromodule Layout Synthesis. ISCAS 1994: 179-182 - [c5]Rahul B. Deokar, Sachin S. Sapatnekar:
A Graph-Theoretic Approach to Clock Skew Optimization. ISCAS 1994: 407-410 - 1993
- [c4]Sachin S. Sapatnekar, Pravin M. Vaidya, Steve M. Kang:
Convexity-based algorithms for design centering. ICCAD 1993: 206-209 - [c3]Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj:
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. ICCAD 1993: 220-223 - [c2]Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang:
Feasible Region Approximation Using Convex Polytopes. ISCAS 1993: 1786-1789 - 1991
- [c1]Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya:
A Convex Optimization Approach to Transistor Sizing for CMOS Circuits. ICCAD 1991: 482-485
Parts in Books or Collections
- 2019
- [p2]Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar:
Error Analysis and Optimization in Approximate Arithmetic Circuits. Approximate Circuits 2019: 225-246 - 2011
- [p1]Sachin S. Sapatnekar:
Statistical Design of Integrated Circuits. Low-Power Variation-Tolerant Design in Nanometer Silicon 2011: 109-149
Editorship
- 2010
- [e4]Sachin S. Sapatnekar:
Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010. ACM 2010, ISBN 978-1-4503-0002-5 [contents] - 2008
- [e3]Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar:
Handbook of Algorithms for Physical Design Automation. Auerbach Publications 2008, ISBN 978-0-8493-7242-1 [contents] - 2002
- [e2]Sachin S. Sapatnekar, Massoud Pedram:
Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002. ACM 2002, ISBN 1-58113-460-6 [contents] - 2001
- [e1]Sachin S. Sapatnekar, Manfred Wiesel:
Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001. ACM 2001, ISBN 1-58113-347-2 [contents]
Reference Works
- 2016
- [r5]Sachin S. Sapatnekar:
Power Grid Analysis. Encyclopedia of Algorithms 2016: 1598-1601 - [r4]Sachin S. Sapatnekar:
Statistical Timing Analysis. Encyclopedia of Algorithms 2016: 2095-2099 - 2008
- [r3]Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar:
Introduction to Physical Design. Handbook of Algorithms for Physical Design Automation 2008 - [r2]Kia Bazargan, Sachin S. Sapatnekar:
Physical Design for Three-Dimensional Circuits. Handbook of Algorithms for Physical Design Automation 2008 - [r1]Frank Liu, Sachin S. Sapatnekar:
Metrics Used in Physical Design. Handbook of Algorithms for Physical Design Automation 2008
Data and Artifacts
- 2024
- [d1]Hüsrev Cilasun, William Moy, Ziqing Zeng, Tahmida Islam, Hao Lo, Alex Vanasse, Megan Tan, Mohammad Anees, Ramprasath S, Abhimanyu Kumar, Sachin S. Sapatnekar, Chris H. Kim, Ulya R. Karpuzcu:
COBI: A Coupled Oscillator Based Ising Chip for Combinatorial Optimization. Zenodo, 2024
Informal and Other Publications
- 2024
- [i27]Vidya A. Chhabria, Wenjing Jiang, Sachin S. Sapatnekar:
IR-Aware ECO Timing Optimization Using Reinforcement Learning. CoRR abs/2402.07781 (2024) - 2023
- [i26]Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar:
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route. CoRR abs/2305.06917 (2023) - [i25]Vidya A. Chhabria, Chetan Choppali Sudarshan, Sarma B. K. Vrudhula, Sachin S. Sapatnekar:
Towards Sustainable Computing: Assessing the Carbon Footprint of Heterogeneous Systems. CoRR abs/2306.09434 (2023) - [i24]Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Sean Kinzer, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang:
Performance Analysis of DNN Inference/Training with Convolution and non-Convolution Operations. CoRR abs/2306.16767 (2023) - [i23]Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng:
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators. CoRR abs/2308.12120 (2023) - [i22]M. Hüsrev Cilasun, Ziqing Zeng, Ramprasath S, Abhimanyu Kumar, Hao Lo, William Cho, Chris H. Kim, Ulya R. Karpuzcu, Sachin S. Sapatnekar:
3SAT on an All-to-All-Connected CMOS Ising Solver Chip. CoRR abs/2309.11017 (2023) - [i21]Yang Lv, Brandon R. Zink, Robert P. Bloom, M. Hüsrev Cilasun, Pravin Khanal, Salonik Resch, Zamshed I. Chowdhury, Ali Habiboglu, Weigang Wang, Sachin S. Sapatnekar, Ulya R. Karpuczu, Jianping Wang:
Experimental demonstration of magnetic tunnel junction-based computational random-access memory. CoRR abs/2312.14264 (2023) - 2022
- [i20]M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Yang Lv, Brandon Zink, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
Error Detection and Correction for Processing in Memory (PiM). CoRR abs/2207.13261 (2022) - 2021
- [i19]Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar:
A New, Computationally Efficient "Blech Criterion" for Immortality in General Interconnects. CoRR abs/2105.08784 (2021) - [i18]Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Sachin S. Sapatnekar:
GNNIE: GNN Inference Engine with Load-balancing and Graph-Specific Caching. CoRR abs/2105.10554 (2021) - [i17]Masoud Zabihi, Salonik Resch, M. Hüsrev Cilasun, Zamshed I. Chowdhury, Zhengyang Zhao, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar:
Exploring the Feasibility of Using 3D XPoint as an In-Memory Computing Accelerator. CoRR abs/2106.08402 (2021) - [i16]Vidya A. Chhabria, Sachin S. Sapatnekar:
OpeNPDN: A Neural-network-based Framework for Power Delivery Network Synthesis. CoRR abs/2110.14184 (2021) - [i15]Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar:
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks. CoRR abs/2110.14197 (2021) - [i14]Salonik Resch, Zamshed I. Chowdhury, M. Hüsrev Cilasun, Masoud Zabihi, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
Towards Homomorphic Inference Beyond the Edge. CoRR abs/2112.08943 (2021) - [i13]Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar:
A Linear-Time Algorithm for Steady-State Analysis of Electromigration in General Interconnects. CoRR abs/2112.13451 (2021) - 2020
- [i12]M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Keshab K. Parhi, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
An Inference and Learning Engine for Spiking Neural Networks in Computational RAM (CRAM). CoRR abs/2006.03007 (2020) - [i11]Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Sachin S. Sapatnekar, Soner Yaldiz:
ALIGN: A System for Automating Analog Layout. CoRR abs/2008.10682 (2020) - [i10]Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar:
Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks. CoRR abs/2009.09009 (2020) - [i9]Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar:
A general approach for identifying hierarchical symmetry constraints for analog circuit layout. CoRR abs/2010.00051 (2020) - [i8]Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar:
MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification. CoRR abs/2012.10597 (2020) - 2019
- [i7]Susmita Dey Manasi, Farhana Sharmin Snigdha, Sachin S. Sapatnekar:
NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile Clients. CoRR abs/1905.05011 (2019) - [i6]Salonik Resch, S. Karen Khatamifard, Zamshed Iqbal Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
A Machine Learning Accelerator In-Memory for Energy Harvesting. CoRR abs/1908.11373 (2019) - 2018
- [i5]Meghna G. Mankalale, Zhengyang Zhao, Jianping Wang, Sachin S. Sapatnekar:
SkyLogic - A proposal for a skyrmion logic device. CoRR abs/1811.02016 (2018) - [i4]Salonik Resch, S. Karen Khatamifard, Zamshed Iqbal Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
Exploiting Processing in Non-Volatile Memory for Binary Neural Network Accelerators. CoRR abs/1812.03989 (2018) - [i3]Zamshed I. Chowdhury, S. Karen Khatamifard, Zhengyang Zhao, Masoud Zabihi, Salonik Resch, Meisam Razaviyayn, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
Computational RAM to Accelerate String Matching at Scale. CoRR abs/1812.08918 (2018) - 2016
- [i2]Meghna G. Mankalale, Zhaoxin Liang, Sachin S. Sapatnekar:
STEM: A Scheme for Two-phase Evaluation of Majority Logic. CoRR abs/1609.05141 (2016) - [i1]Meghna G. Mankalale, Zhaoxin Liang, Zhengyang Zhao, Chris H. Kim, Jianping Wang, Sachin S. Sapatnekar:
CoMET: Composite-Input Magnetoelectric-based Logic Technology. CoRR abs/1611.09714 (2016)
Coauthor Index
Zamshed I. Chowdhury
aka: Zamshed Iqbal Chowdhury
aka: Zamshed Iqbal Chowdhury
M. Hüsrev Cilasun
aka: Hüsrev Cilasun
aka: Hüsrev Cilasun
[j134] [j131] [j126] [j123] [j118] [j117] [j114] [j53] [j39] [j33] [j27] [j23] [j22] [j21] [j18] [j12] [c241] [c237] [c230] [c225] [c220] [c216] [c215] [c211] [c210] [c208] [c207] [c205] [c203] [c201] [c195] [c191] [c190] [c187] [c185] [c182] [c179] [c173] [c172] [c170] [c130] [c70] [c56] [c47] [c42] [c41] [c40] [c35] [c30] [c24] [p2] [i11]
Arvind K. Sharma
aka: Arvind Kumar Sharma
aka: Arvind Kumar Sharma
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