


default search action
ASP-DAC 2005: Shanghai, China
- Tingao Tang:
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005. ACM Press 2005, ISBN 0-7803-8737-6
Keynote address
- Rajeev Madhavan:
Silicon compilation: the answer to reducing IC development costs. - Jan M. Rabaey:
Design at the end of the silicon roadmap. - Zhenghua Jiang:
The development of integrated circuit industry in China.
Tree construction and buffering
- Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan:
The polygonal contraction heuristic for rectilinear Steiner tree construction. 1-6 - Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan:
An-OARSMan: obstacle-avoiding routing tree construction with good length performance. 7-12 - Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Making fast buffer insertion even faster via approximation techniques. 13-18 - Zhong-Ching Lu, Ting-Chi Wang:
Concurrent flip-flop and buffer insertion with adaptive blockage avoidance. 19-22 - Tianpei Zhang, Sachin S. Sapatnekar:
Buffering global interconnects in structured ASIC design. 23-26
System level design methodology for network-on-chip
- Srinivasan Murali, Luca Benini, Giovanni De Micheli:
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees. 27-32 - César A. M. Marcon
, André Borin Suarez, Altamiro Amadeu Susin, Luigi Carro, Flávio Rech Wagner:
Time and energy efficient mapping of embedded applications onto NoCs. 33-38 - Liang-Yu Lin, Cheng-Yeh Wang, Pao-Jui Huang, Chih-Chieh Chou, Jing-Yang Jou:
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip. 39-44 - Andreas Gerstlauer, Dongwan Shin, Rainer Dömer, Daniel D. Gajski:
System-level communication modeling for network-on-chip synthesis. 45-48 - Luciano Ost, Aline Mello, José Palma, Fernando Gehm Moraes
, Ney Calazans:
MAIA: a framework for networks on chip generation and verification. 49-52
Test and DFT (1)
- Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li:
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. 53-58 - Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty
:
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation. 59-64 - Jin-Fu Li:
Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs. 65-70 - Feng Shi, Yiorgos Makris:
SPIN-PAC: test compaction for speed-independent circuits. 71-74 - Michihiro Shintani
, Toshihiro Ohara, Hideyuki Ichihara, Tomoo Inoue:
A Huffman-based coding with efficient test application. 75-78
DFM
- Vijay Pitchumani:
Embedded tutorial I: design for manufacturability. - Rouying Zhan, Haolu Xie, Haigang Feng, Albert Z. Wang:
ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress. 79-82 - Xiaolang Yan, Ye Chen, Zheng Shi, Yue Ma:
A new method for model based frugal OPC. 83-86
Clock, power grid and thermal analysis and optimization
- Yong Zhan, Sachin S. Sapatnekar:
Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up. 87-92 - Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan:
Analysis of buffered hybrid structured clock networks. 93-98 - Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu:
Clock network minimization methodology based on incremental placement. 99-102 - Hongyu Chen, Chung-Kuan Cheng:
A multi-level transmission line network approach for multi-giga hertz clock distribution. 103-106 - Zhixin Tian, Huazhong Yang, Rong Luo:
Gibbs sampling in power grid analysis. 107-110 - Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan:
A wideband hierarchical circuit reduction for massively coupled interconnects. 111-114
Routing and interconnects
- Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong
, Lei He:
A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem. 115-120 - Jason Cong, Yan Zhang:
Thermal-driven multilevel routing for 3-D ICs. 121-126 - Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen:
Wave-pipelined on-chip global interconnect. 127-132 - Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu
:
Evaluation of on-chip transmission line interconnect using wire length distribution. 133-138
System level modeling and embedded software
- Samar Abdi, Daniel Gajski:
A formalism for functionality preserving system level transformations. 139-144 - KiSeun Kwon, Youngmin Yi, Dohyung Kim, Soonhoi Ha:
Embedded software generation from system level specification for multi-tasking embedded systems. 145-150 - Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya:
Scheduler implementation in MP SoC design. 151-156 - G. Chen, Mahmut T. Kandemir:
Optimizing embedded applications using programmer-inserted hints. 157-160 - Dohyung Kim, Soonhoi Ha:
Static analysis and automatic code synthesis of flexible FSM model. 161-165
Test and DFT (2)
- Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Cheng
:
Constraint extraction for pseudo-functional scan-based delay testing. 166-171 - Hafizur Rahaman, Debesh K. Das:
Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA. 172-177 - Xijiang Lin, Janusz Rajski:
Propagation delay fault: a new fault model to test delay faults. 178-183 - Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
Oscillation ring based interconnect test scheme for SOC. 184-187 - Junhao Shi, Görschwin Fey, Rolf Drechsler:
Bridging fault testability of BDD circuits. 188-191
TCAD
- Debjit Sinha, Hai Zhou:
Yield driven gate sizing for coupling-noise reduction under uncertainty. 192-197 - Yun-Ru Wu, Ming-Chao Tsai, Ting-Chi Wang:
Maze routing with OPC consideration. 198-203 - Masahiro Murakawa, Mitiko Miura-Mattausch, Tetsuya Higuchi:
Towards automatic parameter extraction for surface-potential-based MOSFET models with the genetic algorithm. 204-207 - Xiren Wang, Wenjian Yu, Zeyi Wang:
Substrate resistance extraction with direct boundary element method. 208-211 - Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Meiling Wang:
An efficient combinationality check technique for the synthesis of cyclic combinational circuits. 212-215 - Ke Cao, Puneet Dhawan, Jiang Hu:
Library cell layout with Alt-PSM compliance and composability. 216-219 - Rasit Onur Topaloglu
, Alex Orailoglu:
Forward discrete probability propagation method for device performance characterization under process variations. 220-223
Simulation and modeling techniques for RF/analog circuits
- Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu, Lei He:
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction. 224-229 - Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri
, Georges G. E. Gielen:
Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. 230-235 - Xiaochun Duan, Kartikeya Mayaram:
A new approach for ring oscillator simulation using the harmonic balance method. 236-239 - Zhengyong Zhu, Khosro Rouz, Manjit Borah, Chung-Kuan Cheng, Ernest S. Kuh:
Efficient transient simulation for transistor-level analysis. 240-243 - Bang Liu, Xuan Zeng, Yangfeng Su, Jun Tao, Zhaojun Bai, Charles C. Chiang, Dian Zhou:
Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits. 244-249 - Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen:
Block based statistical timing analysis with extended canonical timing model. 250-253
Logic synthesis
- Lin Yuan, Gang Qu, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli:
FSM re-engineering and its application in low power state encoding. 254-259 - Aiqun Cao, Ruibing Lu, Cheng-Kok Koh:
Post-layout logic duplication for synthesis of domino circuits with complex gates. 260-265 - Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch:
Detecting support-reducing bound sets using two-cofactor symmetries. 266-271 - Vivek V. Shende
, Stephen S. Bullock, Igor L. Markov:
Synthesis of quantum logic circuits. 272-275 - Stephen Plaza, Valeria Bertacco:
STACCATO: disjoint support decompositions from BDDs through symbolic kernels. 276-279
System level architecture design
- Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel:
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. 280-285 - Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A processor core synthesis system in IP-based SoC design. 286-291 - Koushik Niyogi, Diana Marculescu
:
Speed and voltage selection for GALS systems based on voltage/frequency islands. 292-297 - Christian Haubelt, Stephan Otto, Cornelia Grabbe, Jürgen Teich:
A system-level approach to hardware reconfigurable systems. 298-301 - Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao
, Edwin Hsing-Mean Sha:
High-level synthesis for DSP applications using heterogeneous functional units. 302-304
Test and verification
- Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara:
Evaluation of the statistical delay quality model. 305-310 - Wenjing Rao, Alex Orailoglu, Ramesh Karri
:
Fault tolerant nanoelectronic processor architectures. 311-316 - Shireesh Verma, Kiran Ramineni, Ian G. Harris:
An efficient control-oriented coverage metric. 317-322 - Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou:
An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. 323-326 - Jin Yang, Avi Puder:
Tightly integrate dynamic verification with formal verification: a GSTE based approach. 327-330
Special Session
- Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen:
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?
Placement techniques
- Satoshi Ono, Patrick H. Madden:
On structure and suboptimality in placement. 331-336 - Pradeep Ramachandaran, Ameya R. Agnihotri, Satoshi Ono, Purushothaman Damodaran, Krishnaswami Srihari, Patrick H. Madden:
Optimal placement by branch-and-price. 337-342 - Puneet Gupta
, Andrew B. Kahng, Chul-Hong Park:
Detailed placement for improved depth of focus and CD control. 343-348 - Chen Li, Cheng-Kok Koh, Patrick H. Madden:
Floorplan management: incremental placement for gate sizing and buffer insertion. 349-354
Security processor design
- Yi-Ping You
, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiun Huang, TingTing Hwang, Sheng-Yu Hsu:
Low-power techniques for network security processors. 355-360 - Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu
:
A configurable AES processor for enhanced security. 361-366 - Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang:
Power estimation starategies for a low-power security processor. 367-371 - Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
:
Design and test of a scalable security processor. 372-375 - Yung-Chia Lin, Chung-Wen Huang, Jenq Kuen Lee:
System-level design space exploration for security processor prototyping in analytical approaches. 376-380
(Special session) embedded tutorial II
- David T. Blaauw, Anirudh Devgan, Farid N. Najm:
Leakage power: trends, analysis and avoidance.
(Special session) CAD for microarchitecture designs
- Bill Grundmann:
Challenges to covering the high-level to silicon gap. 1 - Todd M. Austin, Valeria Bertacco, David T. Blaauw, Trevor N. Mudge:
Opportunities and challenges for better than worst-case design. 2-7 - Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong:
Microarchitecture evaluation with floorplanning and interconnect pipelining. 8-15
University design contest
- Hongxia Wang, Samuel Rodríguez, Cagdas Dirik, Amol Gole, Vincent Chan, Bruce L. Jacob:
TERPS: the embedded reliable processing system. 1-2 - Dimitrios Soudris, Spiridon Nikolaidis, Stilianos Siskos, Konstantinos Tatas, Kostas Siozios, George Koutroumpezis, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Adonios Thanailakis:
AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. 3-4 - Hongyan Jian, Zhangwen Tang, Jie He, Jinglan He, Min Hao:
Standard CMOS technology on-chip inductors with pn junctions substrate isolation. 5-6 - Hao-Yun Chin, Chao-Chung Cheng, Yu-Kun Lin, Tian-Sheuan Chang:
A bandwidth efficient subsampling-based block matching architecture for motion estimation. 7-8 - Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera:
Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process. 9-10 - Chi Huang, Xinyu Wu, Jinmei Lai, Chengshou Sun, Gang Li:
A design of high speed double precision floating point adder using macro modules. 11-12 - Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jürgen Mattausch:
A low-power video segmentation LSI with boundary-active-only architecture. 13-14 - Ningyi Xu, Shaohua Li, Wei Yu, Guanghui He, Hao Zhang, Fei Luo, Zucheng Zhou:
The design and implementation of a DVB receiving chip with PCI interface. 15-16 - Dehui Zhang, Quan Liang Zhao, Jun Gang Han:
Design and implementation of an SDH high-speed switch. 17-18 - Arias Tanti Hapsari, Eniman Y. Syamsudin, Imron Pramana:
Design of vehicle position tracking system using short message services and its implementation on FPGA. 19-20 - Fei Wang, Jianyu Zhang, Xuan Wang, Jinmei Lai, Chengshou Sun:
Design of A 2.4-GHz integrated frequency synthesizer. 21-22 - Jianhua Feng, Jieyi Long, Wenhua Xu, Hongfei Ye:
An improved test access mechanism structure and optimization technique in system-on-chip. 23-24
(Special session) embedded tutorial III
- Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Designing reliable circuit in the presence of soft errors. 1
Design optimization for high-performance digital circuits
- Hsinwei Chou, Yu-Hao Wang, Charlie Chung-Ping Chen:
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation. 381-386 - Zhaojun Wo, Israel Koren:
Effective analytical delay model for transistor sizing. 387-392 - Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Anirudh Devgan:
Achieving continuous VT performance in a dual VT process. 393-398 - Dongwoo Lee, David T. Blaauw, Dennis Sylvester:
Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment. 399-404
Floorplanning and partitioning
- Lei Cheng, Liang Deng, Martin D. F. Wong
:
Floorplanning for 3-D VLSI design. 405-411 - Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong
:
Optimal redistribution of white space for wire length minimization. 412-417 - Yongseok Cheon, Martin D. F. Wong
:
Crowdedness-balanced multilevel partitioning for uniform resource utilization. 418-423 - Ramprasad Ravichandran, Michael T. Niemier, Sung Kyu Lim:
Partitioning and placement for buildable QCA circuits. 424-427 - Chanseok Hwang, Massoud Pedram:
PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits. 428-431
Advances in SAT technology and application
- Jinbo Huang:
MUP: a minimal unsatisfiability prover. 432-437 - Domagoj Babic, Alan J. Hu:
Integration of supercubing and learning in a SAT solver. 438-444 - Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah:
Dynamic symmetry-breaking for improved Boolean optimization. 445-450 - ShengYu Shen, Ying Qin, Sikun Li:
A fast counterexample minimization approach with refutation analysis and incremental SAT. 451-454 - Wei Huang, Pushan Tang, Min Ding:
Sequential equivalence checking using cuts. 455-458
Analysis and simulation techniques
- Xiaolue Lai, Yayun Wan, Jaijeet S. Roychowdhury:
Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise. 459-464 - Fang Liu, Sule Ozev:
Hierarchical analysis of process variation for mixed-signal systems. 465-470 - Xuan Zeng, Bang Liu, Jun Tao, Charles C. Chiang, Dian Zhou:
A novel wavelet method for noise analysis of nonlinear circuits. 471-476 - Mengmeng Ding, Glenn Wolfe, Ranga Vemuri:
An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels. 477-482
Interconnect modeling and analysis and system level design methodology
- Yu Du, Wayne Dai:
Partial reluctance based circuit simulation is efficient and stable. 483-488 - Krishnan Srinivasan, Karam S. Chatha:
SAGA: synthesis technique for guaranteed throughput NoC architectures. 489-494 - Sudeep Pasricha, Nikil D. Dutt
, Mohamed Ben-Romdhane:
Automated throughput-driven synthesis of bus-based communication architectures. 495-498 - Jae-Gon Lee
, Woo-Seung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung:
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks. 499-502 - Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Statistical modeling of cross-coupling effects in VLSI interconnects. 503-506 - Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh, Guoan Zhong:
Compact and stable modeling of partial inductance and reluctance matrices. 507-510