"A unified algorithm for gate sizing and clock skew optimization to ..."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj (1993)

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DOI: 10.1109/ICCAD.1993.580060

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj:
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. ICCAD 1993: 220-223

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